ARM: OMAP4: SMP: Add OMAP4430 SMP board files
This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This commit is contained in:
Santosh Shilimkar
46
arch/arm/mach-omap2/omap-headsmp.S
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46
arch/arm/mach-omap2/omap-headsmp.S
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/*
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* Secondary CPU startup routine source file.
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Interface functions needed for the SMP. This file is based on arm
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* realview smp platform.
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* Copyright (c) 2003 ARM Limited.
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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/* Physical address needed since MMU not enabled yet on secondary core */
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#define OMAP4_AUX_CORE_BOOT1_PA 0x48281804
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__INIT
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/*
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* OMAP4 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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* secondary core is held until we're ready for it to initialise.
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* The primary core will update the this flag using a hardware
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* register AuxCoreBoot1.
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*/
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ENTRY(omap_secondary_startup)
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #0x0f
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hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1
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ldr r2, [r1]
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cmp r2, r0
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bne hold
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/*
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* we've been released from the cpu_release,secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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178
arch/arm/mach-omap2/omap-smp.c
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178
arch/arm/mach-omap2/omap-smp.c
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/*
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* OMAP4 SMP source file. It contains platform specific fucntions
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* needed for the linux smp kernel.
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Platform file needed for the OMAP4 SMP. This file is based on arm
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* realview smp platform.
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* * Copyright (c) 2002 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/localtimer.h>
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#include <asm/smp_scu.h>
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#include <mach/hardware.h>
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/* Registers used for communicating startup information */
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#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800)
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#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804)
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/* SCU base address */
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static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE;
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/*
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* Use SCU config register to count number of cores
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*/
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static inline unsigned int get_core_count(void)
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{
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if (scu_base)
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return scu_get_core_count(scu_base);
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return 1;
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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trace_hardirqs_off();
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/*
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* If any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot1 with boot state for secondary core.
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* omap_secondary_startup() routine will hold the secondary core till
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* the AuxCoreBoot1 register is updated with cpu state
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* A barrier is added to ensure that write buffer is drained
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*/
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__raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1);
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smp_wmb();
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout))
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;
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/*
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return 0;
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}
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static void __init wakeup_secondary(void)
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{
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/*
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* Write the address of secondary startup routine into the
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* AuxCoreBoot0 where ROM code will jump and start executing
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* on secondary core once out of WFE
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* A barrier is added to ensure that write buffer is drained
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*/
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__raw_writel(virt_to_phys(omap_secondary_startup), \
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OMAP4_AUXCOREBOOT_REG0);
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smp_wmb();
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/*
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* Send a 'sev' to wake the secondary core from WFE.
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*/
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set_event();
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mb();
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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unsigned int i, ncores = get_core_count();
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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unsigned int ncores = get_core_count();
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unsigned int cpu = smp_processor_id();
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int i;
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/* sanity check */
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if (ncores == 0) {
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printk(KERN_ERR
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"OMAP4: strange core count of 0? Default to 1\n");
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ncores = 1;
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}
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if (ncores > NR_CPUS) {
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printk(KERN_WARNING
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"OMAP4: no. of cores (%d) greater than configured "
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"maximum of %d - clipping\n",
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ncores, NR_CPUS);
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ncores = NR_CPUS;
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}
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smp_store_cpu_info(cpu);
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/*
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* are we trying to boot more cores than exist?
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*/
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if (max_cpus > ncores)
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max_cpus = ncores;
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/*
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* Initialise the present map, which describes the set of CPUs
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* actually populated at the present time.
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*/
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for (i = 0; i < max_cpus; i++)
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set_cpu_present(i, true);
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if (max_cpus > 1) {
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/*
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* Enable the local timer or broadcast device for the
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* boot CPU, but only if we have more than one CPU.
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*/
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percpu_timer_setup();
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/*
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* Initialise the SCU and wake up the secondary core using
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* wakeup_secondary().
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*/
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scu_enable(scu_base);
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wakeup_secondary();
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}
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}
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51
arch/arm/plat-omap/include/mach/smp.h
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51
arch/arm/plat-omap/include/mach/smp.h
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@@ -0,0 +1,51 @@
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/*
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* OMAP4 machine specific smp.h
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Interface functions needed for the SMP. This file is based on arm
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* realview smp platform.
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* Copyright (c) 2003 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OMAP_ARCH_SMP_H
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#define OMAP_ARCH_SMP_H
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#include <asm/hardware/gic.h>
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/*
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* set_event() is used to wake up secondary core from wfe using sev. ROM
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* code puts the second core into wfe(standby).
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*
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*/
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#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
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/* Needed for secondary core boot */
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extern void omap_secondary_startup(void);
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/*
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* We use Soft IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask)
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{
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gic_raise_softirq(mask, 1);
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}
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/*
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* Read MPIDR: Multiprocessor affinity register
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*/
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#define hard_smp_processor_id() \
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({ \
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unsigned int cpunum; \
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__asm__("mrc p15, 0, %0, c0, c0, 5" \
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: "=r" (cpunum)); \
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cpunum &= 0x0F; \
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})
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#endif
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