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drm/i915: Restore missing command flush before interrupt on BLT ring

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We always skipped flushing the BLT ring if the request flush did not
include the RENDER domain. However, this neglects that we try to flush
the COMMAND domain after every batch and before the breadcrumb interrupt
(to make sure the batch is indeed completed prior to the interrupt
firing and so insuring CPU coherency). As a result of the missing flush,
incoherency did indeed creep in, most notable when using lots of command
buffers and so potentially rewritting an active command buffer (i.e.
the GPU was still executing from it even though the following interrupt
had already fired and the request/buffer retired).

As all ring->flush routines now have the same preconditions, de-duplicate
and move those checks up into i915_gem_flush_ring().

Fixes gem_linear_blit.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35284
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: mengmeng.meng@intel.com
This commit is contained in:
Chris Wilson
2011-03-19 22:26:49 +00:00
parent d4aeee7760
commit 36d527dead
2 changed files with 57 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/i915/i915_gem.c
View File

@@ -2219,13 +2219,18 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
{
int ret;
if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
return 0;
trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
ret = ring->flush(ring, invalidate_domains, flush_domains);
if (ret)
return ret;
if (flush_domains & I915_GEM_GPU_DOMAINS)
i915_gem_process_flushing_list(ring, flush_domains);
return 0;
}

11
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@@ -65,7 +65,6 @@ render_ring_flush(struct intel_ring_buffer *ring,
u32 cmd;
int ret;
if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
/*
* read/write caches:
*
@@ -120,7 +119,6 @@ render_ring_flush(struct intel_ring_buffer *ring,
intel_ring_emit(ring, cmd);
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
}
return 0;
}
@@ -568,9 +566,6 @@ bsd_ring_flush(struct intel_ring_buffer *ring,
{
int ret;
if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
return 0;
ret = intel_ring_begin(ring, 2);
if (ret)
return ret;
@@ -1056,9 +1051,6 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
uint32_t cmd;
int ret;
if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0)
return 0;
ret = intel_ring_begin(ring, 4);
if (ret)
return ret;
@@ -1230,9 +1222,6 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
uint32_t cmd;
int ret;
if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0)
return 0;
ret = blt_ring_begin(ring, 4);
if (ret)
return ret;