MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
Now that no driver any longer depends on the CONFIG_SOC_AU1??? symbols, it's time to get rid of them: Move some of the platform devices to the boards which can use them, Rename a few (unused) constants in the header, Replace them with MIPS_ALCHEMY in the various Kconfig files. Finally delete them altogether from the Alchemy Kconfig file. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
committed by
Ralf Baechle
Ralf Baechle
parent
50d5676eba
commit
3766386037
@@ -591,113 +591,6 @@ enum soc_au1200_ints {
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#endif /* !defined (_LANGUAGE_ASSEMBLY) */
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/*
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* SDRAM register offsets
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*/
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#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
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defined(CONFIG_SOC_AU1100)
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#define MEM_SDMODE0 0x0000
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#define MEM_SDMODE1 0x0004
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#define MEM_SDMODE2 0x0008
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#define MEM_SDADDR0 0x000C
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#define MEM_SDADDR1 0x0010
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#define MEM_SDADDR2 0x0014
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#define MEM_SDREFCFG 0x0018
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#define MEM_SDPRECMD 0x001C
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#define MEM_SDAUTOREF 0x0020
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#define MEM_SDWRMD0 0x0024
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#define MEM_SDWRMD1 0x0028
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#define MEM_SDWRMD2 0x002C
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#define MEM_SDSLEEP 0x0030
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#define MEM_SDSMCKE 0x0034
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/*
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* MEM_SDMODE register content definitions
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*/
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#define MEM_SDMODE_F (1 << 22)
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#define MEM_SDMODE_SR (1 << 21)
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#define MEM_SDMODE_BS (1 << 20)
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#define MEM_SDMODE_RS (3 << 18)
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#define MEM_SDMODE_CS (7 << 15)
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#define MEM_SDMODE_TRAS (15 << 11)
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#define MEM_SDMODE_TMRD (3 << 9)
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#define MEM_SDMODE_TWR (3 << 7)
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#define MEM_SDMODE_TRP (3 << 5)
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#define MEM_SDMODE_TRCD (3 << 3)
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#define MEM_SDMODE_TCL (7 << 0)
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#define MEM_SDMODE_BS_2Bank (0 << 20)
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#define MEM_SDMODE_BS_4Bank (1 << 20)
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#define MEM_SDMODE_RS_11Row (0 << 18)
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#define MEM_SDMODE_RS_12Row (1 << 18)
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#define MEM_SDMODE_RS_13Row (2 << 18)
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#define MEM_SDMODE_RS_N(N) ((N) << 18)
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#define MEM_SDMODE_CS_7Col (0 << 15)
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#define MEM_SDMODE_CS_8Col (1 << 15)
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#define MEM_SDMODE_CS_9Col (2 << 15)
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#define MEM_SDMODE_CS_10Col (3 << 15)
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#define MEM_SDMODE_CS_11Col (4 << 15)
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#define MEM_SDMODE_CS_N(N) ((N) << 15)
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#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
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#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
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#define MEM_SDMODE_TWR_N(N) ((N) << 7)
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#define MEM_SDMODE_TRP_N(N) ((N) << 5)
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#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
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#define MEM_SDMODE_TCL_N(N) ((N) << 0)
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/*
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* MEM_SDADDR register contents definitions
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*/
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#define MEM_SDADDR_E (1 << 20)
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#define MEM_SDADDR_CSBA (0x03FF << 10)
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#define MEM_SDADDR_CSMASK (0x03FF << 0)
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#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
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#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
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/*
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* MEM_SDREFCFG register content definitions
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*/
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#define MEM_SDREFCFG_TRC (15 << 28)
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#define MEM_SDREFCFG_TRPM (3 << 26)
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#define MEM_SDREFCFG_E (1 << 25)
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#define MEM_SDREFCFG_RE (0x1ffffff << 0)
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#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
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#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
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#define MEM_SDREFCFG_REF_N(N) (N)
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#endif
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/***********************************************************************/
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/*
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* Au1550 SDRAM Register Offsets
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*/
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/***********************************************************************/
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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#define MEM_SDMODE0 0x0800
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#define MEM_SDMODE1 0x0808
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#define MEM_SDMODE2 0x0810
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#define MEM_SDADDR0 0x0820
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#define MEM_SDADDR1 0x0828
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#define MEM_SDADDR2 0x0830
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#define MEM_SDCONFIGA 0x0840
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#define MEM_SDCONFIGB 0x0848
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#define MEM_SDSTAT 0x0850
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#define MEM_SDERRADDR 0x0858
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#define MEM_SDSTRIDE0 0x0860
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#define MEM_SDSTRIDE1 0x0868
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#define MEM_SDSTRIDE2 0x0870
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#define MEM_SDWRMD0 0x0880
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#define MEM_SDWRMD1 0x0888
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#define MEM_SDWRMD2 0x0890
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#define MEM_SDPRECMD 0x08C0
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#define MEM_SDAUTOREF 0x08C8
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#define MEM_SDSREF 0x08D0
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#define MEM_SDSLEEP MEM_SDSREF
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#endif
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/*
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* Physical base addresses for integrated peripherals
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* 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
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@@ -761,6 +654,92 @@ enum soc_au1200_ints {
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#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */
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/* Au1000 SDRAM memory controller register offsets */
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#define AU1000_MEM_SDMODE0 0x0000
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#define AU1000_MEM_SDMODE1 0x0004
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#define AU1000_MEM_SDMODE2 0x0008
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#define AU1000_MEM_SDADDR0 0x000C
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#define AU1000_MEM_SDADDR1 0x0010
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#define AU1000_MEM_SDADDR2 0x0014
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#define AU1000_MEM_SDREFCFG 0x0018
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#define AU1000_MEM_SDPRECMD 0x001C
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#define AU1000_MEM_SDAUTOREF 0x0020
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#define AU1000_MEM_SDWRMD0 0x0024
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#define AU1000_MEM_SDWRMD1 0x0028
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#define AU1000_MEM_SDWRMD2 0x002C
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#define AU1000_MEM_SDSLEEP 0x0030
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#define AU1000_MEM_SDSMCKE 0x0034
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/* MEM_SDMODE register content definitions */
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#define MEM_SDMODE_F (1 << 22)
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#define MEM_SDMODE_SR (1 << 21)
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#define MEM_SDMODE_BS (1 << 20)
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#define MEM_SDMODE_RS (3 << 18)
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#define MEM_SDMODE_CS (7 << 15)
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#define MEM_SDMODE_TRAS (15 << 11)
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#define MEM_SDMODE_TMRD (3 << 9)
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#define MEM_SDMODE_TWR (3 << 7)
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#define MEM_SDMODE_TRP (3 << 5)
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#define MEM_SDMODE_TRCD (3 << 3)
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#define MEM_SDMODE_TCL (7 << 0)
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#define MEM_SDMODE_BS_2Bank (0 << 20)
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#define MEM_SDMODE_BS_4Bank (1 << 20)
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#define MEM_SDMODE_RS_11Row (0 << 18)
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#define MEM_SDMODE_RS_12Row (1 << 18)
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#define MEM_SDMODE_RS_13Row (2 << 18)
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#define MEM_SDMODE_RS_N(N) ((N) << 18)
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#define MEM_SDMODE_CS_7Col (0 << 15)
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#define MEM_SDMODE_CS_8Col (1 << 15)
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#define MEM_SDMODE_CS_9Col (2 << 15)
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#define MEM_SDMODE_CS_10Col (3 << 15)
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#define MEM_SDMODE_CS_11Col (4 << 15)
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#define MEM_SDMODE_CS_N(N) ((N) << 15)
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#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
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#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
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#define MEM_SDMODE_TWR_N(N) ((N) << 7)
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#define MEM_SDMODE_TRP_N(N) ((N) << 5)
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#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
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#define MEM_SDMODE_TCL_N(N) ((N) << 0)
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/* MEM_SDADDR register contents definitions */
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#define MEM_SDADDR_E (1 << 20)
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#define MEM_SDADDR_CSBA (0x03FF << 10)
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#define MEM_SDADDR_CSMASK (0x03FF << 0)
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#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
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#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
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/* MEM_SDREFCFG register content definitions */
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#define MEM_SDREFCFG_TRC (15 << 28)
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#define MEM_SDREFCFG_TRPM (3 << 26)
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#define MEM_SDREFCFG_E (1 << 25)
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#define MEM_SDREFCFG_RE (0x1ffffff << 0)
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#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
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#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
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#define MEM_SDREFCFG_REF_N(N) (N)
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/* Au1550 SDRAM Register Offsets */
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#define AU1550_MEM_SDMODE0 0x0800
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#define AU1550_MEM_SDMODE1 0x0808
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#define AU1550_MEM_SDMODE2 0x0810
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#define AU1550_MEM_SDADDR0 0x0820
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#define AU1550_MEM_SDADDR1 0x0828
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#define AU1550_MEM_SDADDR2 0x0830
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#define AU1550_MEM_SDCONFIGA 0x0840
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#define AU1550_MEM_SDCONFIGB 0x0848
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#define AU1550_MEM_SDSTAT 0x0850
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#define AU1550_MEM_SDERRADDR 0x0858
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#define AU1550_MEM_SDSTRIDE0 0x0860
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#define AU1550_MEM_SDSTRIDE1 0x0868
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#define AU1550_MEM_SDSTRIDE2 0x0870
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#define AU1550_MEM_SDWRMD0 0x0880
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#define AU1550_MEM_SDWRMD1 0x0888
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#define AU1550_MEM_SDWRMD2 0x0890
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#define AU1550_MEM_SDPRECMD 0x08C0
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#define AU1550_MEM_SDAUTOREF 0x08C8
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#define AU1550_MEM_SDSREF 0x08D0
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#define AU1550_MEM_SDSLEEP MEM_SDSREF
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/* Static Bus Controller */
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#define MEM_STCFG0 0xB4001000
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#define MEM_STTIME0 0xB4001004
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@@ -778,14 +757,12 @@ enum soc_au1200_ints {
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#define MEM_STTIME3 0xB4001034
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#define MEM_STADDR3 0xB4001038
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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#define MEM_STNDCTL 0xB4001100
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#define MEM_STSTAT 0xB4001104
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#define MEM_STNAND_CMD 0x0
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#define MEM_STNAND_ADDR 0x4
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#define MEM_STNAND_DATA 0x20
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#endif
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/* Programmable Counters 0 and 1 */
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@@ -1172,7 +1149,6 @@ enum soc_au1200_ints {
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# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
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/* Au1200 only */
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#ifdef CONFIG_SOC_AU1200
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#define SYS_PINFUNC_DMA (1 << 31)
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#define SYS_PINFUNC_S0A (1 << 30)
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#define SYS_PINFUNC_S1A (1 << 29)
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@@ -1200,7 +1176,6 @@ enum soc_au1200_ints {
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#define SYS_PINFUNC_P0B (1 << 4)
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#define SYS_PINFUNC_U0T (1 << 3)
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#define SYS_PINFUNC_S1B (1 << 2)
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#endif
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/* Power Management */
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#define SYS_SCRATCH0 0xB1900018
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@@ -1256,12 +1231,12 @@ enum soc_au1200_ints {
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# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
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# define SYS_CS_DI2 (1 << 16)
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# define SYS_CS_CI2 (1 << 15)
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#ifdef CONFIG_SOC_AU1100
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# define SYS_CS_ML_BIT 7
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# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
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# define SYS_CS_DL (1 << 6)
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# define SYS_CS_CL (1 << 5)
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#else
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# define SYS_CS_MUH_BIT 12
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# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
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# define SYS_CS_DUH (1 << 11)
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@@ -1270,7 +1245,7 @@ enum soc_au1200_ints {
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# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
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# define SYS_CS_DUD (1 << 6)
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# define SYS_CS_CUD (1 << 5)
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#endif
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# define SYS_CS_MIR_BIT 2
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# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
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# define SYS_CS_DIR (1 << 1)
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