igb: access to NIC time
Adds the register definitions and code to read the time register. Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Patrick Ohly <patrick.ohly@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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committed by
David S. Miller
parent
d24fff22d8
commit
38c845c764
@@ -175,6 +175,54 @@ MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_VERSION);
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/**
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* Scale the NIC clock cycle by a large factor so that
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* relatively small clock corrections can be added or
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* substracted at each clock tick. The drawbacks of a
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* large factor are a) that the clock register overflows
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* more quickly (not such a big deal) and b) that the
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* increment per tick has to fit into 24 bits.
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*
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* Note that
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* TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
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* IGB_TSYNC_SCALE
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* TIMINCA += TIMINCA * adjustment [ppm] / 1e9
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*
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* The base scale factor is intentionally a power of two
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* so that the division in %struct timecounter can be done with
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* a shift.
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*/
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#define IGB_TSYNC_SHIFT (19)
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#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
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/**
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* The duration of one clock cycle of the NIC.
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*
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* @todo This hard-coded value is part of the specification and might change
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* in future hardware revisions. Add revision check.
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*/
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#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
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#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
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# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
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#endif
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/**
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* igb_read_clock - read raw cycle counter (to be used by time counter)
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*/
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static cycle_t igb_read_clock(const struct cyclecounter *tc)
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{
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struct igb_adapter *adapter =
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container_of(tc, struct igb_adapter, cycles);
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struct e1000_hw *hw = &adapter->hw;
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u64 stamp;
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stamp = rd32(E1000_SYSTIML);
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stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
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return stamp;
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}
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#ifdef DEBUG
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/**
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* igb_get_hw_dev_name - return device name string
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@@ -185,6 +233,29 @@ char *igb_get_hw_dev_name(struct e1000_hw *hw)
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struct igb_adapter *adapter = hw->back;
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return adapter->netdev->name;
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}
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/**
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* igb_get_time_str - format current NIC and system time as string
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*/
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static char *igb_get_time_str(struct igb_adapter *adapter,
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char buffer[160])
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{
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cycle_t hw = adapter->cycles.read(&adapter->cycles);
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struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
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struct timespec sys;
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struct timespec delta;
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getnstimeofday(&sys);
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delta = timespec_sub(nic, sys);
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sprintf(buffer,
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"NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
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(long)nic.tv_sec, nic.tv_nsec,
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(long)sys.tv_sec, sys.tv_nsec,
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(long)delta.tv_sec, delta.tv_nsec);
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return buffer;
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}
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#endif
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/**
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@@ -1298,6 +1369,46 @@ static int __devinit igb_probe(struct pci_dev *pdev,
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}
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#endif
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/*
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* Initialize hardware timer: we keep it running just in case
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* that some program needs it later on.
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*/
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memset(&adapter->cycles, 0, sizeof(adapter->cycles));
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adapter->cycles.read = igb_read_clock;
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adapter->cycles.mask = CLOCKSOURCE_MASK(64);
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adapter->cycles.mult = 1;
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adapter->cycles.shift = IGB_TSYNC_SHIFT;
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wr32(E1000_TIMINCA,
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(1<<24) |
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IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
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#if 0
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/*
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* Avoid rollover while we initialize by resetting the time counter.
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*/
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wr32(E1000_SYSTIML, 0x00000000);
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wr32(E1000_SYSTIMH, 0x00000000);
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#else
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/*
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* Set registers so that rollover occurs soon to test this.
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*/
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wr32(E1000_SYSTIML, 0x00000000);
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wr32(E1000_SYSTIMH, 0xFF800000);
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#endif
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wrfl();
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timecounter_init(&adapter->clock,
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&adapter->cycles,
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ktime_to_ns(ktime_get_real()));
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#ifdef DEBUG
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{
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char buffer[160];
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printk(KERN_DEBUG
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"igb: %s: hw %p initialized timer\n",
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igb_get_time_str(adapter, buffer),
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&adapter->hw);
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}
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#endif
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dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
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/* print bus type/speed/width info */
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dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
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