[MIPS] Add support for MIPS CMP platform.
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
295
arch/mips/kernel/irq-gic.c
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295
arch/mips/kernel/irq-gic.c
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#undef DEBUG
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#include <linux/bitmap.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/gic.h>
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#include <asm/gcmpregs.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/irq.h>
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#include <linux/hardirq.h>
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#include <asm-generic/bitops/find.h>
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static unsigned long _gic_base;
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static unsigned int _irqbase, _mapsize, numvpes, numintrs;
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static struct gic_intr_map *_intrmap;
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static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
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static struct gic_pending_regs pending_regs[NR_CPUS];
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static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
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#define gic_wedgeb2bok 0 /*
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* Can GIC handle b2b writes to wedge register?
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*/
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#if gic_wedgeb2bok == 0
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static DEFINE_SPINLOCK(gic_wedgeb2b_lock);
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#endif
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void gic_send_ipi(unsigned int intr)
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{
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#if gic_wedgeb2bok == 0
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unsigned long flags;
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#endif
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pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
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read_c0_status());
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if (!gic_wedgeb2bok)
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spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
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GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
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if (!gic_wedgeb2bok) {
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(void) GIC_REG(SHARED, GIC_SH_CONFIG);
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spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
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}
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}
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/* This is Malta specific and needs to be exported */
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static void vpe_local_setup(unsigned int numvpes)
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{
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int i;
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unsigned long timer_interrupt = 5, perf_interrupt = 5;
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unsigned int vpe_ctl;
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/*
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* Setup the default performance counter timer interrupts
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* for all VPEs
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*/
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for (i = 0; i < numvpes; i++) {
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
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/* Are Interrupts locally routable? */
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GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
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if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
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GIC_MAP_TO_PIN_MSK | timer_interrupt);
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if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
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GIC_MAP_TO_PIN_MSK | perf_interrupt);
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}
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}
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unsigned int gic_get_int(void)
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{
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unsigned int i;
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unsigned long *pending, *intrmask, *pcpu_mask;
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unsigned long *pending_abs, *intrmask_abs;
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/* Get per-cpu bitmaps */
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pending = pending_regs[smp_processor_id()].pending;
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intrmask = intrmask_regs[smp_processor_id()].intrmask;
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pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
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pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
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GIC_SH_PEND_31_0_OFS);
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intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
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GIC_SH_MASK_31_0_OFS);
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for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
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GICREAD(*pending_abs, pending[i]);
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GICREAD(*intrmask_abs, intrmask[i]);
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pending_abs++;
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intrmask_abs++;
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}
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bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
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bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
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i = find_first_bit(pending, GIC_NUM_INTRS);
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pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
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return i;
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}
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static unsigned int gic_irq_startup(unsigned int irq)
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{
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pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
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irq -= _irqbase;
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/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
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GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
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1 << (irq % 32));
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return 0;
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}
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static void gic_irq_ack(unsigned int irq)
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{
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#if gic_wedgeb2bok == 0
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unsigned long flags;
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#endif
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pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
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irq -= _irqbase;
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GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
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1 << (irq % 32));
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if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) {
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if (!gic_wedgeb2bok)
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spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
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GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
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if (!gic_wedgeb2bok) {
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(void) GIC_REG(SHARED, GIC_SH_CONFIG);
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spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
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}
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}
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}
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static void gic_mask_irq(unsigned int irq)
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{
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pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
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irq -= _irqbase;
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/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
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GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
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1 << (irq % 32));
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}
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static void gic_unmask_irq(unsigned int irq)
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{
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pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
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irq -= _irqbase;
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/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
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GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
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1 << (irq % 32));
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}
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#ifdef CONFIG_SMP
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static DEFINE_SPINLOCK(gic_lock);
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static void gic_set_affinity(unsigned int irq, cpumask_t cpumask)
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{
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cpumask_t tmp = CPU_MASK_NONE;
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unsigned long flags;
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int i;
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pr_debug(KERN_DEBUG "%s called\n", __func__);
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irq -= _irqbase;
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cpus_and(tmp, cpumask, cpu_online_map);
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if (cpus_empty(tmp))
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return;
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/* Assumption : cpumask refers to a single CPU */
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spin_lock_irqsave(&gic_lock, flags);
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for (;;) {
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/* Re-route this IRQ */
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GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
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/*
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* FIXME: assumption that _intrmap is ordered and has no holes
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*/
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/* Update the intr_map */
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_intrmap[irq].cpunum = first_cpu(tmp);
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/* Update the pcpu_masks */
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for (i = 0; i < NR_CPUS; i++)
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clear_bit(irq, pcpu_masks[i].pcpu_mask);
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set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
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}
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irq_desc[irq].affinity = cpumask;
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spin_unlock_irqrestore(&gic_lock, flags);
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}
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#endif
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static struct irq_chip gic_irq_controller = {
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.name = "MIPS GIC",
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.startup = gic_irq_startup,
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.ack = gic_irq_ack,
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.mask = gic_mask_irq,
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.mask_ack = gic_mask_irq,
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.unmask = gic_unmask_irq,
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.eoi = gic_unmask_irq,
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#ifdef CONFIG_SMP
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.set_affinity = gic_set_affinity,
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#endif
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};
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static void __init setup_intr(unsigned int intr, unsigned int cpu,
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unsigned int pin, unsigned int polarity, unsigned int trigtype)
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{
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/* Setup Intr to Pin mapping */
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if (pin & GIC_MAP_TO_NMI_MSK) {
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
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/* FIXME: hack to route NMI to all cpu's */
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for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
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GICWRITE(GIC_REG_ADDR(SHARED,
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GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
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0xffffffff);
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}
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} else {
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
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GIC_MAP_TO_PIN_MSK | pin);
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/* Setup Intr to CPU mapping */
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GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
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}
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/* Setup Intr Polarity */
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GIC_SET_POLARITY(intr, polarity);
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/* Setup Intr Trigger Type */
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GIC_SET_TRIGGER(intr, trigtype);
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/* Init Intr Masks */
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GIC_SET_INTR_MASK(intr, 0);
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}
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static void __init gic_basic_init(void)
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{
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unsigned int i, cpu;
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/* Setup defaults */
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for (i = 0; i < GIC_NUM_INTRS; i++) {
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GIC_SET_POLARITY(i, GIC_POL_POS);
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GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
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GIC_SET_INTR_MASK(i, 0);
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}
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/* Setup specifics */
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for (i = 0; i < _mapsize; i++) {
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cpu = _intrmap[i].cpunum;
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if (cpu == X)
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continue;
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setup_intr(_intrmap[i].intrnum,
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_intrmap[i].cpunum,
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_intrmap[i].pin,
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_intrmap[i].polarity,
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_intrmap[i].trigtype);
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/* Initialise per-cpu Interrupt software masks */
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if (_intrmap[i].ipiflag)
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set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask);
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}
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vpe_local_setup(numvpes);
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for (i = _irqbase; i < (_irqbase + numintrs); i++)
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set_irq_chip(i, &gic_irq_controller);
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}
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void __init gic_init(unsigned long gic_base_addr,
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unsigned long gic_addrspace_size,
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struct gic_intr_map *intr_map, unsigned int intr_map_size,
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unsigned int irqbase)
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{
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unsigned int gicconfig;
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_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
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gic_addrspace_size);
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_irqbase = irqbase;
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_intrmap = intr_map;
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_mapsize = intr_map_size;
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GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
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numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
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GIC_SH_CONFIG_NUMINTRS_SHF;
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numintrs = ((numintrs + 1) * 8);
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numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
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GIC_SH_CONFIG_NUMVPES_SHF;
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pr_debug("%s called\n", __func__);
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gic_basic_init();
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}
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