[MIPS] Add support for MIPS CMP platform.
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
@@ -22,6 +22,7 @@
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#include <linux/kallsyms.h>
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#include <linux/bootmem.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <asm/bootinfo.h>
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#include <asm/branch.h>
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@@ -80,19 +81,22 @@ void (*board_bind_eic_interrupt)(int irq, int regset);
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static void show_raw_backtrace(unsigned long reg29)
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{
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unsigned long *sp = (unsigned long *)reg29;
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unsigned long *sp = (unsigned long *)(reg29 & ~3);
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unsigned long addr;
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printk("Call Trace:");
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#ifdef CONFIG_KALLSYMS
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printk("\n");
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#endif
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while (!kstack_end(sp)) {
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addr = *sp++;
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if (__kernel_text_address(addr))
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print_ip_sym(addr);
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#define IS_KVA01(a) ((((unsigned int)a) & 0xc0000000) == 0x80000000)
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if (IS_KVA01(sp)) {
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while (!kstack_end(sp)) {
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addr = *sp++;
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if (__kernel_text_address(addr))
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print_ip_sym(addr);
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}
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printk("\n");
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}
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printk("\n");
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}
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#ifdef CONFIG_KALLSYMS
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@@ -192,16 +196,19 @@ EXPORT_SYMBOL(dump_stack);
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static void show_code(unsigned int __user *pc)
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{
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long i;
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unsigned short __user *pc16 = NULL;
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printk("\nCode:");
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if ((unsigned long)pc & 1)
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pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
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for(i = -3 ; i < 6 ; i++) {
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unsigned int insn;
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if (__get_user(insn, pc + i)) {
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if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
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printk(" (Bad address in epc)\n");
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break;
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}
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printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
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printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
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}
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}
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@@ -311,10 +318,21 @@ void show_regs(struct pt_regs *regs)
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void show_registers(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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__show_regs(regs);
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print_modules();
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printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
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current->comm, task_pid_nr(current), current_thread_info(), current);
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printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
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current->comm, current->pid, current_thread_info(), current,
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field, current_thread_info()->tp_value);
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if (cpu_has_userlocal) {
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unsigned long tls;
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tls = read_c0_userlocal();
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if (tls != current_thread_info()->tp_value)
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printk("*HwTLS: %0*lx\n", field, tls);
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}
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show_stacktrace(current, regs);
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show_code((unsigned int __user *) regs->cp0_epc);
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printk("\n");
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@@ -985,6 +1003,21 @@ asmlinkage void do_reserved(struct pt_regs *regs)
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(regs->cp0_cause & 0x7f) >> 2);
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}
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static int __initdata l1parity = 1;
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static int __init nol1parity(char *s)
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{
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l1parity = 0;
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return 1;
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}
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__setup("nol1par", nol1parity);
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static int __initdata l2parity = 1;
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static int __init nol2parity(char *s)
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{
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l2parity = 0;
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return 1;
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}
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__setup("nol2par", nol2parity);
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/*
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* Some MIPS CPUs can enable/disable for cache parity detection, but do
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* it different ways.
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@@ -994,6 +1027,62 @@ static inline void parity_protection_init(void)
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switch (current_cpu_type()) {
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case CPU_24K:
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case CPU_34K:
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case CPU_74K:
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case CPU_1004K:
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{
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#define ERRCTL_PE 0x80000000
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#define ERRCTL_L2P 0x00800000
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unsigned long errctl;
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unsigned int l1parity_present, l2parity_present;
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errctl = read_c0_ecc();
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errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
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/* probe L1 parity support */
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write_c0_ecc(errctl | ERRCTL_PE);
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back_to_back_c0_hazard();
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l1parity_present = (read_c0_ecc() & ERRCTL_PE);
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/* probe L2 parity support */
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write_c0_ecc(errctl|ERRCTL_L2P);
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back_to_back_c0_hazard();
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l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
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if (l1parity_present && l2parity_present) {
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if (l1parity)
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errctl |= ERRCTL_PE;
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if (l1parity ^ l2parity)
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errctl |= ERRCTL_L2P;
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} else if (l1parity_present) {
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if (l1parity)
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errctl |= ERRCTL_PE;
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} else if (l2parity_present) {
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if (l2parity)
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errctl |= ERRCTL_L2P;
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} else {
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/* No parity available */
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}
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printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
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write_c0_ecc(errctl);
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back_to_back_c0_hazard();
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errctl = read_c0_ecc();
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printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
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if (l1parity_present)
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printk(KERN_INFO "Cache parity protection %sabled\n",
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(errctl & ERRCTL_PE) ? "en" : "dis");
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if (l2parity_present) {
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if (l1parity_present && l1parity)
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errctl ^= ERRCTL_L2P;
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printk(KERN_INFO "L2 cache parity protection %sabled\n",
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(errctl & ERRCTL_L2P) ? "en" : "dis");
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}
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}
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break;
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case CPU_5KC:
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write_c0_ecc(0x80000000);
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back_to_back_c0_hazard();
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@@ -1353,7 +1442,6 @@ void __cpuinit per_cpu_trap_init(void)
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change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
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status_set);
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#ifdef CONFIG_CPU_MIPSR2
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if (cpu_has_mips_r2) {
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unsigned int enable = 0x0000000f;
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@@ -1362,7 +1450,6 @@ void __cpuinit per_cpu_trap_init(void)
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write_c0_hwrena(enable);
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}
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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if (!secondaryTC) {
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