lk/linux-kernel-test
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

m68knommu: map ColdFire interrupts to correct masking bits

Browse Source 
The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer
2009-05-22 13:33:35 +10:00
parent f6a66276f5
commit 39f0fb6a34
7 changed files with 90 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
arch/m68k/include/asm/mcfintc.h
View File

@ -24,11 +24,6 @@
* interrupt control purposes.
*/
/*
* Define the base address of the SIM within the MBAR address space.
*/
#define MCFSIM_BASE 0x0 /* Base address within SIM */
/*
* Bit definitions for the ICR family of registers.
*/
@ -48,7 +43,9 @@
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
/*
* IMR bit position definitions.
* IMR bit position definitions. Not all ColdFire parts with this interrupt
* controller actually support all of these interrupt sources. But the bit
* numbers are the same in all cores.
*/
#define MCFINTC_EINT1 1 /* External int #1 */
#define MCFINTC_EINT2 2 /* External int #2 */
@ -70,6 +67,19 @@
#define MCFINTC_QSPI 18
#ifndef __ASSEMBLER__
/*
* There is no one-is-one correspondance between the interrupt number (irq)
* and the bit fields on the mask register. So we create a per-cpu type
* mapping of irq to mask bit. The CPU platform code needs to register
* its supported irq's at init time, using this function.
*/
extern unsigned char mcf_irq2imr[];
static inline void mcf_mapirq2imr(int irq, int imr)
{
mcf_irq2imr[irq] = imr;
}
void mcf_autovector(int irq);
void mcf_setimr(int index);
void mcf_clrimr(int index);