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OMAP3: Add support for DPLL3 divisor values higher than 2

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Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
This commit is contained in:
Tero Kristo
2009-06-19 19:08:29 -06:00
committed by paul
parent df14e4747a
commit 3afec6332e
4 changed files with 15 additions and 14 deletions
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6
arch/arm/plat-omap/include/mach/sram.h
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@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll, u32 f, u32 sdrc_mr);
u32 unlock_dll, u32 f, u32 sdrc_mr,
u32 inc);
/* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll, u32 f, u32 sdrc_mr);
u32 unlock_dll, u32 f, u32 sdrc_mr,
u32 inc);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif