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x86, amd: Extend AMD northbridge caching code to support "Link Control" devices

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"Link Control" devices (NB function 4) will be used by L3 cache
partitioning on family 0x15.

Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
Cc: <andreas.herrmann3@amd.com>
LKML-Reference: <1295881543-572552-4-git-send-email-hans.rosenfeld@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Hans Rosenfeld
2011-01-24 16:05:42 +01:00
committed by Ingo Molnar
parent b453de02b7
commit 41b2610c34
3 changed files with 11 additions and 2 deletions
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arch/x86/include/asm/amd_nb.h
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@ -26,6 +26,7 @@ extern void amd_get_nodes(struct bootnode *nodes);
struct amd_northbridge {
struct pci_dev *misc;
struct pci_dev *link;
};
struct amd_northbridge_info {