[MIPS] Alchemy: cleanup interrupt code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
@@ -26,39 +26,18 @@
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/mach-au1x00/au1000.h>
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#ifdef CONFIG_MIPS_PB1000
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#include <asm/mach-pb1x00/pb1000.h>
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#endif
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#undef DEBUG_IRQ
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#ifdef DEBUG_IRQ
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/* note: prints function name for you */
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#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
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#else
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#define DPRINTK(fmt, args...)
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#endif
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#define EXT_INTC0_REQ0 2 /* IP 2 */
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#define EXT_INTC0_REQ1 3 /* IP 3 */
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#define EXT_INTC1_REQ0 4 /* IP 4 */
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@@ -69,16 +48,98 @@ void (*board_init_irq)(void);
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static DEFINE_SPINLOCK(irq_lock);
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#ifdef CONFIG_PM
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/*
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* Save/restore the interrupt controller state.
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* Called from the save/restore core registers as part of the
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* au_sleep function in power.c.....maybe I should just pm_register()
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* them instead?
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*/
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static unsigned int sleep_intctl_config0[2];
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static unsigned int sleep_intctl_config1[2];
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static unsigned int sleep_intctl_config2[2];
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static unsigned int sleep_intctl_src[2];
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static unsigned int sleep_intctl_assign[2];
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static unsigned int sleep_intctl_wake[2];
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static unsigned int sleep_intctl_mask[2];
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void save_au1xxx_intctl(void)
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{
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sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
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sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
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sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
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sleep_intctl_src[0] = au_readl(IC0_SRCRD);
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sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
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sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
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sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
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sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
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sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
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sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
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sleep_intctl_src[1] = au_readl(IC1_SRCRD);
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sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
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sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
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sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
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}
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/*
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* For most restore operations, we clear the entire register and
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* then set the bits we found during the save.
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*/
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void restore_au1xxx_intctl(void)
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{
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au_writel(0xffffffff, IC0_MASKCLR); au_sync();
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au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
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au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
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au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
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au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
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au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
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au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
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au_writel(0xffffffff, IC0_SRCCLR); au_sync();
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au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
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au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
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au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
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au_writel(0xffffffff, IC0_WAKECLR); au_sync();
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au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
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au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
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au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
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au_writel(0x00000000, IC0_TESTBIT); au_sync();
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au_writel(0xffffffff, IC1_MASKCLR); au_sync();
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au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
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au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
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au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
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au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
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au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
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au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
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au_writel(0xffffffff, IC1_SRCCLR); au_sync();
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au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
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au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
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au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
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au_writel(0xffffffff, IC1_WAKECLR); au_sync();
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au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
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au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
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au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
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au_writel(0x00000000, IC1_TESTBIT); au_sync();
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au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
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au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
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}
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#endif /* CONFIG_PM */
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inline void local_enable_irq(unsigned int irq_nr)
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{
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1<<(irq_nr-32), IC1_MASKSET);
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au_writel(1<<(irq_nr-32), IC1_WAKESET);
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}
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else {
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au_writel(1<<irq_nr, IC0_MASKSET);
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au_writel(1<<irq_nr, IC0_WAKESET);
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au_writel(1 << (irq_nr - 32), IC1_MASKSET);
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au_writel(1 << (irq_nr - 32), IC1_WAKESET);
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} else {
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au_writel(1 << irq_nr, IC0_MASKSET);
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au_writel(1 << irq_nr, IC0_WAKESET);
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}
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au_sync();
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}
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@@ -87,12 +148,11 @@ inline void local_enable_irq(unsigned int irq_nr)
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inline void local_disable_irq(unsigned int irq_nr)
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{
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1<<(irq_nr-32), IC1_MASKCLR);
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au_writel(1<<(irq_nr-32), IC1_WAKECLR);
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}
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else {
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au_writel(1<<irq_nr, IC0_MASKCLR);
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au_writel(1<<irq_nr, IC0_WAKECLR);
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
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} else {
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au_writel(1 << irq_nr, IC0_MASKCLR);
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au_writel(1 << irq_nr, IC0_WAKECLR);
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}
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au_sync();
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}
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@@ -101,12 +161,11 @@ inline void local_disable_irq(unsigned int irq_nr)
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static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
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{
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
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au_writel(1<<(irq_nr-32), IC1_MASKCLR);
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}
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else {
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au_writel(1<<irq_nr, IC0_RISINGCLR);
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au_writel(1<<irq_nr, IC0_MASKCLR);
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au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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} else {
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au_writel(1 << irq_nr, IC0_RISINGCLR);
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au_writel(1 << irq_nr, IC0_MASKCLR);
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}
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au_sync();
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}
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@@ -115,12 +174,11 @@ static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
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static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
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{
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
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au_writel(1<<(irq_nr-32), IC1_MASKCLR);
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}
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else {
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au_writel(1<<irq_nr, IC0_FALLINGCLR);
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au_writel(1<<irq_nr, IC0_MASKCLR);
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au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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} else {
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au_writel(1 << irq_nr, IC0_FALLINGCLR);
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au_writel(1 << irq_nr, IC0_MASKCLR);
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}
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au_sync();
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}
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@@ -132,14 +190,13 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
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* both edges at once, or if we do, that we don't care.
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*/
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
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au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
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au_writel(1<<(irq_nr-32), IC1_MASKCLR);
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}
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else {
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au_writel(1<<irq_nr, IC0_FALLINGCLR);
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au_writel(1<<irq_nr, IC0_RISINGCLR);
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au_writel(1<<irq_nr, IC0_MASKCLR);
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au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
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au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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} else {
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au_writel(1 << irq_nr, IC0_FALLINGCLR);
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au_writel(1 << irq_nr, IC0_RISINGCLR);
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au_writel(1 << irq_nr, IC0_MASKCLR);
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}
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au_sync();
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}
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@@ -162,9 +219,9 @@ static inline void mask_and_ack_level_irq(unsigned int irq_nr)
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static void end_irq(unsigned int irq_nr)
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{
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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local_enable_irq(irq_nr);
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}
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#if defined(CONFIG_MIPS_PB1000)
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if (irq_nr == AU1000_GPIO_15) {
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au_writel(0x4000, PB1000_MDR); /* enable int */
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@@ -181,16 +238,13 @@ unsigned long save_local_and_disable(int controller)
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spin_lock_irqsave(&irq_lock, flags);
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if (controller) {
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mask = au_readl(IC1_MASKSET);
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for (i=32; i<64; i++) {
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for (i = 32; i < 64; i++)
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local_disable_irq(i);
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}
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}
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else {
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} else {
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mask = au_readl(IC0_MASKSET);
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for (i=0; i<32; i++) {
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for (i = 0; i < 32; i++)
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local_disable_irq(i);
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}
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}
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spin_unlock_irqrestore(&irq_lock, flags);
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return mask;
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@@ -202,10 +256,10 @@ void restore_local_and_enable(int controller, unsigned long mask)
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unsigned long flags, new_mask;
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spin_lock_irqsave(&irq_lock, flags);
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for (i=0; i<32; i++) {
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if (mask & (1<<i)) {
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for (i = 0; i < 32; i++) {
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if (mask & (1 << i)) {
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if (controller)
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local_enable_irq(i+32);
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local_enable_irq(i + 32);
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else
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local_enable_irq(i);
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}
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@@ -263,7 +317,8 @@ void startup_match20_interrupt(irq_handler_t handler)
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static struct irqaction action;
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memset(&action, 0, sizeof(struct irqaction));
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/* This is a big problem.... since we didn't use request_irq
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/*
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* This is a big problem.... since we didn't use request_irq
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* when kernel/irq.c calls probe_irq_xxx this interrupt will
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* be probed for usage. This will end up disabling the device :(
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* Give it a bogus "action" pointer -- this will keep it from
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@@ -293,110 +348,215 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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switch (type) {
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case INTC_INT_RISE_EDGE: /* 0:0:1 */
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au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG0SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
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set_irq_chip(irq_nr, &rise_edge_irq_type);
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break;
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case INTC_INT_FALL_EDGE: /* 0:1:0 */
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au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG1SET);
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au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
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set_irq_chip(irq_nr, &fall_edge_irq_type);
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break;
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case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
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au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG1SET);
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au_writel(1<<(irq_nr-32), IC1_CFG0SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
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set_irq_chip(irq_nr, &either_edge_irq_type);
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break;
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case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
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au_writel(1<<(irq_nr-32), IC1_CFG2SET);
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au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG0SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
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set_irq_chip(irq_nr, &level_irq_type);
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break;
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case INTC_INT_LOW_LEVEL: /* 1:1:0 */
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au_writel(1<<(irq_nr-32), IC1_CFG2SET);
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au_writel(1<<(irq_nr-32), IC1_CFG1SET);
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au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
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set_irq_chip(irq_nr, &level_irq_type);
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break;
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case INTC_INT_DISABLED: /* 0:0:0 */
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au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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break;
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default: /* disable the interrupt */
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printk("unexpected int type %d (irq %d)\n", type, irq_nr);
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au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
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au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
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printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
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type, irq_nr);
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au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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return;
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}
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if (int_req) /* assign to interrupt request 1 */
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au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
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au_writel(1 << (irq_nr - 32), IC1_ASSIGNCLR);
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else /* assign to interrupt request 0 */
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au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
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au_writel(1<<(irq_nr-32), IC1_SRCSET);
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au_writel(1<<(irq_nr-32), IC1_MASKCLR);
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au_writel(1<<(irq_nr-32), IC1_WAKECLR);
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}
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else {
|
||||
au_writel(1 << (irq_nr - 32), IC1_ASSIGNSET);
|
||||
au_writel(1 << (irq_nr - 32), IC1_SRCSET);
|
||||
au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
|
||||
au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
|
||||
} else {
|
||||
switch (type) {
|
||||
case INTC_INT_RISE_EDGE: /* 0:0:1 */
|
||||
au_writel(1<<irq_nr, IC0_CFG2CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG1CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG0SET);
|
||||
au_writel(1 << irq_nr, IC0_CFG2CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG1CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG0SET);
|
||||
set_irq_chip(irq_nr, &rise_edge_irq_type);
|
||||
break;
|
||||
case INTC_INT_FALL_EDGE: /* 0:1:0 */
|
||||
au_writel(1<<irq_nr, IC0_CFG2CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG1SET);
|
||||
au_writel(1<<irq_nr, IC0_CFG0CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG2CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG1SET);
|
||||
au_writel(1 << irq_nr, IC0_CFG0CLR);
|
||||
set_irq_chip(irq_nr, &fall_edge_irq_type);
|
||||
break;
|
||||
case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
|
||||
au_writel(1<<irq_nr, IC0_CFG2CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG1SET);
|
||||
au_writel(1<<irq_nr, IC0_CFG0SET);
|
||||
au_writel(1 << irq_nr, IC0_CFG2CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG1SET);
|
||||
au_writel(1 << irq_nr, IC0_CFG0SET);
|
||||
set_irq_chip(irq_nr, &either_edge_irq_type);
|
||||
break;
|
||||
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
|
||||
au_writel(1<<irq_nr, IC0_CFG2SET);
|
||||
au_writel(1<<irq_nr, IC0_CFG1CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG0SET);
|
||||
au_writel(1 << irq_nr, IC0_CFG2SET);
|
||||
au_writel(1 << irq_nr, IC0_CFG1CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG0SET);
|
||||
set_irq_chip(irq_nr, &level_irq_type);
|
||||
break;
|
||||
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
|
||||
au_writel(1<<irq_nr, IC0_CFG2SET);
|
||||
au_writel(1<<irq_nr, IC0_CFG1SET);
|
||||
au_writel(1<<irq_nr, IC0_CFG0CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG2SET);
|
||||
au_writel(1 << irq_nr, IC0_CFG1SET);
|
||||
au_writel(1 << irq_nr, IC0_CFG0CLR);
|
||||
set_irq_chip(irq_nr, &level_irq_type);
|
||||
break;
|
||||
case INTC_INT_DISABLED: /* 0:0:0 */
|
||||
au_writel(1<<irq_nr, IC0_CFG0CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG1CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG2CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG0CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG1CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG2CLR);
|
||||
break;
|
||||
default: /* disable the interrupt */
|
||||
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
|
||||
au_writel(1<<irq_nr, IC0_CFG0CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG1CLR);
|
||||
au_writel(1<<irq_nr, IC0_CFG2CLR);
|
||||
printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
|
||||
type, irq_nr);
|
||||
au_writel(1 << irq_nr, IC0_CFG0CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG1CLR);
|
||||
au_writel(1 << irq_nr, IC0_CFG2CLR);
|
||||
return;
|
||||
}
|
||||
if (int_req) /* assign to interrupt request 1 */
|
||||
au_writel(1<<irq_nr, IC0_ASSIGNCLR);
|
||||
au_writel(1 << irq_nr, IC0_ASSIGNCLR);
|
||||
else /* assign to interrupt request 0 */
|
||||
au_writel(1<<irq_nr, IC0_ASSIGNSET);
|
||||
au_writel(1<<irq_nr, IC0_SRCSET);
|
||||
au_writel(1<<irq_nr, IC0_MASKCLR);
|
||||
au_writel(1<<irq_nr, IC0_WAKECLR);
|
||||
au_writel(1 << irq_nr, IC0_ASSIGNSET);
|
||||
au_writel(1 << irq_nr, IC0_SRCSET);
|
||||
au_writel(1 << irq_nr, IC0_MASKCLR);
|
||||
au_writel(1 << irq_nr, IC0_WAKECLR);
|
||||
}
|
||||
au_sync();
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupts are nested. Even if an interrupt handler is registered
|
||||
* as "fast", we might get another interrupt before we return from
|
||||
* intcX_reqX_irqdispatch().
|
||||
*/
|
||||
|
||||
static void intc0_req0_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc0_req0;
|
||||
|
||||
intc0_req0 |= au_readl(IC0_REQ0INT);
|
||||
|
||||
if (!intc0_req0)
|
||||
return;
|
||||
|
||||
#ifdef AU1000_USB_DEV_REQ_INT
|
||||
/*
|
||||
* Because of the tight timing of SETUP token to reply
|
||||
* transactions, the USB devices-side packet complete
|
||||
* interrupt needs the highest priority.
|
||||
*/
|
||||
if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) {
|
||||
intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT);
|
||||
do_IRQ(AU1000_USB_DEV_REQ_INT);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
irq = au_ffs(intc0_req0) - 1;
|
||||
intc0_req0 &= ~(1 << irq);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
static void intc0_req1_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc0_req1;
|
||||
|
||||
intc0_req1 |= au_readl(IC0_REQ1INT);
|
||||
|
||||
if (!intc0_req1)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc0_req1) - 1;
|
||||
intc0_req1 &= ~(1 << irq);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Controller 1:
|
||||
* interrupts 32 - 63
|
||||
*/
|
||||
static void intc1_req0_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc1_req0;
|
||||
|
||||
intc1_req0 |= au_readl(IC1_REQ0INT);
|
||||
|
||||
if (!intc1_req0)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc1_req0) - 1;
|
||||
intc1_req0 &= ~(1 << irq);
|
||||
irq += 32;
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
static void intc1_req1_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc1_req1;
|
||||
|
||||
intc1_req1 |= au_readl(IC1_REQ1INT);
|
||||
|
||||
if (!intc1_req1)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc1_req1) - 1;
|
||||
intc1_req1 &= ~(1 << irq);
|
||||
irq += 32;
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
|
||||
if (pending & CAUSEF_IP7)
|
||||
do_IRQ(63);
|
||||
else if (pending & CAUSEF_IP2)
|
||||
intc0_req0_irqdispatch();
|
||||
else if (pending & CAUSEF_IP3)
|
||||
intc0_req1_irqdispatch();
|
||||
else if (pending & CAUSEF_IP4)
|
||||
intc1_req0_irqdispatch();
|
||||
else if (pending & CAUSEF_IP5)
|
||||
intc1_req1_irqdispatch();
|
||||
else
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
@@ -437,7 +597,7 @@ void __init arch_init_irq(void)
|
||||
/* Initialize IC0, which is fixed per processor.
|
||||
*/
|
||||
imp = au1xxx_ic0_map;
|
||||
for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
|
||||
for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
|
||||
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
|
||||
imp++;
|
||||
}
|
||||
@@ -445,7 +605,7 @@ void __init arch_init_irq(void)
|
||||
/* Now set up the irq mapping for the board.
|
||||
*/
|
||||
imp = au1xxx_irq_map;
|
||||
for (i=0; i<au1xxx_nr_irqs; i++) {
|
||||
for (i = 0; i < au1xxx_nr_irqs; i++) {
|
||||
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
|
||||
imp++;
|
||||
}
|
||||
@@ -457,191 +617,3 @@ void __init arch_init_irq(void)
|
||||
if (board_init_irq)
|
||||
(*board_init_irq)();
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Interrupts are nested. Even if an interrupt handler is registered
|
||||
* as "fast", we might get another interrupt before we return from
|
||||
* intcX_reqX_irqdispatch().
|
||||
*/
|
||||
|
||||
static void intc0_req0_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc0_req0 = 0;
|
||||
|
||||
intc0_req0 |= au_readl(IC0_REQ0INT);
|
||||
|
||||
if (!intc0_req0)
|
||||
return;
|
||||
#ifdef AU1000_USB_DEV_REQ_INT
|
||||
/*
|
||||
* Because of the tight timing of SETUP token to reply
|
||||
* transactions, the USB devices-side packet complete
|
||||
* interrupt needs the highest priority.
|
||||
*/
|
||||
if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
|
||||
intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
|
||||
do_IRQ(AU1000_USB_DEV_REQ_INT);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
irq = au_ffs(intc0_req0) - 1;
|
||||
intc0_req0 &= ~(1<<irq);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
static void intc0_req1_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc0_req1 = 0;
|
||||
|
||||
intc0_req1 |= au_readl(IC0_REQ1INT);
|
||||
|
||||
if (!intc0_req1)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc0_req1) - 1;
|
||||
intc0_req1 &= ~(1<<irq);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Controller 1:
|
||||
* interrupts 32 - 63
|
||||
*/
|
||||
static void intc1_req0_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc1_req0 = 0;
|
||||
|
||||
intc1_req0 |= au_readl(IC1_REQ0INT);
|
||||
|
||||
if (!intc1_req0)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc1_req0) - 1;
|
||||
intc1_req0 &= ~(1<<irq);
|
||||
irq += 32;
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
static void intc1_req1_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc1_req1 = 0;
|
||||
|
||||
intc1_req1 |= au_readl(IC1_REQ1INT);
|
||||
|
||||
if (!intc1_req1)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc1_req1) - 1;
|
||||
intc1_req1 &= ~(1<<irq);
|
||||
irq += 32;
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
/* Save/restore the interrupt controller state.
|
||||
* Called from the save/restore core registers as part of the
|
||||
* au_sleep function in power.c.....maybe I should just pm_register()
|
||||
* them instead?
|
||||
*/
|
||||
static unsigned int sleep_intctl_config0[2];
|
||||
static unsigned int sleep_intctl_config1[2];
|
||||
static unsigned int sleep_intctl_config2[2];
|
||||
static unsigned int sleep_intctl_src[2];
|
||||
static unsigned int sleep_intctl_assign[2];
|
||||
static unsigned int sleep_intctl_wake[2];
|
||||
static unsigned int sleep_intctl_mask[2];
|
||||
|
||||
void
|
||||
save_au1xxx_intctl(void)
|
||||
{
|
||||
sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
|
||||
sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
|
||||
sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
|
||||
sleep_intctl_src[0] = au_readl(IC0_SRCRD);
|
||||
sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
|
||||
sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
|
||||
sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
|
||||
|
||||
sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
|
||||
sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
|
||||
sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
|
||||
sleep_intctl_src[1] = au_readl(IC1_SRCRD);
|
||||
sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
|
||||
sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
|
||||
sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
|
||||
}
|
||||
|
||||
/* For most restore operations, we clear the entire register and
|
||||
* then set the bits we found during the save.
|
||||
*/
|
||||
void
|
||||
restore_au1xxx_intctl(void)
|
||||
{
|
||||
au_writel(0xffffffff, IC0_MASKCLR); au_sync();
|
||||
|
||||
au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
|
||||
au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
|
||||
au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
|
||||
au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
|
||||
au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
|
||||
au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
|
||||
au_writel(0xffffffff, IC0_SRCCLR); au_sync();
|
||||
au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
|
||||
au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
|
||||
au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
|
||||
au_writel(0xffffffff, IC0_WAKECLR); au_sync();
|
||||
au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
|
||||
au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
|
||||
au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
|
||||
au_writel(0x00000000, IC0_TESTBIT); au_sync();
|
||||
|
||||
au_writel(0xffffffff, IC1_MASKCLR); au_sync();
|
||||
|
||||
au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
|
||||
au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
|
||||
au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
|
||||
au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
|
||||
au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
|
||||
au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
|
||||
au_writel(0xffffffff, IC1_SRCCLR); au_sync();
|
||||
au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
|
||||
au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
|
||||
au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
|
||||
au_writel(0xffffffff, IC1_WAKECLR); au_sync();
|
||||
au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
|
||||
au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
|
||||
au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
|
||||
au_writel(0x00000000, IC1_TESTBIT); au_sync();
|
||||
|
||||
au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
|
||||
|
||||
au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
|
||||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
|
||||
if (pending & CAUSEF_IP7)
|
||||
do_IRQ(63);
|
||||
else if (pending & CAUSEF_IP2)
|
||||
intc0_req0_irqdispatch();
|
||||
else if (pending & CAUSEF_IP3)
|
||||
intc0_req1_irqdispatch();
|
||||
else if (pending & CAUSEF_IP4)
|
||||
intc1_req0_irqdispatch();
|
||||
else if (pending & CAUSEF_IP5)
|
||||
intc1_req1_irqdispatch();
|
||||
else
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user