lk/linux-kernel-test
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge branch 'for-linus2' of git://git.profusion.mobi/users/lucas/linux-2.6

Browse Source 
* 'for-linus2' of git://git.profusion.mobi/users/lucas/linux-2.6:
  Fix common misspellings
This commit is contained in:
Linus Torvalds
2011-04-07 11:14:49 -07:00
parent 2b9accbee5 25985edced
commit 42933bac11
2463 changed files with 4249 additions and 4249 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
arch/sparc/include/asm/hypervisor.h
View File

@@ -654,7 +654,7 @@ extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
* ARG3: mmu context
* ARG4: flags (HV_MMU_{IMMU,DMMU})
* RET0: status
* ERRORS: EINVAL Invalid virutal address, context, or
* ERRORS: EINVAL Invalid virtual address, context, or
* flags value
* ENOTSUPPORTED ARG0 or ARG1 is non-zero
*
@@ -721,7 +721,7 @@ extern void sun4v_mmu_demap_all(void);
* ARG2: TTE
* ARG3: flags (HV_MMU_{IMMU,DMMU})
* RET0: status
* ERRORS: EINVAL Invalid virutal address or flags value
* ERRORS: EINVAL Invalid virtual address or flags value
* EBADPGSZ Invalid page size value
* ENORADDR Invalid real address in TTE
* ETOOMANY Too many mappings (max of 8 reached)
@@ -800,7 +800,7 @@ extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
* ARG1: reserved, must be zero
* ARG2: flags (HV_MMU_{IMMU,DMMU})
* RET0: status
* ERRORS: EINVAL Invalid virutal address or flags value
* ERRORS: EINVAL Invalid virtual address or flags value
* ENOMAP Specified mapping was not found
*
* Demaps any permanent page mapping (established via
@@ -1205,7 +1205,7 @@ struct hv_trap_trace_control {
* structure contents. Attempts to do so will result in undefined
* behavior for the guest.
*
* Each trap trace buffer entry is layed out as follows:
* Each trap trace buffer entry is laid out as follows:
*/
#ifndef __ASSEMBLY__
struct hv_trap_trace_entry {
@@ -1300,7 +1300,7 @@ struct hv_trap_trace_entry {
* state in RET1. Future systems may define various flags for the
* enable argument (ARG0), for the moment a guest should pass
* "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
* tracing - which will ensure future compatability.
* tracing - which will ensure future compatibility.
*/
#define HV_FAST_TTRACE_ENABLE 0x92
@@ -1880,7 +1880,7 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
* pci_device, at pci_config_offset from the beginning of the device's
* configuration space. If there was no error, RET1 is set to zero and
* RET2 is set to the data read. Insignificant bits in RET2 are not
* guarenteed to have any specific value and therefore must be ignored.
* guaranteed to have any specific value and therefore must be ignored.
*
* The data returned in RET2 is size based byte swapped.
*
@@ -1941,9 +1941,9 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
* and return the actual data read in RET2. The data returned is size based
* byte swapped.
*
* Non-significant bits in RET2 are not guarenteed to have any specific value
* Non-significant bits in RET2 are not guaranteed to have any specific value
* and therefore must be ignored. If RET1 is returned as non-zero, the data
* value is not guarenteed to have any specific value and should be ignored.
* value is not guaranteed to have any specific value and should be ignored.
*
* The caller must have permission to read from the given devhandle, real
* address, which must be an IO address. The argument real address must be a
@@ -2456,9 +2456,9 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
*
* As receive queue configuration causes a reset of the queue's head and
* tail pointers there is no way for a gues to determine how many entries
* have been received between a preceeding ldc_get_rx_state() API call
* have been received between a preceding ldc_get_rx_state() API call
* and the completion of the configuration operation. It should be noted
* that datagram delivery is not guarenteed via domain channels anyway,
* that datagram delivery is not guaranteed via domain channels anyway,
* and therefore any higher protocol should be resilient to datagram
* loss if necessary. However, to overcome this specific race potential
* it is recommended, for example, that a higher level protocol be employed

2
arch/sparc/include/asm/ns87303.h
View File

@@ -37,7 +37,7 @@
/* Power and Test Register (PTR) bits */
#define PTR_LPTB_IRQ7 0x08
#define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controlls direction */
#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */
/* of the parallel port */
/* Function Control Register (FCR) bits */

2
arch/sparc/include/asm/pcr.h
View File

@@ -31,7 +31,7 @@ extern unsigned int picl_shift;
/* In order to commonize as much of the implementation as
* possible, we use PICH as our counter. Mostly this is
* to accomodate Niagara-1 which can only count insn cycles
* to accommodate Niagara-1 which can only count insn cycles
* in PICH.
*/
static inline u64 picl_value(unsigned int nmi_hz)

2
arch/sparc/include/asm/ptrace.h
View File

@@ -33,7 +33,7 @@ struct pt_regs {
* things like "in a system call" etc. for an arbitray
* process.
*
* The PT_REGS_MAGIC is choosen such that it can be
* The PT_REGS_MAGIC is chosen such that it can be
* loaded completely using just a sethi instruction.
*/
unsigned int magic;

4
arch/sparc/kernel/entry.S
View File

@@ -801,7 +801,7 @@ vac_linesize_patch_32: subcc %l7, 32, %l7
.globl vac_hwflush_patch1_on, vac_hwflush_patch2_on
/*
* Ugly, but we cant use hardware flushing on the sun4 and we'd require
* Ugly, but we can't use hardware flushing on the sun4 and we'd require
* two instructions (Anton)
*/
vac_hwflush_patch1_on: addcc %l7, -PAGE_SIZE, %l7
@@ -851,7 +851,7 @@ sun4c_fault:
sethi %hi(~((1 << SUN4C_REAL_PGDIR_SHIFT) - 1)), %l4
/* If the kernel references a bum kernel pointer, or a pte which
* points to a non existant page in ram, we will run this code
* points to a non existent page in ram, we will run this code
* _forever_ and lock up the machine!!!!! So we must check for
* this condition, the AC_SYNC_ERR bits are what we must examine.
* Also a parity error would make this happen as well. So we just

2
arch/sparc/kernel/head_64.S
View File

@@ -85,7 +85,7 @@ sparc_ramdisk_image64:
sparc64_boot:
mov %o4, %l7
/* We need to remap the kernel. Use position independant
/* We need to remap the kernel. Use position independent
* code to remap us to KERNBASE.
*
* SILO can invoke us with 32-bit address masking enabled,

2
arch/sparc/kernel/init_task.c
View File

@@ -15,7 +15,7 @@ EXPORT_SYMBOL(init_task);
/* .text section in head.S is aligned at 8k boundary and this gets linked
* right after that so that the init_thread_union is aligned properly as well.
* If this is not aligned on a 8k boundry, then you should change code
* If this is not aligned on a 8k boundary, then you should change code
* in etrap.S which assumes it.
*/
union thread_union init_thread_union __init_task_data =

2
arch/sparc/kernel/of_device_64.c
View File

@@ -459,7 +459,7 @@ apply_interrupt_map(struct device_node *dp, struct device_node *pp,
*
* Handle this by deciding that, if we didn't get a
* match in the parent's 'interrupt-map', and the
* parent is an IRQ translater, then use the parent as
* parent is an IRQ translator, then use the parent as
* our IRQ controller.
*/
if (pp->irq_trans)

2
arch/sparc/kernel/perf_event.c
View File

@@ -1027,7 +1027,7 @@ static int sparc_pmu_add(struct perf_event *event, int ef_flags)
/*
* If group events scheduling transaction was started,
* skip the schedulability test here, it will be peformed
* skip the schedulability test here, it will be performed
* at commit time(->commit_txn) as a whole
*/
if (cpuc->group_flag & PERF_EVENT_TXN)

2
arch/sparc/math-emu/Makefile
View File

@@ -2,7 +2,7 @@
# Makefile for the FPU instruction emulation.
#
# supress all warnings - as math.c produces a lot!
# suppress all warnings - as math.c produces a lot!
ccflags-y := -w
obj-y := math_$(BITS).o