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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

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Pull m68knommu fixes from Greg Ungerer:
 "It contains a few small fixes for the non-MMU m68k platforms.  Fixes
  some compilation problems, some broken header definitions, removes an
  unused config option and adds a name for the old 68000 CPU support."

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68k: drop "select EMAC_INC"
  m68knommu: fix misnamed GPIO pin definition for ColdFire 528x CPU
  m68knommu: fix MC68328.h defines
  m68knommu: fix build when CPU is not coldfire
  m68knommu: add CPU_NAME for 68000
This commit is contained in:
Linus Torvalds
2013-03-12 10:20:15 -07:00
parent fa4a6732a8 ef9240f482
commit 4388817f70
5 changed files with 10 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/m68k/Kconfig.machine
View File

@@ -310,7 +310,6 @@ config COBRA5282
config SOM5282EM config SOM5282EM
bool "EMAC.Inc SOM5282EM board support" bool "EMAC.Inc SOM5282EM board support"
depends on M528x depends on M528x
select EMAC_INC
help help
Support for the EMAC.Inc SOM5282EM module. Support for the EMAC.Inc SOM5282EM module.

10
arch/m68k/include/asm/MC68328.h
View File

@@ -293,7 +293,7 @@
/* /*
* Here go the bitmasks themselves * Here go the bitmasks themselves
*/ */
#define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */ #define IMR_MSPIM (1 << SPIM_IRQ_NUM) /* Mask SPI Master interrupt */
#define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */ #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
@@ -327,7 +327,7 @@
#define IWR_ADDR 0xfffff308 #define IWR_ADDR 0xfffff308
#define IWR LONG_REF(IWR_ADDR) #define IWR LONG_REF(IWR_ADDR)
#define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ #define IWR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
#define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ #define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
#define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ #define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
@@ -357,7 +357,7 @@
#define ISR_ADDR 0xfffff30c #define ISR_ADDR 0xfffff30c
#define ISR LONG_REF(ISR_ADDR) #define ISR LONG_REF(ISR_ADDR)
#define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ #define ISR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
#define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ #define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
@@ -391,7 +391,7 @@
#define IPR_ADDR 0xfffff310 #define IPR_ADDR 0xfffff310
#define IPR LONG_REF(IPR_ADDR) #define IPR LONG_REF(IPR_ADDR)
#define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ #define IPR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
#define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ #define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
@@ -757,7 +757,7 @@
/* 'EZ328-compatible definitions */ /* 'EZ328-compatible definitions */
#define TCN_ADDR TCN1_ADDR #define TCN_ADDR TCN1_ADDR
#define TCN TCN #define TCN TCN1
/* /*
* Timer Unit 1 and 2 Status Registers * Timer Unit 1 and 2 Status Registers

3
arch/m68k/kernel/setup_no.c
View File

@@ -57,6 +57,9 @@ void (*mach_reset)(void);
void (*mach_halt)(void); void (*mach_halt)(void);
void (*mach_power_off)(void); void (*mach_power_off)(void);
#ifdef CONFIG_M68000
#define CPU_NAME "MC68000"
#endif
#ifdef CONFIG_M68328 #ifdef CONFIG_M68328
#define CPU_NAME "MC68328" #define CPU_NAME "MC68328"
#endif #endif

2
arch/m68k/mm/init.c
View File

@@ -188,7 +188,7 @@ void __init mem_init(void)
} }
} }
#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) #if defined(CONFIG_MMU) && !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
/* insert pointer tables allocated so far into the tablelist */ /* insert pointer tables allocated so far into the tablelist */
init_pointer_table((unsigned long)kernel_pg_dir); init_pointer_table((unsigned long)kernel_pg_dir);
for (i = 0; i < PTRS_PER_PGD; i++) { for (i = 0; i < PTRS_PER_PGD; i++) {

2
arch/m68k/platform/coldfire/m528x.c
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@@ -69,7 +69,7 @@ static void __init m528x_uarts_init(void)
u8 port; u8 port;
/* make sure PUAPAR is set for UART0 and UART1 */ /* make sure PUAPAR is set for UART0 and UART1 */
port = readb(MCF5282_GPIO_PUAPAR); port = readb(MCFGPIO_PUAPAR);
port |= 0x03 | (0x03 << 2); port |= 0x03 | (0x03 << 2);
writeb(port, MCFGPIO_PUAPAR); writeb(port, MCFGPIO_PUAPAR);
} }