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ixgbe: move Tx ring configuration into a separate function

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This patch moves the Tx ring configuration into a separate function.  In
addition the function drops the setting of the head writeback RO bit since
head writeback is no longer used within ixgbe.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexander Duyck
2010-08-19 13:35:12 +00:00
committed by David S. Miller
parent 120ff942cc
commit 43e69bf0f0
1 changed files with 29 additions and 40 deletions
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69
drivers/net/ixgbe/ixgbe_main.c
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@@ -2424,6 +2424,32 @@ static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
e_info(hw, "Legacy interrupt IVAR setup done\n"); e_info(hw, "Legacy interrupt IVAR setup done\n");
} }
/**
* ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
* @adapter: board private structure
* @ring: structure containing ring specific data
*
* Configure the Tx descriptor ring after a reset.
**/
static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
struct ixgbe_ring *ring)
{
struct ixgbe_hw *hw = &adapter->hw;
u64 tdba = ring->dma;
u16 reg_idx = ring->reg_idx;
IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
(tdba & DMA_BIT_MASK(32)));
IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
ring->count * sizeof(union ixgbe_adv_tx_desc));
IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
ring->head = IXGBE_TDH(reg_idx);
ring->tail = IXGBE_TDT(reg_idx);
}
static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
{ {
struct ixgbe_hw *hw = &adapter->hw; struct ixgbe_hw *hw = &adapter->hw;
@@ -2471,48 +2497,11 @@ static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
**/ **/
static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
{ {
u64 tdba; u32 i;
struct ixgbe_hw *hw = &adapter->hw;
u32 i, j, tdlen, txctrl;
/* Setup the HW Tx Head and Tail descriptor pointers */ /* Setup the HW Tx Head and Tail descriptor pointers */
for (i = 0; i < adapter->num_tx_queues; i++) { for (i = 0; i < adapter->num_tx_queues; i++)
struct ixgbe_ring *ring = adapter->tx_ring[i]; ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
j = ring->reg_idx;
tdba = ring->dma;
tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
(tdba & DMA_BIT_MASK(32)));
IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
adapter->tx_ring[i]->head = IXGBE_TDH(j);
adapter->tx_ring[i]->tail = IXGBE_TDT(j);
/*
* Disable Tx Head Writeback RO bit, since this hoses
* bookkeeping if things aren't delivered in order.
*/
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
break;
case ixgbe_mac_82599EB:
default:
txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
break;
}
txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
break;
case ixgbe_mac_82599EB:
default:
IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
break;
}
}
ixgbe_setup_mtqc(adapter); ixgbe_setup_mtqc(adapter);
} }