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OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz

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According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz.  CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations.  Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Paul Walmsley
2009-05-12 17:26:32 -06:00
committed by paul
parent b2abb271a5
commit 4519c2bf43
4 changed files with 24 additions and 12 deletions
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6
arch/arm/plat-omap/include/mach/sram.h
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@@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2);
u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll);
/* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2);
u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif