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drm/radeon/kms: allow rendering while no colorbuffer is set on r300

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Because hardware cannot disable all colorbuffers directly to do depth-only
rendering, a user should:
- disable reading from a colorbuffer in blending
- disable fastfill
- set the color channel mask to 0 to prevent writing to a colorbuffer

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Marek Olšák
2009-12-17 06:02:28 +01:00
committed by Dave Airlie
parent 5ea597f376
commit 46c64d4bfa
3 changed files with 19 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/radeon/r100.c
View File

@@ -2881,6 +2881,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
for (i = 0; i < track->num_cb; i++) { for (i = 0; i < track->num_cb; i++) {
if (track->cb[i].robj == NULL) { if (track->cb[i].robj == NULL) {
if (!(track->fastfill || track->color_channel_mask ||
track->blend_read_enable)) {
continue;
}
DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
return -EINVAL; return -EINVAL;
} }

4
drivers/gpu/drm/radeon/r100_track.h
View File

@@ -67,13 +67,15 @@ struct r100_cs_track {
unsigned immd_dwords; unsigned immd_dwords;
unsigned num_arrays; unsigned num_arrays;
unsigned max_indx; unsigned max_indx;
unsigned color_channel_mask;
struct r100_cs_track_array arrays[11]; struct r100_cs_track_array arrays[11];
struct r100_cs_track_cb cb[R300_MAX_CB]; struct r100_cs_track_cb cb[R300_MAX_CB];
struct r100_cs_track_cb zb; struct r100_cs_track_cb zb;
struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
bool z_enabled; bool z_enabled;
bool separate_cube; bool separate_cube;
bool fastfill;
bool blend_read_enable;
}; };
int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);

12
drivers/gpu/drm/radeon/r300.c
View File

@@ -992,6 +992,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
} }
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
break; break;
case 0x4e0c:
/* RB3D_COLOR_CHANNEL_MASK */
track->color_channel_mask = idx_value;
break;
case 0x4d1c:
/* ZB_BW_CNTL */
track->fastfill = !!(idx_value & (1 << 2));
break;
case 0x4e04:
/* RB3D_BLENDCNTL */
track->blend_read_enable = !!(idx_value & (1 << 2));
break;
case 0x4be8: case 0x4be8:
/* valid register only on RV530 */ /* valid register only on RV530 */
if (p->rdev->family == CHIP_RV530) if (p->rdev->family == CHIP_RV530)