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Blackfin: dpmc: optimize SIC_IWR programming a little

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For parts with more than one SIC_IWR, we can optimize the writing
a little bit using better Blackfin insns.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
2011-06-26 14:07:17 -04:00
parent 01f8e34c98
commit 4705a25c06
1 changed files with 6 additions and 9 deletions
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15
arch/blackfin/mach-common/dpmc_modes.S
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@@ -239,21 +239,18 @@ ENDPROC(_unset_dram_srfs)
ENTRY(_set_sic_iwr) ENTRY(_set_sic_iwr)
#ifdef SIC_IWR0 #ifdef SIC_IWR0
P0.H = hi(SIC_IWR0); P0.H = hi(SYSMMR_BASE);
P0.L = lo(SIC_IWR0); P0.L = lo(SYSMMR_BASE);
P1.H = hi(SIC_IWR1); [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
P1.L = lo(SIC_IWR1); [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
[P1] = R1;
# ifdef SIC_IWR2 # ifdef SIC_IWR2
P1.H = hi(SIC_IWR2); [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
P1.L = lo(SIC_IWR2);
[P1] = R2;
# endif # endif
#else #else
P0.H = hi(SIC_IWR); P0.H = hi(SIC_IWR);
P0.L = lo(SIC_IWR); P0.L = lo(SIC_IWR);
#endif
[P0] = R0; [P0] = R0;
#endif
SSYNC; SSYNC;
RTS; RTS;