[ARM] 4434/1: PXA: remove PXA_IRQ_SKIP
1. PXA_IRQ_SKIP is defined to be 7 on PXA25x so that the first IRQ starts from zero. This makes IRQ numbering inconsistent between PXA25x and PXA27x. Remove this macro so that the same IRQ_XXXXX definition has the same value on both PXA25x and PXA27x. 2. make IRQ_SSP3..IRQ_PWRI2C valid only if PXA27x is defined, this avoids unintentional use of these macros on PXA25x Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@@ -30,12 +30,12 @@
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static void pxa_mask_low_irq(unsigned int irq)
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static void pxa_mask_low_irq(unsigned int irq)
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{
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{
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ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
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ICMR &= ~(1 << irq);
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}
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}
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static void pxa_unmask_low_irq(unsigned int irq)
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static void pxa_unmask_low_irq(unsigned int irq)
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{
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{
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ICMR |= (1 << (irq + PXA_IRQ_SKIP));
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ICMR |= (1 << irq);
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}
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}
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static int pxa_set_wake(unsigned int irq, unsigned int on)
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static int pxa_set_wake(unsigned int irq, unsigned int on)
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@@ -75,12 +75,12 @@ static struct irq_chip pxa_internal_chip_low = {
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static void pxa_mask_high_irq(unsigned int irq)
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static void pxa_mask_high_irq(unsigned int irq)
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{
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{
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ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP));
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ICMR2 &= ~(1 << (irq - 32));
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}
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}
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static void pxa_unmask_high_irq(unsigned int irq)
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static void pxa_unmask_high_irq(unsigned int irq)
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{
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{
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ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP));
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ICMR2 |= (1 << (irq - 32));
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}
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}
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static struct irq_chip pxa_internal_chip_high = {
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static struct irq_chip pxa_internal_chip_high = {
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@@ -351,7 +351,7 @@ void __init pxa_init_irq(void)
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/* GPIO 0 and 1 must have their mask bit always set */
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/* GPIO 0 and 1 must have their mask bit always set */
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GPIO_IRQ_mask[0] = 3;
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GPIO_IRQ_mask[0] = 3;
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for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
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for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
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set_irq_chip(irq, &pxa_internal_chip_low);
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set_irq_chip(irq, &pxa_internal_chip_low);
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set_irq_handler(irq, handle_level_irq);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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set_irq_flags(irq, IRQF_VALID);
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@@ -34,6 +34,6 @@
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rsb \irqstat, \irqnr, #0
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rsb \irqstat, \irqnr, #0
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and \irqstat, \irqstat, \irqnr
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and \irqstat, \irqstat, \irqnr
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clz \irqnr, \irqstat
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clz \irqnr, \irqstat
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rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP)
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rsb \irqnr, \irqnr, #31
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1001:
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1001:
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.endm
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.endm
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@@ -11,14 +11,9 @@
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*/
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*/
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#define PXA_IRQ(x) (x)
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#ifdef CONFIG_PXA27x
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#ifdef CONFIG_PXA27x
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#define PXA_IRQ_SKIP 0
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#else
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#define PXA_IRQ_SKIP 7
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#endif
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#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP)
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#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
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#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
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#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
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#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
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#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
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#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
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@@ -26,6 +21,8 @@
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#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
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#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
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#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
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#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
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#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
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#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
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#endif
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#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
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#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
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#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
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#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
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#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
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#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
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