x86,mrst: Power control commands update
On the Intel MID devices SCU commands are issued to manage power off and the like. We need to issue different ones for non-Lincroft based devices. Signed-off-by: Alek Du <alek.du@intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -76,6 +76,20 @@ struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
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EXPORT_SYMBOL_GPL(sfi_mrtc_array);
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int sfi_mrtc_num;
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static void mrst_power_off(void)
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{
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if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
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intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 1);
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}
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static void mrst_reboot(void)
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{
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if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
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intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
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else
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intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
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}
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/* parse all the mtimer info to a static mtimer array */
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static int __init sfi_parse_mtmr(struct sfi_table_header *table)
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{
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@ -265,17 +279,6 @@ static int mrst_i8042_detect(void)
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return 0;
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}
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/* Reboot and power off are handled by the SCU on a MID device */
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static void mrst_power_off(void)
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{
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intel_scu_ipc_simple_command(0xf1, 1);
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}
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static void mrst_reboot(void)
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{
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intel_scu_ipc_simple_command(0xf1, 0);
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}
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/*
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* Moorestown does not have external NMI source nor port 0x61 to report
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* NMI status. The possible NMI sources are from pmu as a result of NMI
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