From 864c6c22e9a5742b0f43c983b6c405d52817bacd Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 16 Nov 2011 15:42:28 +0100 Subject: [PATCH 001/119] MIPS: Alchemy: Fix PCI PM Move PCI Controller PM to syscore_ops since the platform_driver PM methods are called way too late on resume and far too early on suspend (after and before PCI device resume/suspend). This also allows to simplify wired entry management a bit. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3007/ Signed-off-by: Ralf Baechle --- arch/mips/pci/pci-alchemy.c | 137 ++++++++++++++++++------------------ 1 file changed, 67 insertions(+), 70 deletions(-) diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index b5ce041cdafb..b5eddf533c0b 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -41,6 +42,12 @@ struct alchemy_pci_context { int (*board_pci_idsel)(unsigned int devsel, int assert); }; +/* for syscore_ops. There's only one PCI controller on Alchemy chips, so this + * should suffice for now. + */ +static struct alchemy_pci_context *__alchemy_pci_ctx; + + /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr * in arch/mips/alchemy/common/setup.c */ @@ -99,18 +106,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, return -1; } - /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired - * on resume, clearing our wired entry. Unfortunately the ->resume() - * callback is called way way way too late (and ->suspend() too early) - * to have them destroy and recreate it. Instead just test if c0_wired - * is now lower than the index we retrieved before suspending and then - * recreate the entry if necessary. Of course this is totally bonkers - * and breaks as soon as someone else adds another wired entry somewhere - * else. Anyone have any ideas how to handle this better? - */ - if (unlikely(read_c0_wired() < ctx->wired_entry)) - alchemy_pci_wired_entry(ctx); - local_irq_save(flags); r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; r |= PCI_STATCMD_STATUS(0x2000); @@ -304,6 +299,62 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert) return 1; /* success */ } +/* save PCI controller register contents. */ +static int alchemy_pci_suspend(void) +{ + struct alchemy_pci_context *ctx = __alchemy_pci_ctx; + if (!ctx) + return 0; + + ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); + ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; + ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); + ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); + ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); + ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); + ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); + ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); + ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); + ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); + ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); + ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); + + return 0; +} + +static void alchemy_pci_resume(void) +{ + struct alchemy_pci_context *ctx = __alchemy_pci_ctx; + if (!ctx) + return; + + __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); + __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); + __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); + __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); + __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); + __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); + __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); + __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); + __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); + __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); + __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); + wmb(); + __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); + wmb(); + + /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired + * on resume, making it necessary to recreate it as soon as possible. + */ + ctx->wired_entry = 8191; /* impossibly high value */ + alchemy_pci_wired_entry(ctx); /* install it */ +} + +static struct syscore_ops alchemy_pci_pmops = { + .suspend = alchemy_pci_suspend, + .resume = alchemy_pci_resume, +}; + static int __devinit alchemy_pci_probe(struct platform_device *pdev) { struct alchemy_pci_platdata *pd = pdev->dev.platform_data; @@ -396,7 +447,8 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev) ret = -ENOMEM; goto out4; } - ctx->wired_entry = 8192; /* impossibly high value */ + ctx->wired_entry = 8191; /* impossibly high value */ + alchemy_pci_wired_entry(ctx); /* install it */ set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); @@ -408,7 +460,9 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev) __raw_writel(val, ctx->regs + PCI_REG_CONFIG); wmb(); + __alchemy_pci_ctx = ctx; platform_set_drvdata(pdev, ctx); + register_syscore_ops(&alchemy_pci_pmops); register_pci_controller(&ctx->alchemy_pci_ctrl); return 0; @@ -425,68 +479,11 @@ out: return ret; } - -#ifdef CONFIG_PM -/* save PCI controller register contents. */ -static int alchemy_pci_suspend(struct device *dev) -{ - struct alchemy_pci_context *ctx = dev_get_drvdata(dev); - - ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); - ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; - ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); - ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); - ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); - ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); - ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); - ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); - ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); - ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); - ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); - ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); - - return 0; -} - -static int alchemy_pci_resume(struct device *dev) -{ - struct alchemy_pci_context *ctx = dev_get_drvdata(dev); - - __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); - __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); - __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); - __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); - __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); - __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); - __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); - __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); - __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); - __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); - __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); - wmb(); - __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); - wmb(); - - return 0; -} - -static const struct dev_pm_ops alchemy_pci_pmops = { - .suspend = alchemy_pci_suspend, - .resume = alchemy_pci_resume, -}; - -#define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops) - -#else -#define ALCHEMY_PCICTL_PM NULL -#endif - static struct platform_driver alchemy_pcictl_driver = { .probe = alchemy_pci_probe, .driver = { .name = "alchemy-pci", .owner = THIS_MODULE, - .pm = ALCHEMY_PCICTL_PM, }, }; From ab75dc02c151c9d2a2fd446334d740b097a3b9db Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 17 Nov 2011 15:07:31 +0000 Subject: [PATCH 002/119] MIPS: Fix up inconsistency in panic() string argument. Panic() invokes printk() to add a \n internally, so panic arguments should not themselves end in \n. Panic invocations in arch/mips and elsewhere are inconsistently sometimes terminating in \n, sometimes not. Signed-off-by: Ralf Baechle --- arch/mips/ar7/platform.c | 2 +- arch/mips/ar7/setup.c | 2 +- arch/mips/ath79/setup.c | 2 +- arch/mips/bcm47xx/setup.c | 4 ++-- arch/mips/cavium-octeon/setup.c | 6 +++--- arch/mips/cavium-octeon/smp.c | 2 +- arch/mips/jz4740/board-qi_lb60.c | 2 +- arch/mips/kernel/smtc.c | 4 ++-- arch/mips/kernel/traps.c | 4 ++-- arch/mips/lantiq/clk.c | 4 ++-- arch/mips/lantiq/irq.c | 12 ++++++------ arch/mips/lantiq/xway/dma.c | 6 +++--- arch/mips/lantiq/xway/ebu.c | 6 +++--- arch/mips/lantiq/xway/pmu.c | 8 ++++---- arch/mips/lantiq/xway/reset.c | 6 +++--- arch/mips/mm/c-octeon.c | 2 +- arch/mips/pci/msi-octeon.c | 2 +- arch/mips/pmc-sierra/msp71xx/msp_setup.c | 2 +- arch/mips/sgi-ip27/ip27-irq.c | 4 ++-- 19 files changed, 40 insertions(+), 40 deletions(-) diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 33ffecf6a6d6..60102392af01 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -536,7 +536,7 @@ static int __init ar7_register_uarts(void) bus_clk = clk_get(NULL, "bus"); if (IS_ERR(bus_clk)) - panic("unable to get bus clk\n"); + panic("unable to get bus clk"); uart_port.type = PORT_AR7; uart_port.uartclk = clk_get_rate(bus_clk) / 2; diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c index f20b53e597c4..9a357fffcfbe 100644 --- a/arch/mips/ar7/setup.c +++ b/arch/mips/ar7/setup.c @@ -96,7 +96,7 @@ void __init plat_mem_setup(void) io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000); if (!io_base) - panic("Can't remap IO base!\n"); + panic("Can't remap IO base!"); set_io_port_base(io_base); prom_meminit(); diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 159b42f106b0..1cf60e1d9dd3 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -134,7 +134,7 @@ static void __init ath79_detect_sys_type(void) break; default: - panic("ath79: unknown SoC, id:0x%08x\n", id); + panic("ath79: unknown SoC, id:0x%08x", id); } sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 1cfdda03546a..aab6b0c40a75 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -289,7 +289,7 @@ static void __init bcm47xx_register_ssb(void) err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE, bcm47xx_get_invariants); if (err) - panic("Failed to initialize SSB bus (err %d)\n", err); + panic("Failed to initialize SSB bus (err %d)", err); mcore = &bcm47xx_bus.ssb.mipscore; if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) { @@ -314,7 +314,7 @@ static void __init bcm47xx_register_bcma(void) err = bcma_host_soc_register(&bcm47xx_bus.bcma); if (err) - panic("Failed to initialize BCMA bus (err %d)\n", err); + panic("Failed to initialize BCMA bus (err %d)", err); } #endif diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 2d9028f1474c..853bac4f25b2 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -767,11 +767,11 @@ void prom_free_prom_memory(void) : "=r" (insn) : : "$31", "memory"); if ((insn >> 26) != 0x33) - panic("No PREF instruction at Core-14449 probe point.\n"); + panic("No PREF instruction at Core-14449 probe point."); if (((insn >> 16) & 0x1f) != 28) panic("Core-14449 WAR not in place (%04x).\n" - "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn); + "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); } #ifdef CONFIG_CAVIUM_DECODE_RSL cvmx_interrupt_rsl_enable(); @@ -779,7 +779,7 @@ void prom_free_prom_memory(void) /* Add an interrupt handler for general failures. */ if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, "RML/RSL", octeon_rlm_interrupt)) { - panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); + panic("Unable to request_irq(OCTEON_IRQ_RML)"); } #endif } diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index efcfff4d4627..b1535fe409d4 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -210,7 +210,7 @@ void octeon_prepare_cpus(unsigned int max_cpus) if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", mailbox_interrupt)) { - panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); + panic("Cannot request_irq(OCTEON_IRQ_MBOX0)"); } } diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index c3b04be3fb2b..639e3ce6c264 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -488,7 +488,7 @@ static int __init qi_lb60_board_setup(void) board_gpio_setup(); if (qi_lb60_init_platform_devices()) - panic("Failed to initialize platform devices\n"); + panic("Failed to initialize platform devices"); return 0; } diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index f0895e70e283..b1eea63cc988 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -559,7 +559,7 @@ void smtc_prepare_cpus(int cpus) pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); if (pipi == NULL) - panic("kmalloc of IPI message buffers failed\n"); + panic("kmalloc of IPI message buffers failed"); else printk("IPI buffer pool of %d buffers\n", nipi); for (i = 0; i < nipi; i++) { @@ -813,7 +813,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) if (pipi == NULL) { bust_spinlocks(1); mips_mt_regdump(dvpe()); - panic("IPI Msg. Buffers Depleted\n"); + panic("IPI Msg. Buffers Depleted"); } pipi->type = type; pipi->arg = (void *)action; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 5c8a49d55054..363c4764b818 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -400,7 +400,7 @@ void __noreturn die(const char *str, struct pt_regs *regs) panic("Fatal exception in interrupt"); if (panic_on_oops) { - printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); + printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); ssleep(5); panic("Fatal exception"); } @@ -1150,7 +1150,7 @@ asmlinkage void do_mt(struct pt_regs *regs) asmlinkage void do_dsp(struct pt_regs *regs) { if (cpu_has_dsp) - panic("Unexpected DSP exception\n"); + panic("Unexpected DSP exception"); force_sig(SIGILL, current); } diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index 77ed70fc2fe5..412814fdd3ee 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -134,11 +134,11 @@ void __init plat_time_init(void) struct clk *clk; if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) - panic("Failed to insert cgu memory\n"); + panic("Failed to insert cgu memory"); if (request_mem_region(ltq_cgu_resource.start, resource_size(<q_cgu_resource), "cgu") < 0) - panic("Failed to request cgu memory\n"); + panic("Failed to request cgu memory"); ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, resource_size(<q_cgu_resource)); diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index f9737bb3c5ab..51fa0a4ba556 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -249,28 +249,28 @@ void __init arch_init_irq(void) int i; if (insert_resource(&iomem_resource, <q_icu_resource) < 0) - panic("Failed to insert icu memory\n"); + panic("Failed to insert icu memory"); if (request_mem_region(ltq_icu_resource.start, resource_size(<q_icu_resource), "icu") < 0) - panic("Failed to request icu memory\n"); + panic("Failed to request icu memory"); ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, resource_size(<q_icu_resource)); if (!ltq_icu_membase) - panic("Failed to remap icu memory\n"); + panic("Failed to remap icu memory"); if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) - panic("Failed to insert eiu memory\n"); + panic("Failed to insert eiu memory"); if (request_mem_region(ltq_eiu_resource.start, resource_size(<q_eiu_resource), "eiu") < 0) - panic("Failed to request eiu memory\n"); + panic("Failed to request eiu memory"); ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, resource_size(<q_eiu_resource)); if (!ltq_eiu_membase) - panic("Failed to remap eiu memory\n"); + panic("Failed to remap eiu memory"); /* make sure all irqs are turned off by default */ for (i = 0; i < 5; i++) diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index cbb6ae5747b9..b210e936c7c3 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -222,17 +222,17 @@ ltq_dma_init(void) /* insert and request the memory region */ if (insert_resource(&iomem_resource, <q_dma_resource) < 0) - panic("Failed to insert dma memory\n"); + panic("Failed to insert dma memory"); if (request_mem_region(ltq_dma_resource.start, resource_size(<q_dma_resource), "dma") < 0) - panic("Failed to request dma memory\n"); + panic("Failed to request dma memory"); /* remap dma register range */ ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, resource_size(<q_dma_resource)); if (!ltq_dma_membase) - panic("Failed to remap dma memory\n"); + panic("Failed to remap dma memory"); /* power up and reset the dma engine */ ltq_pmu_enable(PMU_DMA); diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c index 033b3184c7a7..862e3e830680 100644 --- a/arch/mips/lantiq/xway/ebu.c +++ b/arch/mips/lantiq/xway/ebu.c @@ -32,17 +32,17 @@ static int __init lantiq_ebu_init(void) { /* insert and request the memory region */ if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) - panic("Failed to insert ebu memory\n"); + panic("Failed to insert ebu memory"); if (request_mem_region(ltq_ebu_resource.start, resource_size(<q_ebu_resource), "ebu") < 0) - panic("Failed to request ebu memory\n"); + panic("Failed to request ebu memory"); /* remap ebu register range */ ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, resource_size(<q_ebu_resource)); if (!ltq_ebu_membase) - panic("Failed to remap ebu memory\n"); + panic("Failed to remap ebu memory"); /* make sure to unprotect the memory region where flash is located */ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c index 39f0d2641cbf..fe85361e032e 100644 --- a/arch/mips/lantiq/xway/pmu.c +++ b/arch/mips/lantiq/xway/pmu.c @@ -40,7 +40,7 @@ void ltq_pmu_enable(unsigned int module) do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); if (!err) - panic("activating PMU module failed!\n"); + panic("activating PMU module failed!"); } EXPORT_SYMBOL(ltq_pmu_enable); @@ -53,16 +53,16 @@ EXPORT_SYMBOL(ltq_pmu_disable); int __init ltq_pmu_init(void) { if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) - panic("Failed to insert pmu memory\n"); + panic("Failed to insert pmu memory"); if (request_mem_region(ltq_pmu_resource.start, resource_size(<q_pmu_resource), "pmu") < 0) - panic("Failed to request pmu memory\n"); + panic("Failed to request pmu memory"); ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, resource_size(<q_pmu_resource)); if (!ltq_pmu_membase) - panic("Failed to remap pmu memory\n"); + panic("Failed to remap pmu memory"); return 0; } diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c index 3d41f0bb5bf7..8b66bd87f0c1 100644 --- a/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c @@ -69,17 +69,17 @@ static int __init mips_reboot_setup(void) { /* insert and request the memory region */ if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) - panic("Failed to insert rcu memory\n"); + panic("Failed to insert rcu memory"); if (request_mem_region(ltq_rcu_resource.start, resource_size(<q_rcu_resource), "rcu") < 0) - panic("Failed to request rcu memory\n"); + panic("Failed to request rcu memory"); /* remap rcu register range */ ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, resource_size(<q_rcu_resource)); if (!ltq_rcu_membase) - panic("Failed to remap rcu memory\n"); + panic("Failed to remap rcu memory"); _machine_restart = ltq_machine_restart; _machine_halt = ltq_machine_halt; diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index daa81f7284ac..cf7895db0739 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -223,7 +223,7 @@ static void __cpuinit probe_octeon(void) break; default: - panic("Unsupported Cavium Networks CPU type\n"); + panic("Unsupported Cavium Networks CPU type"); break; } diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 5d530f89d872..d37be36dc659 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -162,7 +162,7 @@ msi_irq_allocated: msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; break; default: - panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n"); + panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type"); } msg.data = irq - OCTEON_IRQ_MSI_BIT0; diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index 655308a4e1cd..7a834b2f8a5f 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -209,7 +209,7 @@ void __init prom_init(void) default: /* we don't recognize the machine */ mips_machtype = MACH_UNKNOWN; - panic("***Bogosity factor five***, exiting\n"); + panic("***Bogosity factor five***, exiting"); break; } diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index f90dce315e04..ec3782d31894 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -73,7 +73,7 @@ static inline int alloc_level(int cpu, int irq) level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); if (level >= LEVELS_PER_SLICE) - panic("Cpu %d flooded with devices\n", cpu); + panic("Cpu %d flooded with devices", cpu); __set_bit(level, hub->irq_alloc_mask); si->level_to_irq[level] = irq; @@ -96,7 +96,7 @@ static inline int find_level(cpuid_t *cpunum, int irq) } } - panic("Could not identify cpu/level for irq %d\n", irq); + panic("Could not identify cpu/level for irq %d", irq); } /* From 3d18c98367eac23555ea4887c4f570423474eeaf Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 28 Nov 2011 16:11:28 +0000 Subject: [PATCH 003/119] MIPS: Fix Jazz 64-bit build error. Move add_wired_entry to its own header file from where it will be always included. Patch up other users of add_wired_entry to also include the header as needed. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/pgtable-32.h | 6 ------ arch/mips/include/asm/tlbmisc.h | 10 ++++++++++ arch/mips/jazz/irq.c | 1 + arch/mips/jazz/setup.c | 1 + arch/mips/mm/tlb-r3k.c | 1 + arch/mips/mm/tlb-r4k.c | 1 + arch/mips/pci/pci-alchemy.c | 1 + 7 files changed, 15 insertions(+), 6 deletions(-) create mode 100644 arch/mips/include/asm/tlbmisc.h diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index 8a153d2fa62a..469390656c3f 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -18,12 +18,6 @@ #include -/* - * - add_wired_entry() add a fixed TLB entry, and move wired register - */ -extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask); - /* * - add_temporary_entry() add a temporary TLB entry. We use TLB entries * starting at the top and working down. This is for populating the diff --git a/arch/mips/include/asm/tlbmisc.h b/arch/mips/include/asm/tlbmisc.h new file mode 100644 index 000000000000..3a452282cba0 --- /dev/null +++ b/arch/mips/include/asm/tlbmisc.h @@ -0,0 +1,10 @@ +#ifndef __ASM_TLBMISC_H +#define __ASM_TLBMISC_H + +/* + * - add_wired_entry() add a fixed TLB entry, and move wired register + */ +extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask); + +#endif /* __ASM_TLBMISC_H */ diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index ca9bd2069142..99ab86ffa4c0 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -20,6 +20,7 @@ #include #include #include +#include static DEFINE_RAW_SPINLOCK(r4030_lock); diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index 0d0f054a02f4..820e926dacbc 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -21,6 +21,7 @@ #include #include #include +#include extern asmlinkage void jazz_handle_int(void); diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index 87bb85d8d537..ed1fa460f84e 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 0d394e0e8837..d163455552b0 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -19,6 +19,7 @@ #include #include #include +#include extern void build_tlb_refill_handler(void); diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index b5eddf533c0b..ec125bed721c 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -17,6 +17,7 @@ #include #include +#include #ifdef CONFIG_DEBUG_PCI #define DBG(x...) printk(KERN_DEBUG x) From 3f724080a3e91d76ba6d5cacd3cf0a0cf16d121a Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 2 Nov 2011 12:53:44 +0100 Subject: [PATCH 004/119] MIPS: Alchemy: remove PB1000 support Noone seems to have test hardware or care anymore. Drop PB1000 support and along with it the old Alchemy PCMCIA socket driver. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: linux-pcmcia@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/2881/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 9 - arch/mips/alchemy/Platform | 7 - arch/mips/alchemy/common/irq.c | 11 - arch/mips/alchemy/devboards/Makefile | 1 - arch/mips/alchemy/devboards/pb1000/Makefile | 8 - .../alchemy/devboards/pb1000/board_setup.c | 209 ------- arch/mips/alchemy/devboards/prom.c | 2 +- arch/mips/include/asm/mach-pb1x00/pb1000.h | 87 --- drivers/net/irda/au1k_ir.c | 5 +- drivers/pcmcia/Kconfig | 4 - drivers/pcmcia/Makefile | 4 - drivers/pcmcia/au1000_generic.c | 545 ------------------ drivers/pcmcia/au1000_generic.h | 135 ----- drivers/pcmcia/au1000_pb1x00.c | 294 ---------- 14 files changed, 2 insertions(+), 1319 deletions(-) delete mode 100644 arch/mips/alchemy/devboards/pb1000/Makefile delete mode 100644 arch/mips/alchemy/devboards/pb1000/board_setup.c delete mode 100644 arch/mips/include/asm/mach-pb1x00/pb1000.h delete mode 100644 drivers/pcmcia/au1000_generic.c delete mode 100644 drivers/pcmcia/au1000_generic.h delete mode 100644 drivers/pcmcia/au1000_pb1x00.c diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 2a68be6a1b97..5a48387d0751 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -78,15 +78,6 @@ config MIPS_MIRAGE select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_PB1000 - bool "Alchemy PB1000 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - select SWAP_IO_SPACE - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_PB1100 bool "Alchemy PB1100 board" select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 96e9e41f1b2a..4e079672f9bf 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -4,13 +4,6 @@ platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/ -# -# AMD Alchemy Pb1000 eval board -# -platform-$(CONFIG_MIPS_PB1000) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 -load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000 - # # AMD Alchemy Pb1100 eval board # diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 8b60ba0675e2..2a94a64b7333 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -35,9 +35,6 @@ #include #include #include -#ifdef CONFIG_MIPS_PB1000 -#include -#endif /* Interrupt Controller register offsets */ #define IC_CFG0RD 0x40 @@ -265,14 +262,6 @@ static void au1x_ic1_unmask(struct irq_data *d) __raw_writel(1 << bit, base + IC_MASKSET); __raw_writel(1 << bit, base + IC_WAKESET); - -/* very hacky. does the pb1000 cpld auto-disable this int? - * nowhere in the current kernel sources is it disabled. --mlau - */ -#if defined(CONFIG_MIPS_PB1000) - if (d->irq == AU1000_GPIO15_INT) - __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */ -#endif wmb(); } diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 826449c817c3..bea80d787781 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -4,7 +4,6 @@ obj-y += prom.o bcsr.o platform.o obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_MIPS_PB1000) += pb1000/ obj-$(CONFIG_MIPS_PB1100) += pb1100/ obj-$(CONFIG_MIPS_PB1200) += pb1200/ obj-$(CONFIG_MIPS_PB1500) += pb1500/ diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile deleted file mode 100644 index 97c6615ba2bb..000000000000 --- a/arch/mips/alchemy/devboards/pb1000/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# -# Makefile for the Alchemy Semiconductor Pb1000 board. -# - -obj-y := board_setup.o diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c deleted file mode 100644 index e64fdcbf75d0..000000000000 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../platform.h" - -const char *get_system_type(void) -{ - return "Alchemy Pb1000"; -} - -static void board_reset(char *c) -{ - asm volatile ("jr %0" : : "r" (0xbfc00000)); -} - -static void board_power_off(void) -{ - while (1) - asm volatile ( - " .set mips32 \n" - " wait \n" - " .set mips0 \n"); -} - -void __init board_setup(void) -{ - u32 pin_func, static_cfg0; - u32 sys_freqctrl, sys_clksrc; - u32 prid = read_c0_prid(); - - sys_freqctrl = 0; - sys_clksrc = 0; - - /* Set AUX clock to 12 MHz * 8 = 96 MHz */ - au_writel(8, SYS_AUXPLL); - alchemy_gpio1_input_enable(); - udelay(100); - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - /* Zero and disable FREQ2 */ - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* Zero and disable USBH/USBD clocks */ - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | - SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); - au_writel(sys_clksrc, SYS_CLKSRC); - - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | - SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); - - switch (prid & 0x000000FF) { - case 0x00: /* DA */ - case 0x01: /* HA */ - case 0x02: /* HB */ - /* CPU core freq to 48 MHz to slow it way down... */ - au_writel(4, SYS_CPUPLL); - - /* - * Setup 48 MHz FREQ2 from CPUPLL for USB Host - * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz - */ - sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* CPU core freq to 384 MHz */ - au_writel(0x20, SYS_CPUPLL); - - printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n"); - break; - - default: /* HC and newer */ - /* FREQ2 = aux / 2 = 48 MHz */ - sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | - SYS_FC_FE2 | SYS_FC_FS2; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - break; - } - - /* - * Route 48 MHz FREQ2 into USB Host and/or Device - */ - sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT; - au_writel(sys_clksrc, SYS_CLKSRC); - - /* Configure pins GPIO[14:9] as GPIO */ - pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB); - - /* 2nd USB port is USB host */ - pin_func |= SYS_PF_USB; - - au_writel(pin_func, SYS_PINFUNC); - - alchemy_gpio_direction_input(11); - alchemy_gpio_direction_input(13); - alchemy_gpio_direction_output(4, 0); - alchemy_gpio_direction_output(5, 0); -#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ - - /* Make GPIO 15 an input (for interrupt line) */ - pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF; - /* We don't need I2S, so make it available for GPIO[31:29] */ - pin_func |= SYS_PF_I2S; - au_writel(pin_func, SYS_PINFUNC); - - alchemy_gpio_direction_input(15); - - static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00; - au_writel(static_cfg0, MEM_STCFG0); - - /* configure RCE2* for LCD */ - au_writel(0x00000004, MEM_STCFG2); - - /* MEM_STTIME2 */ - au_writel(0x09000000, MEM_STTIME2); - - /* Set 32-bit base address decoding for RCE2* */ - au_writel(0x10003ff0, MEM_STADDR2); - - /* - * PCI CPLD setup - * Expand CE0 to cover PCI - */ - au_writel(0x11803e40, MEM_STADDR1); - - /* Burst visibility on */ - au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0); - - au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */ - au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */ - - /* Setup the static bus controller */ - au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ - au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ - au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ - - /* - * Enable Au1000 BCLK switching - note: sed1356 must not use - * its BCLK (Au1000 LCLK) for any timings - */ - switch (prid & 0x000000FF) { - case 0x00: /* DA */ - case 0x01: /* HA */ - case 0x02: /* HB */ - break; - default: /* HC and newer */ - /* - * Enable sys bus clock divider when IDLE state or no bus - * activity. - */ - au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); - break; - } - - pm_power_off = board_power_off; - _machine_halt = board_power_off; - _machine_restart = board_reset; -} - -static int __init pb1000_init_irq(void) -{ - irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); - return 0; -} -arch_initcall(pb1000_init_irq); - -static int __init pb1000_device_init(void) -{ - return db1x_register_norflash(8 * 1024 * 1024, 4, 0); -} -device_initcall(pb1000_device_init); diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index e5306b56da6d..56d7ea52fd97 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -33,7 +33,7 @@ #include #include -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \ +#if defined(CONFIG_MIPS_DB1000) || \ defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h deleted file mode 100644 index 65059255dc1e..000000000000 --- a/arch/mips/include/asm/mach-pb1x00/pb1000.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Alchemy Semi Pb1000 Reference Board - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1000_H -#define __ASM_PB1000_H - -/* PCMCIA PB1000 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -#define PB1000_PCR 0xBE000000 -# define PCR_SLOT_0_VPP0 (1 << 0) -# define PCR_SLOT_0_VPP1 (1 << 1) -# define PCR_SLOT_0_VCC0 (1 << 2) -# define PCR_SLOT_0_VCC1 (1 << 3) -# define PCR_SLOT_0_RST (1 << 4) -# define PCR_SLOT_1_VPP0 (1 << 8) -# define PCR_SLOT_1_VPP1 (1 << 9) -# define PCR_SLOT_1_VCC0 (1 << 10) -# define PCR_SLOT_1_VCC1 (1 << 11) -# define PCR_SLOT_1_RST (1 << 12) - -#define PB1000_MDR 0xBE000004 -# define MDR_PI (1 << 5) /* PCMCIA int latch */ -# define MDR_EPI (1 << 14) /* enable PCMCIA int */ -# define MDR_CPI (1 << 15) /* clear PCMCIA int */ - -#define PB1000_ACR1 0xBE000008 -# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */ -# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */ -# define ACR1_SLOT_0_READY (1 << 2) /* ready */ -# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */ -# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */ -# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */ -# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */ -# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */ -# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */ -# define ACR1_SLOT_1_READY (1 << 10) /* ready */ -# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */ -# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */ -# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */ -# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */ - -#define CPLD_AUX0 0xBE00000C -#define CPLD_AUX1 0xBE000010 -#define CPLD_AUX2 0xBE000014 - -/* Voltage levels */ - -/* VPPEN1 - VPPEN0 */ -#define VPP_GND ((0 << 1) | (0 << 0)) -#define VPP_5V ((1 << 1) | (0 << 0)) -#define VPP_3V ((0 << 1) | (1 << 0)) -#define VPP_12V ((0 << 1) | (1 << 0)) -#define VPP_HIZ ((1 << 1) | (1 << 0)) - -/* VCCEN1 - VCCEN0 */ -#define VCC_3V ((0 << 1) | (1 << 0)) -#define VCC_5V ((1 << 1) | (0 << 0)) -#define VCC_HIZ ((0 << 1) | (0 << 0)) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) -#endif /* __ASM_PB1000_H */ diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index a3d696a9456a..d1a77ef9b9e8 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c @@ -32,10 +32,7 @@ #include #include #include -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) -#include -#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) -#include +#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) #include #else #error au1k_ir: unsupported board diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 6e318ce41136..c022b5cedcf9 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -155,10 +155,6 @@ config PCMCIA_M8XX This driver is also available as a module called m8xx_pcmcia. -config PCMCIA_AU1X00 - tristate "Au1x00 pcmcia support" - depends on MIPS_ALCHEMY && PCMCIA - config PCMCIA_ALCHEMY_DEVBOARD tristate "Alchemy Db/Pb1xxx PCMCIA socket services" depends on MIPS_ALCHEMY && PCMCIA diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 29935ea921df..ec543a4ff2e4 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_base.o sa1100_cs.o obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_base.o sa1111_cs.o obj-$(CONFIG_M32R_PCC) += m32r_pcc.o obj-$(CONFIG_M32R_CFC) += m32r_cfc.o -obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o @@ -39,9 +38,6 @@ obj-$(CONFIG_AT91_CF) += at91_cf.o obj-$(CONFIG_ELECTRA_CF) += electra_cf.o obj-$(CONFIG_PCMCIA_ALCHEMY_DEVBOARD) += db1xxx_ss.o -au1x00_ss-y += au1000_generic.o -au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o - sa1111_cs-y += sa1111_generic.o sa1111_cs-$(CONFIG_ASSABET_NEPONSET) += sa1100_neponset.o sa1111_cs-$(CONFIG_SA1100_BADGE4) += sa1100_badge4.o diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c deleted file mode 100644 index 95dd7c62741f..000000000000 --- a/drivers/pcmcia/au1000_generic.c +++ /dev/null @@ -1,545 +0,0 @@ -/* - * - * Alchemy Semi Au1000 pcmcia driver - * - * Copyright 2001-2003 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@embeddedalley.com or source@mvista.com - * - * Copyright 2004 Pete Popov, Embedded Alley Solutions, Inc. - * Updated the driver to 2.6. Followed the sa11xx API and largely - * copied many of the hardware independent functions. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include "au1000_generic.h" - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Pete Popov "); -MODULE_DESCRIPTION("Linux PCMCIA Card Services: Au1x00 Socket Controller"); - -#if 0 -#define debug(x,args...) printk(KERN_DEBUG "%s: " x, __func__ , ##args) -#else -#define debug(x,args...) -#endif - -#define MAP_SIZE 0x100000 -extern struct au1000_pcmcia_socket au1000_pcmcia_socket[]; -#define PCMCIA_SOCKET(x) (au1000_pcmcia_socket + (x)) -#define to_au1000_socket(x) container_of(x, struct au1000_pcmcia_socket, socket) - -/* Some boards like to support CF cards as IDE root devices, so they - * grab pcmcia sockets directly. - */ -u32 *pcmcia_base_vaddrs[2]; -extern const unsigned long mips_io_port_base; - -static DEFINE_MUTEX(pcmcia_sockets_lock); - -static int (*au1x00_pcmcia_hw_init[])(struct device *dev) = { - au1x_board_init, -}; - -static int -au1x00_pcmcia_skt_state(struct au1000_pcmcia_socket *skt) -{ - struct pcmcia_state state; - unsigned int stat; - - memset(&state, 0, sizeof(struct pcmcia_state)); - - skt->ops->socket_state(skt, &state); - - stat = state.detect ? SS_DETECT : 0; - stat |= state.ready ? SS_READY : 0; - stat |= state.wrprot ? SS_WRPROT : 0; - stat |= state.vs_3v ? SS_3VCARD : 0; - stat |= state.vs_Xv ? SS_XVCARD : 0; - stat |= skt->cs_state.Vcc ? SS_POWERON : 0; - - if (skt->cs_state.flags & SS_IOCARD) - stat |= state.bvd1 ? SS_STSCHG : 0; - else { - if (state.bvd1 == 0) - stat |= SS_BATDEAD; - else if (state.bvd2 == 0) - stat |= SS_BATWARN; - } - return stat; -} - -/* - * au100_pcmcia_config_skt - * - * Convert PCMCIA socket state to our socket configure structure. - */ -static int -au1x00_pcmcia_config_skt(struct au1000_pcmcia_socket *skt, socket_state_t *state) -{ - int ret; - - ret = skt->ops->configure_socket(skt, state); - if (ret == 0) { - skt->cs_state = *state; - } - - if (ret < 0) - debug("unable to configure socket %d\n", skt->nr); - - return ret; -} - -/* au1x00_pcmcia_sock_init() - * - * (Re-)Initialise the socket, turning on status interrupts - * and PCMCIA bus. This must wait for power to stabilise - * so that the card status signals report correctly. - * - * Returns: 0 - */ -static int au1x00_pcmcia_sock_init(struct pcmcia_socket *sock) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - - debug("initializing socket %u\n", skt->nr); - - skt->ops->socket_init(skt); - return 0; -} - -/* - * au1x00_pcmcia_suspend() - * - * Remove power on the socket, disable IRQs from the card. - * Turn off status interrupts, and disable the PCMCIA bus. - * - * Returns: 0 - */ -static int au1x00_pcmcia_suspend(struct pcmcia_socket *sock) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - - debug("suspending socket %u\n", skt->nr); - - skt->ops->socket_suspend(skt); - - return 0; -} - -static DEFINE_SPINLOCK(status_lock); - -/* - * au1x00_check_status() - */ -static void au1x00_check_status(struct au1000_pcmcia_socket *skt) -{ - unsigned int events; - - debug("entering PCMCIA monitoring thread\n"); - - do { - unsigned int status; - unsigned long flags; - - status = au1x00_pcmcia_skt_state(skt); - - spin_lock_irqsave(&status_lock, flags); - events = (status ^ skt->status) & skt->cs_state.csc_mask; - skt->status = status; - spin_unlock_irqrestore(&status_lock, flags); - - debug("events: %s%s%s%s%s%s\n", - events == 0 ? "" : "", - events & SS_DETECT ? "DETECT " : "", - events & SS_READY ? "READY " : "", - events & SS_BATDEAD ? "BATDEAD " : "", - events & SS_BATWARN ? "BATWARN " : "", - events & SS_STSCHG ? "STSCHG " : ""); - - if (events) - pcmcia_parse_events(&skt->socket, events); - } while (events); -} - -/* - * au1x00_pcmcia_poll_event() - * Let's poll for events in addition to IRQs since IRQ only is unreliable... - */ -static void au1x00_pcmcia_poll_event(unsigned long dummy) -{ - struct au1000_pcmcia_socket *skt = (struct au1000_pcmcia_socket *)dummy; - debug("polling for events\n"); - - mod_timer(&skt->poll_timer, jiffies + AU1000_PCMCIA_POLL_PERIOD); - - au1x00_check_status(skt); -} - -/* au1x00_pcmcia_get_status() - * - * From the sa11xx_core.c: - * Implements the get_status() operation for the in-kernel PCMCIA - * service (formerly SS_GetStatus in Card Services). Essentially just - * fills in bits in `status' according to internal driver state or - * the value of the voltage detect chipselect register. - * - * As a debugging note, during card startup, the PCMCIA core issues - * three set_socket() commands in a row the first with RESET deasserted, - * the second with RESET asserted, and the last with RESET deasserted - * again. Following the third set_socket(), a get_status() command will - * be issued. The kernel is looking for the SS_READY flag (see - * setup_socket(), reset_socket(), and unreset_socket() in cs.c). - * - * Returns: 0 - */ -static int -au1x00_pcmcia_get_status(struct pcmcia_socket *sock, unsigned int *status) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - - skt->status = au1x00_pcmcia_skt_state(skt); - *status = skt->status; - - return 0; -} - -/* au1x00_pcmcia_set_socket() - * Implements the set_socket() operation for the in-kernel PCMCIA - * service (formerly SS_SetSocket in Card Services). We more or - * less punt all of this work and let the kernel handle the details - * of power configuration, reset, &c. We also record the value of - * `state' in order to regurgitate it to the PCMCIA core later. - * - * Returns: 0 - */ -static int -au1x00_pcmcia_set_socket(struct pcmcia_socket *sock, socket_state_t *state) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - - debug("for sock %u\n", skt->nr); - - debug("\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n", - (state->csc_mask==0)?"":"", - (state->csc_mask&SS_DETECT)?"DETECT ":"", - (state->csc_mask&SS_READY)?"READY ":"", - (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"", - (state->csc_mask&SS_BATWARN)?"BATWARN ":"", - (state->csc_mask&SS_STSCHG)?"STSCHG ":"", - (state->flags==0)?"":"", - (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"", - (state->flags&SS_IOCARD)?"IOCARD ":"", - (state->flags&SS_RESET)?"RESET ":"", - (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"", - (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":""); - debug("\tVcc %d Vpp %d irq %d\n", - state->Vcc, state->Vpp, state->io_irq); - - return au1x00_pcmcia_config_skt(skt, state); -} - -int -au1x00_pcmcia_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *map) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - unsigned int speed; - - if(map->map>=MAX_IO_WIN){ - debug("map (%d) out of range\n", map->map); - return -1; - } - - if(map->flags&MAP_ACTIVE){ - speed=(map->speed>0)?map->speed:AU1000_PCMCIA_IO_SPEED; - skt->spd_io[map->map] = speed; - } - - map->start=(unsigned int)(u32)skt->virt_io; - map->stop=map->start+MAP_SIZE; - return 0; - -} /* au1x00_pcmcia_set_io_map() */ - - -static int -au1x00_pcmcia_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - unsigned short speed = map->speed; - - if(map->map>=MAX_WIN){ - debug("map (%d) out of range\n", map->map); - return -1; - } - - if (map->flags & MAP_ATTRIB) { - skt->spd_attr[map->map] = speed; - skt->spd_mem[map->map] = 0; - } else { - skt->spd_attr[map->map] = 0; - skt->spd_mem[map->map] = speed; - } - - if (map->flags & MAP_ATTRIB) { - map->static_start = skt->phys_attr + map->card_start; - } - else { - map->static_start = skt->phys_mem + map->card_start; - } - - debug("set_mem_map %d start %08lx card_start %08x\n", - map->map, map->static_start, map->card_start); - return 0; - -} /* au1x00_pcmcia_set_mem_map() */ - -static struct pccard_operations au1x00_pcmcia_operations = { - .init = au1x00_pcmcia_sock_init, - .suspend = au1x00_pcmcia_suspend, - .get_status = au1x00_pcmcia_get_status, - .set_socket = au1x00_pcmcia_set_socket, - .set_io_map = au1x00_pcmcia_set_io_map, - .set_mem_map = au1x00_pcmcia_set_mem_map, -}; - -static const char *skt_names[] = { - "PCMCIA socket 0", - "PCMCIA socket 1", -}; - -struct skt_dev_info { - int nskt; -}; - -int au1x00_pcmcia_socket_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr) -{ - struct skt_dev_info *sinfo; - struct au1000_pcmcia_socket *skt; - int ret, i; - - sinfo = kzalloc(sizeof(struct skt_dev_info), GFP_KERNEL); - if (!sinfo) { - ret = -ENOMEM; - goto out; - } - - sinfo->nskt = nr; - - /* - * Initialise the per-socket structure. - */ - for (i = 0; i < nr; i++) { - skt = PCMCIA_SOCKET(i); - memset(skt, 0, sizeof(*skt)); - - skt->socket.resource_ops = &pccard_static_ops; - skt->socket.ops = &au1x00_pcmcia_operations; - skt->socket.owner = ops->owner; - skt->socket.dev.parent = dev; - - init_timer(&skt->poll_timer); - skt->poll_timer.function = au1x00_pcmcia_poll_event; - skt->poll_timer.data = (unsigned long)skt; - skt->poll_timer.expires = jiffies + AU1000_PCMCIA_POLL_PERIOD; - - skt->nr = first + i; - skt->irq = 255; - skt->dev = dev; - skt->ops = ops; - - skt->res_skt.name = skt_names[skt->nr]; - skt->res_io.name = "io"; - skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; - skt->res_mem.name = "memory"; - skt->res_mem.flags = IORESOURCE_MEM; - skt->res_attr.name = "attribute"; - skt->res_attr.flags = IORESOURCE_MEM; - - /* - * PCMCIA client drivers use the inb/outb macros to access the - * IO registers. Since mips_io_port_base is added to the - * access address of the mips implementation of inb/outb, - * we need to subtract it here because we want to access the - * I/O or MEM address directly, without going through this - * "mips_io_port_base" mechanism. - */ - if (i == 0) { - skt->virt_io = (void *) - (ioremap((phys_t)AU1X_SOCK0_IO, 0x1000) - - (u32)mips_io_port_base); - skt->phys_attr = AU1X_SOCK0_PHYS_ATTR; - skt->phys_mem = AU1X_SOCK0_PHYS_MEM; - } - else { - skt->virt_io = (void *) - (ioremap((phys_t)AU1X_SOCK1_IO, 0x1000) - - (u32)mips_io_port_base); - skt->phys_attr = AU1X_SOCK1_PHYS_ATTR; - skt->phys_mem = AU1X_SOCK1_PHYS_MEM; - } - pcmcia_base_vaddrs[i] = (u32 *)skt->virt_io; - ret = ops->hw_init(skt); - - skt->socket.features = SS_CAP_STATIC_MAP|SS_CAP_PCCARD; - skt->socket.irq_mask = 0; - skt->socket.map_size = MAP_SIZE; - skt->socket.pci_irq = skt->irq; - skt->socket.io_offset = (unsigned long)skt->virt_io; - - skt->status = au1x00_pcmcia_skt_state(skt); - - ret = pcmcia_register_socket(&skt->socket); - if (ret) - goto out_err; - - WARN_ON(skt->socket.sock != i); - - add_timer(&skt->poll_timer); - } - - dev_set_drvdata(dev, sinfo); - return 0; - - -out_err: - ops->hw_shutdown(skt); - while (i-- > 0) { - skt = PCMCIA_SOCKET(i); - - del_timer_sync(&skt->poll_timer); - pcmcia_unregister_socket(&skt->socket); - if (i == 0) { - iounmap(skt->virt_io + (u32)mips_io_port_base); - skt->virt_io = NULL; - } -#ifndef CONFIG_MIPS_XXS1500 - else { - iounmap(skt->virt_io + (u32)mips_io_port_base); - skt->virt_io = NULL; - } -#endif - ops->hw_shutdown(skt); - - } - kfree(sinfo); -out: - return ret; -} - -int au1x00_drv_pcmcia_remove(struct platform_device *dev) -{ - struct skt_dev_info *sinfo = platform_get_drvdata(dev); - int i; - - mutex_lock(&pcmcia_sockets_lock); - platform_set_drvdata(dev, NULL); - - for (i = 0; i < sinfo->nskt; i++) { - struct au1000_pcmcia_socket *skt = PCMCIA_SOCKET(i); - - del_timer_sync(&skt->poll_timer); - pcmcia_unregister_socket(&skt->socket); - skt->ops->hw_shutdown(skt); - au1x00_pcmcia_config_skt(skt, &dead_socket); - iounmap(skt->virt_io + (u32)mips_io_port_base); - skt->virt_io = NULL; - } - - kfree(sinfo); - mutex_unlock(&pcmcia_sockets_lock); - return 0; -} - - -/* - * PCMCIA "Driver" API - */ - -static int au1x00_drv_pcmcia_probe(struct platform_device *dev) -{ - int i, ret = -ENODEV; - - mutex_lock(&pcmcia_sockets_lock); - for (i=0; i < ARRAY_SIZE(au1x00_pcmcia_hw_init); i++) { - ret = au1x00_pcmcia_hw_init[i](&dev->dev); - if (ret == 0) - break; - } - mutex_unlock(&pcmcia_sockets_lock); - return ret; -} - -static struct platform_driver au1x00_pcmcia_driver = { - .driver = { - .name = "au1x00-pcmcia", - .owner = THIS_MODULE, - }, - .probe = au1x00_drv_pcmcia_probe, - .remove = au1x00_drv_pcmcia_remove, -}; - - -/* au1x00_pcmcia_init() - * - * This routine performs low-level PCMCIA initialization and then - * registers this socket driver with Card Services. - * - * Returns: 0 on success, -ve error code on failure - */ -static int __init au1x00_pcmcia_init(void) -{ - int error = 0; - error = platform_driver_register(&au1x00_pcmcia_driver); - return error; -} - -/* au1x00_pcmcia_exit() - * Invokes the low-level kernel service to free IRQs associated with this - * socket controller and reset GPIO edge detection. - */ -static void __exit au1x00_pcmcia_exit(void) -{ - platform_driver_unregister(&au1x00_pcmcia_driver); -} - -module_init(au1x00_pcmcia_init); -module_exit(au1x00_pcmcia_exit); diff --git a/drivers/pcmcia/au1000_generic.h b/drivers/pcmcia/au1000_generic.h deleted file mode 100644 index 5c36bda2963b..000000000000 --- a/drivers/pcmcia/au1000_generic.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Alchemy Semi Au1000 pcmcia driver include file - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef __ASM_AU1000_PCMCIA_H -#define __ASM_AU1000_PCMCIA_H - -/* include the world */ - -#include -#include -#include "cs_internal.h" - -#define AU1000_PCMCIA_POLL_PERIOD (2*HZ) -#define AU1000_PCMCIA_IO_SPEED (255) -#define AU1000_PCMCIA_MEM_SPEED (300) - -#define AU1X_SOCK0_IO 0xF00000000ULL -#define AU1X_SOCK0_PHYS_ATTR 0xF40000000ULL -#define AU1X_SOCK0_PHYS_MEM 0xF80000000ULL - -/* pcmcia socket 1 needs external glue logic so the memory map - * differs from board to board. - */ -#if defined(CONFIG_MIPS_PB1000) -#define AU1X_SOCK1_IO 0xF08000000ULL -#define AU1X_SOCK1_PHYS_ATTR 0xF48000000ULL -#define AU1X_SOCK1_PHYS_MEM 0xF88000000ULL -#endif - -struct pcmcia_state { - unsigned detect: 1, - ready: 1, - wrprot: 1, - bvd1: 1, - bvd2: 1, - vs_3v: 1, - vs_Xv: 1; -}; - -struct pcmcia_configure { - unsigned sock: 8, - vcc: 8, - vpp: 8, - output: 1, - speaker: 1, - reset: 1; -}; - -struct pcmcia_irqs { - int sock; - int irq; - const char *str; -}; - - -struct au1000_pcmcia_socket { - struct pcmcia_socket socket; - - /* - * Info from low level handler - */ - struct device *dev; - unsigned int nr; - unsigned int irq; - - /* - * Core PCMCIA state - */ - struct pcmcia_low_level *ops; - - unsigned int status; - socket_state_t cs_state; - - unsigned short spd_io[MAX_IO_WIN]; - unsigned short spd_mem[MAX_WIN]; - unsigned short spd_attr[MAX_WIN]; - - struct resource res_skt; - struct resource res_io; - struct resource res_mem; - struct resource res_attr; - - void * virt_io; - unsigned int phys_io; - unsigned int phys_attr; - unsigned int phys_mem; - unsigned short speed_io, speed_attr, speed_mem; - - unsigned int irq_state; - - struct timer_list poll_timer; -}; - -struct pcmcia_low_level { - struct module *owner; - - int (*hw_init)(struct au1000_pcmcia_socket *); - void (*hw_shutdown)(struct au1000_pcmcia_socket *); - - void (*socket_state)(struct au1000_pcmcia_socket *, struct pcmcia_state *); - int (*configure_socket)(struct au1000_pcmcia_socket *, struct socket_state_t *); - - /* - * Enable card status IRQs on (re-)initialisation. This can - * be called at initialisation, power management event, or - * pcmcia event. - */ - void (*socket_init)(struct au1000_pcmcia_socket *); - - /* - * Disable card status IRQs and PCMCIA bus on suspend. - */ - void (*socket_suspend)(struct au1000_pcmcia_socket *); -}; - -extern int au1x_board_init(struct device *dev); - -#endif /* __ASM_AU1000_PCMCIA_H */ diff --git a/drivers/pcmcia/au1000_pb1x00.c b/drivers/pcmcia/au1000_pb1x00.c deleted file mode 100644 index b2396647a165..000000000000 --- a/drivers/pcmcia/au1000_pb1x00.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * - * Alchemy Semi Pb1000 boards specific pcmcia routines. - * - * Copyright 2002 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include - -#define debug(fmt, arg...) do { } while (0) - -#include -#define PCMCIA_IRQ AU1000_GPIO_15 - -static int pb1x00_pcmcia_init(struct pcmcia_init *init) -{ - u16 pcr; - pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST; - - au_writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */ - au_sync_delay(100); - au_writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */ - au_sync(); - - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0); - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1); - au_writel(pcr, PB1000_PCR); - au_sync_delay(20); - - return PCMCIA_NUM_SOCKS; -} - -static int pb1x00_pcmcia_shutdown(void) -{ - u16 pcr; - pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST; - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0); - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1); - au_writel(pcr, PB1000_PCR); - au_sync_delay(20); - return 0; -} - -static int -pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state) -{ - u32 inserted0, inserted1; - u16 vs0, vs1; - - vs0 = vs1 = (u16)au_readl(PB1000_ACR1); - inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2)); - inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2)); - vs0 = (vs0 >> 4) & 0x3; - vs1 = (vs1 >> 12) & 0x3; - - state->ready = 0; - state->vs_Xv = 0; - state->vs_3v = 0; - state->detect = 0; - - if (sock == 0) { - if (inserted0) { - switch (vs0) { - case 0: - case 2: - state->vs_3v=1; - break; - case 3: /* 5V */ - break; - default: - /* return without setting 'detect' */ - printk(KERN_ERR "pb1x00 bad VS (%d)\n", - vs0); - return 0; - } - state->detect = 1; - } - } - else { - if (inserted1) { - switch (vs1) { - case 0: - case 2: - state->vs_3v=1; - break; - case 3: /* 5V */ - break; - default: - /* return without setting 'detect' */ - printk(KERN_ERR "pb1x00 bad VS (%d)\n", - vs1); - return 0; - } - state->detect = 1; - } - } - - if (state->detect) { - state->ready = 1; - } - - state->bvd1=1; - state->bvd2=1; - state->wrprot=0; - return 1; -} - - -static int pb1x00_pcmcia_get_irq_info(struct pcmcia_irq_info *info) -{ - - if(info->sock > PCMCIA_MAX_SOCK) return -1; - - /* - * Even in the case of the Pb1000, both sockets are connected - * to the same irq line. - */ - info->irq = PCMCIA_IRQ; - - return 0; -} - - -static int -pb1x00_pcmcia_configure_socket(const struct pcmcia_configure *configure) -{ - u16 pcr; - - if(configure->sock > PCMCIA_MAX_SOCK) return -1; - - pcr = au_readl(PB1000_PCR); - - if (configure->sock == 0) { - pcr &= ~(PCR_SLOT_0_VCC0 | PCR_SLOT_0_VCC1 | - PCR_SLOT_0_VPP0 | PCR_SLOT_0_VPP1); - } - else { - pcr &= ~(PCR_SLOT_1_VCC0 | PCR_SLOT_1_VCC1 | - PCR_SLOT_1_VPP0 | PCR_SLOT_1_VPP1); - } - - pcr &= ~PCR_SLOT_0_RST; - debug("Vcc %dV Vpp %dV, pcr %x\n", - configure->vcc, configure->vpp, pcr); - switch(configure->vcc){ - case 0: /* Vcc 0 */ - switch(configure->vpp) { - case 0: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_GND, - configure->sock); - break; - case 12: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_12V, - configure->sock); - break; - case 50: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_5V, - configure->sock); - break; - case 33: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_3V, - configure->sock); - break; - default: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, - configure->sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __func__, - configure->vcc, - configure->vpp); - break; - } - break; - case 50: /* Vcc 5V */ - switch(configure->vpp) { - case 0: - pcr |= SET_VCC_VPP(VCC_5V,VPP_GND, - configure->sock); - break; - case 50: - pcr |= SET_VCC_VPP(VCC_5V,VPP_5V, - configure->sock); - break; - case 12: - pcr |= SET_VCC_VPP(VCC_5V,VPP_12V, - configure->sock); - break; - case 33: - pcr |= SET_VCC_VPP(VCC_5V,VPP_3V, - configure->sock); - break; - default: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, - configure->sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __func__, - configure->vcc, - configure->vpp); - break; - } - break; - case 33: /* Vcc 3.3V */ - switch(configure->vpp) { - case 0: - pcr |= SET_VCC_VPP(VCC_3V,VPP_GND, - configure->sock); - break; - case 50: - pcr |= SET_VCC_VPP(VCC_3V,VPP_5V, - configure->sock); - break; - case 12: - pcr |= SET_VCC_VPP(VCC_3V,VPP_12V, - configure->sock); - break; - case 33: - pcr |= SET_VCC_VPP(VCC_3V,VPP_3V, - configure->sock); - break; - default: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, - configure->sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __func__, - configure->vcc, - configure->vpp); - break; - } - break; - default: /* what's this ? */ - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,configure->sock); - printk(KERN_ERR "%s: bad Vcc %d\n", - __func__, configure->vcc); - break; - } - - if (configure->sock == 0) { - pcr &= ~(PCR_SLOT_0_RST); - if (configure->reset) - pcr |= PCR_SLOT_0_RST; - } - else { - pcr &= ~(PCR_SLOT_1_RST); - if (configure->reset) - pcr |= PCR_SLOT_1_RST; - } - au_writel(pcr, PB1000_PCR); - au_sync_delay(300); - - return 0; -} - - -struct pcmcia_low_level pb1x00_pcmcia_ops = { - pb1x00_pcmcia_init, - pb1x00_pcmcia_shutdown, - pb1x00_pcmcia_socket_state, - pb1x00_pcmcia_get_irq_info, - pb1x00_pcmcia_configure_socket -}; From 435037c630dcd984cf95c9cfff973f8626cea368 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Tue, 1 Nov 2011 20:03:28 +0100 Subject: [PATCH 005/119] MIPS: Alchemy: Drop MIRAGE/BOSPORUS board support No test hardware and no (apparent) users. These boards seem very similar to the DB1500, so if required support can be brought back again (I have datasheets) but then with dedicated board code, not tacked on to DB1000 support. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2864/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 14 --- arch/mips/alchemy/Platform | 14 --- arch/mips/alchemy/devboards/Makefile | 2 - .../alchemy/devboards/db1x00/board_setup.c | 105 +----------------- arch/mips/alchemy/devboards/db1x00/platform.c | 68 +----------- arch/mips/alchemy/devboards/prom.c | 3 +- 6 files changed, 3 insertions(+), 203 deletions(-) diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 5a48387d0751..36df5e2c8e07 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -22,13 +22,6 @@ config MIPS_MTX1 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_BOSPORUS - bool "Alchemy Bosporus board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_DB1000 bool "Alchemy DB1000 board" select ALCHEMY_GPIOINT_AU1000 @@ -71,13 +64,6 @@ config MIPS_DB1550 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_MIRAGE - bool "Alchemy Mirage board" - select DMA_NONCOHERENT - select ALCHEMY_GPIOINT_AU1000 - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_PB1100 bool "Alchemy PB1100 board" select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 4e079672f9bf..2920af9c2569 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -67,20 +67,6 @@ platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 -# -# AMD Alchemy Bosporus eval board -# -platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000 - -# -# AMD Alchemy Mirage eval board -# -platform-$(CONFIG_MIPS_MIRAGE) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 - # # 4G-Systems eval board # diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index bea80d787781..5afaf944868f 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -13,5 +13,3 @@ obj-$(CONFIG_MIPS_DB1100) += db1x00/ obj-$(CONFIG_MIPS_DB1200) += db1200/ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ -obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ -obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 7cd36e631f6c..8a222b3eba32 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -40,64 +40,10 @@ #include -#ifdef CONFIG_MIPS_BOSPORUS -char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ - [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ -}; - -/* - * Micrel/Kendin 5 port switch attached to MAC0, - * MAC0 is associated with PHY address 5 (== WAN port) - * MAC1 is not associated with any PHY, since it's connected directly - * to the switch. - * no interrupts are used - */ -static struct au1000_eth_platform_data eth0_pdata = { - .phy_static_config = 1, - .phy_addr = 5, -}; - -static void bosporus_power_off(void) -{ - while (1) - asm volatile (".set mips3 ; wait ; .set mips0"); -} - -const char *get_system_type(void) -{ - return "Alchemy Bosporus Gateway Reference"; -} -#endif - - -#ifdef CONFIG_MIPS_MIRAGE -static void mirage_power_off(void) -{ - alchemy_gpio_direction_output(210, 1); -} - -const char *get_system_type(void) -{ - return "Alchemy Mirage"; -} -#endif - - -#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) -static void mips_softreset(void) -{ - asm volatile ("jr\t%0" : : "r"(0xbfc00000)); -} - -#else - const char *get_system_type(void) { return "Alchemy Db1x00"; } -#endif void __init board_setup(void) @@ -116,14 +62,6 @@ void __init board_setup(void) #ifdef CONFIG_MIPS_DB1100 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); #endif -#ifdef CONFIG_MIPS_BOSPORUS - au1xxx_override_eth_cfg(0, ð0_pdata); - - printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); -#endif -#ifdef CONFIG_MIPS_MIRAGE - printk(KERN_INFO "AMD Alchemy Mirage Board\n"); -#endif #ifdef CONFIG_MIPS_DB1550 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); @@ -150,52 +88,11 @@ void __init board_setup(void) /* Enable GPIO[31:0] inputs */ alchemy_gpio1_input_enable(); - -#ifdef CONFIG_MIPS_MIRAGE - { - u32 pin_func; - - /* GPIO[20] is output */ - alchemy_gpio_direction_output(20, 0); - - /* Set GPIO[210:208] instead of SSI_0 */ - pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; - - /* Set GPIO[215:211] for LEDs */ - pin_func |= 5 << 2; - - /* Set GPIO[214:213] for more LEDs */ - pin_func |= 5 << 12; - - /* Set GPIO[207:200] instead of PCMCIA/LCD */ - pin_func |= SYS_PF_LCD | SYS_PF_PC; - au_writel(pin_func, SYS_PINFUNC); - - /* - * Enable speaker amplifier. This should - * be part of the audio driver. - */ - alchemy_gpio_direction_output(209, 1); - - pm_power_off = mirage_power_off; - _machine_halt = mirage_power_off; - _machine_restart = (void(*)(char *))mips_softreset; - } -#endif - -#ifdef CONFIG_MIPS_BOSPORUS - pm_power_off = bosporus_power_off; - _machine_halt = bosporus_power_off; - _machine_restart = (void(*)(char *))mips_softreset; -#endif - au_sync(); } static int __init db1x00_init_irq(void) { -#if defined(CONFIG_MIPS_MIRAGE) - irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ -#elif defined(CONFIG_MIPS_DB1550) +#if defined(CONFIG_MIPS_DB1550) irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 9e6b3d442acd..677414d5f5b4 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -37,7 +37,6 @@ struct pci_dev; * Db1550: 0/1, 21/22, 3/5 */ -#define DB1XXX_HAS_PCMCIA #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) #if defined(CONFIG_MIPS_DB1000) @@ -48,7 +47,6 @@ struct pci_dev; #define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ #elif defined(CONFIG_MIPS_DB1100) #define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT #define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT @@ -57,7 +55,6 @@ struct pci_dev; #define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ #elif defined(CONFIG_MIPS_DB1500) #define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT #define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT @@ -66,7 +63,6 @@ struct pci_dev; #define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ #elif defined(CONFIG_MIPS_DB1550) #define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT #define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT @@ -75,19 +71,6 @@ struct pci_dev; #define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT #define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT #define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#else -/* other board: no PCMCIA */ -#undef DB1XXX_HAS_PCMCIA -#undef F_SWAPPED -#define F_SWAPPED 0 -#if defined(CONFIG_MIPS_BOSPORUS) -#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */ -#define BOARD_FLASH_WIDTH 2 /* 16-bits */ -#elif defined(CONFIG_MIPS_MIRAGE) -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif #endif #ifdef CONFIG_PCI @@ -137,52 +120,6 @@ static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) } #endif -#ifdef CONFIG_MIPS_BOSPORUS -static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 11) || (slot > 13) || pin == 0) - return -1; - if (slot == 12) - return (pin == 1) ? AU1500_PCI_INTA : 0xff; - if (slot == 11) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - default: return 0xff; - } - } - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - case 3: return AU1500_PCI_INTC; - case 4: return AU1500_PCI_INTD; - } - } - return -1; -} -#endif - -#ifdef CONFIG_MIPS_MIRAGE -static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 11) || (slot > 13) || pin == 0) - return -1; - if (slot == 11) - return (pin == 1) ? AU1500_PCI_INTD : 0xff; - if (slot == 12) - return (pin == 3) ? AU1500_PCI_INTC : 0xff; - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - default: return 0xff; - } - } - return -1; -} -#endif - static struct resource alchemy_pci_host_res[] = { [0] = { .start = AU1500_PCI_PHYS_ADDR, @@ -280,7 +217,6 @@ static struct platform_device db1x00_audio_dev = { static int __init db1xxx_dev_init(void) { -#ifdef DB1XXX_HAS_PCMCIA db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, @@ -300,17 +236,15 @@ static int __init db1xxx_dev_init(void) AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); -#endif #ifdef CONFIG_MIPS_DB1100 platform_device_register(&au1100_lcd_device); #endif - db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); - platform_device_register(&db1x00_codec_dev); platform_device_register(&alchemy_ac97c_dma_dev); platform_device_register(&alchemy_ac97c_dev); platform_device_register(&db1x00_audio_dev); + db1x_register_norflash(BOARD_FLASH_SIZE, 4 /* 32bit */, F_SWAPPED); return 0; } device_initcall(db1xxx_dev_init); diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index 56d7ea52fd97..f734833fbdda 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -35,8 +35,7 @@ #if defined(CONFIG_MIPS_DB1000) || \ defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ - defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) + defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) #define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 #else /* Au1550/Au1200-based develboards */ From fb469f084fdf1631e31d87270f5263c20a7f5cd6 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Tue, 1 Nov 2011 20:03:29 +0100 Subject: [PATCH 006/119] MIPS: Alchemy: devboards: remove unneeded BCSR IRQ reg acc Initially I had to write to both the MASK and ENABLE registers, otherwise the CPLD would generate tons of spurious interrupts. With the change to the demux handler to disable the muxed line, it is now sufficient to disable the interrupt by writing either the enable or mask register. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2865/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/bcsr.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index 463d2c4d9441..1e83ce2e1147 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -97,14 +97,9 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) enable_irq(irq); } -/* NOTE: both the enable and mask bits must be cleared, otherwise the - * CPLD generates tons of spurious interrupts (at least on my DB1200). - * -- mlau - */ static void bcsr_irq_mask(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); wmb(); } @@ -112,7 +107,6 @@ static void bcsr_irq_mask(struct irq_data *d) static void bcsr_irq_maskack(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ wmb(); @@ -121,7 +115,6 @@ static void bcsr_irq_maskack(struct irq_data *d) static void bcsr_irq_unmask(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTSET); __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); wmb(); } @@ -137,9 +130,9 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) { unsigned int irq; - /* mask & disable & ack all */ - __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR); + /* mask & enable & ack all */ __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); + __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET); __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); wmb(); From 809f36c6f4a0568178c909ff1096ca83eae33f7d Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Tue, 1 Nov 2011 20:03:30 +0100 Subject: [PATCH 007/119] MIPS: Alchemy: Au1300 SoC support Add basic support for the Au1300 variant(s): - New GPIO/Interrupt controller - DBDMA ids - USB setup - MMC support - enable various PSC drivers - detection code. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2866/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 4 + arch/mips/alchemy/common/Makefile | 3 +- arch/mips/alchemy/common/dbdma.c | 46 ++ arch/mips/alchemy/common/gpioint.c | 411 ++++++++++++++++++ arch/mips/alchemy/common/gpiolib.c | 42 ++ arch/mips/alchemy/common/platform.c | 31 +- arch/mips/alchemy/common/power.c | 3 + arch/mips/alchemy/common/sleeper.S | 73 ++++ arch/mips/alchemy/common/time.c | 1 + arch/mips/alchemy/common/vss.c | 84 ++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/include/asm/mach-au1x00/au1000.h | 221 +++++++++- .../mips/include/asm/mach-au1x00/au1100_mmc.h | 2 + .../include/asm/mach-au1x00/au1xxx_dbdma.h | 31 ++ .../include/asm/mach-au1x00/gpio-au1300.h | 241 ++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 3 + arch/mips/kernel/cpu-probe.c | 7 + drivers/i2c/busses/Kconfig | 4 +- drivers/mmc/host/au1xmmc.c | 53 ++- drivers/spi/Kconfig | 4 +- drivers/usb/host/alchemy-common.c | 277 ++++++++++++ drivers/usb/host/ohci-au1xxx.c | 13 +- drivers/video/Kconfig | 8 +- sound/soc/au1x/Kconfig | 6 +- 24 files changed, 1518 insertions(+), 51 deletions(-) create mode 100644 arch/mips/alchemy/common/gpioint.c create mode 100644 arch/mips/alchemy/common/vss.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1300.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 36df5e2c8e07..766badaef3b0 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -2,6 +2,10 @@ config ALCHEMY_GPIOINT_AU1000 bool +# au1300-style GPIO/INT controller +config ALCHEMY_GPIOINT_AU1300 + bool + # select this in your board config if you don't want to use the gpio # namespace as documented in the manuals. In this case however you need # to create the necessary gpio_* functions in your board code/headers! diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 811ece7b22e3..d3f5c5137804 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -6,9 +6,10 @@ # obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o + sleeper.o dma.o dbdma.o vss.o obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o +obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpioint.o # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 0e63ee487d6d..c723ec1d3b2c 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -148,6 +148,50 @@ static dbdev_tab_t au1200_dbdev_tab[] __initdata = { { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, }; +static dbdev_tab_t au1300_dbdev_tab[] __initdata = { + { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 }, + { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 }, + { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 }, + { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, +}; + /* 32 predefined plus 32 custom */ #define DBDEV_TAB_SIZE 64 @@ -1038,6 +1082,8 @@ static int __init alchemy_dbdma_init(void) return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab); case ALCHEMY_CPU_AU1200: return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab); + case ALCHEMY_CPU_AU1300: + return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab); } return 0; } diff --git a/arch/mips/alchemy/common/gpioint.c b/arch/mips/alchemy/common/gpioint.c new file mode 100644 index 000000000000..b8cd3364ff69 --- /dev/null +++ b/arch/mips/alchemy/common/gpioint.c @@ -0,0 +1,411 @@ +/* + * gpioint.c - Au1300 GPIO+Interrupt controller (I call it "GPIC") support. + * + * Copyright (c) 2009-2011 Manuel Lauss + * + * licensed under the GPLv2. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static int au1300_gpic_settype(struct irq_data *d, unsigned int type); + +/* setup for known onchip sources */ +struct gpic_devint_data { + int irq; /* linux IRQ number */ + int type; /* IRQ_TYPE_ */ + int prio; /* irq priority, 0 highest, 3 lowest */ + int internal; /* internal source (no ext. pin)? */ +}; + +static const struct gpic_devint_data au1300_devints[] __initdata = { + /* multifunction: gpio pin or device */ + { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + /* au1300 internal */ + { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, }, + { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { -1, }, /* terminator */ +}; + + +/* + * au1300_gpic_chgcfg - change PIN configuration. + * @gpio: pin to change (0-based GPIO number from datasheet). + * @clr: clear all bits set in 'clr'. + * @set: set these bits. + * + * modifies a pins' configuration register, bits set in @clr will + * be cleared in the register, bits in @set will be set. + */ +static inline void au1300_gpic_chgcfg(unsigned int gpio, + unsigned long clr, + unsigned long set) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long l; + + r += gpio * 4; /* offset into pin config array */ + l = __raw_readl(r + AU1300_GPIC_PINCFG); + l &= ~clr; + l |= set; + __raw_writel(l, r + AU1300_GPIC_PINCFG); + wmb(); +} + +/* + * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl). + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to the GPIO controller, so its level can either + * be read or set through the generic GPIO functions. + * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1). + * REVISIT: is this function really necessary? + */ +void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio) +{ + au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio); + +/* + * au1300_pinfunc_to_dev - assign a pin to the device function. + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to its associated device function; the pin will be + * driven by the device and not through GPIO functions. + */ +void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + r += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, r + AU1300_GPIC_DEVSEL); + wmb(); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev); + +/* + * au1300_set_irq_priority - set internal priority of IRQ. + * @irq: irq to set priority (linux irq number). + * @p: priority (0 = highest, 3 = lowest). + */ +void au1300_set_irq_priority(unsigned int irq, int p) +{ + irq -= ALCHEMY_GPIC_INT_BASE; + au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p)); +} +EXPORT_SYMBOL_GPL(au1300_set_irq_priority); + +/* + * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers. + * @dchan: dbdma trigger select (0, 1). + * @gpio: pin to assign as trigger. + * + * DBDMA controller has 2 external trigger sources; this function + * assigns a GPIO to the selected trigger. + */ +void au1300_set_dbdma_gpio(int dchan, unsigned int gpio) +{ + unsigned long r; + + if ((dchan >= 0) && (dchan <= 1)) { + r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + r &= ~(0xff << (8 * dchan)); + r |= (gpio & 0x7f) << (8 * dchan); + __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + wmb(); + } +} + +/**********************************************************************/ + +static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow) +{ + au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE, + allow ? GPIC_CFG_IDLEWAKE : 0); +} + +static void au1300_gpic_mask(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IDIS); + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_unmask(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + + gpic_pin_set_idlewake(irq, 1); + + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IEN); + wmb(); +} + +static void au1300_gpic_maskack(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */ + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_ack(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + wmb(); +} + +static struct irq_chip au1300_gpic = { + .name = "GPIOINT", + .irq_ack = au1300_gpic_ack, + .irq_mask = au1300_gpic_mask, + .irq_mask_ack = au1300_gpic_maskack, + .irq_unmask = au1300_gpic_unmask, + .irq_set_type = au1300_gpic_settype, +}; + +static int au1300_gpic_settype(struct irq_data *d, unsigned int type) +{ + unsigned long s; + unsigned char *name = NULL; + irq_flow_handler_t hdl = NULL; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + s = GPIC_CFG_IC_LEVEL_HIGH; + name = "high"; + hdl = handle_level_irq; + break; + case IRQ_TYPE_LEVEL_LOW: + s = GPIC_CFG_IC_LEVEL_LOW; + name = "low"; + hdl = handle_level_irq; + break; + case IRQ_TYPE_EDGE_RISING: + s = GPIC_CFG_IC_EDGE_RISE; + name = "posedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_EDGE_FALLING: + s = GPIC_CFG_IC_EDGE_FALL; + name = "negedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_EDGE_BOTH: + s = GPIC_CFG_IC_EDGE_BOTH; + name = "bothedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_NONE: + s = GPIC_CFG_IC_OFF; + name = "disabled"; + hdl = handle_level_irq; + break; + default: + return -EINVAL; + } + + __irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name); + + au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s); + + return 0; +} + +static void __init alchemy_gpic_init_irq(const struct gpic_devint_data *dints) +{ + int i; + void __iomem *bank_base; + + mips_cpu_irq_init(); + + /* disable & ack all possible interrupt sources */ + for (i = 0; i < 4; i++) { + bank_base = AU1300_GPIC_ADDR + (i * 4); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS); + wmb(); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND); + wmb(); + } + + /* register an irq_chip for them, with 2nd highest priority */ + for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) { + au1300_set_irq_priority(i, 1); + au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); + } + + /* setup known on-chip sources */ + while ((i = dints->irq) != -1) { + au1300_gpic_settype(irq_get_irq_data(i), dints->type); + au1300_set_irq_priority(i, dints->prio); + + if (dints->internal) + au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE); + + dints++; + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); +} + +static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6]; + +static int alchemy_gpic_suspend(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; + + /* save 4 interrupt mask status registers */ + alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0); + alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4); + alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8); + alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc); + + /* save misc register(s) */ + alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL); + + /* molto silenzioso */ + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); + wmb(); + + /* save pin/int-type configuration */ + base += AU1300_GPIC_PINCFG; + for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++) + alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2)); + + wmb(); + + return 0; +} + +static void alchemy_gpic_resume(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; + + /* disable all first */ + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); + wmb(); + + /* restore pin/int-type configurations */ + base += AU1300_GPIC_PINCFG; + for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++) + __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2)); + wmb(); + + /* restore misc register(s) */ + base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL); + wmb(); + + /* finally restore masks */ + __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0); + __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4); + __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8); + __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc); + wmb(); +} + +static struct syscore_ops alchemy_gpic_pmops = { + .suspend = alchemy_gpic_suspend, + .resume = alchemy_gpic_resume, +}; + +/**********************************************************************/ + +void __init arch_init_irq(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + alchemy_gpic_init_irq(&au1300_devints[0]); + register_syscore_ops(&alchemy_gpic_pmops); + break; + } +} + +#define CAUSEF_GPIC (CAUSEF_IP2 | CAUSEF_IP3 | CAUSEF_IP4 | CAUSEF_IP5) + +void plat_irq_dispatch(void) +{ + unsigned long i, c = read_c0_cause() & read_c0_status(); + + if (c & CAUSEF_IP7) /* c0 timer */ + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (likely(c & CAUSEF_GPIC)) { + i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC); + do_IRQ(i + ALCHEMY_GPIC_INT_BASE); + } else + spurious_interrupt(); +} diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c index 91fb4d9e30fd..f1b50f0c01db 100644 --- a/arch/mips/alchemy/common/gpiolib.c +++ b/arch/mips/alchemy/common/gpiolib.c @@ -27,6 +27,7 @@ * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! * au1000 SoC have only one GPIO block : GPIO1 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 + * Au1300 is totally different: 1 block with up to 128 GPIOs */ #include @@ -35,6 +36,7 @@ #include #include #include +#include static int gpio2_get(struct gpio_chip *chip, unsigned offset) { @@ -115,6 +117,43 @@ struct gpio_chip alchemy_gpio_chip[] = { }, }; +static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_get_value(off + AU1300_GPIO_BASE); +} + +static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v) +{ + au1300_gpio_set_value(off + AU1300_GPIO_BASE, v); +} + +static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_direction_input(off + AU1300_GPIO_BASE); +} + +static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off, + int v) +{ + return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v); +} + +static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_to_irq(off + AU1300_GPIO_BASE); +} + +static struct gpio_chip au1300_gpiochip = { + .label = "alchemy-gpic", + .direction_input = alchemy_gpic_dir_input, + .direction_output = alchemy_gpic_dir_output, + .get = alchemy_gpic_get, + .set = alchemy_gpic_set, + .to_irq = alchemy_gpic_gpio_to_irq, + .base = AU1300_GPIO_BASE, + .ngpio = AU1300_GPIO_NUM, +}; + static int __init alchemy_gpiochip_init(void) { int ret = 0; @@ -127,6 +166,9 @@ static int __init alchemy_gpiochip_init(void) ret = gpiochip_add(&alchemy_gpio_chip[0]); ret |= gpiochip_add(&alchemy_gpio_chip[1]); break; + case ALCHEMY_CPU_AU1300: + ret = gpiochip_add(&au1300_gpiochip); + break; } return ret; } diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index c8e5d72a5826..95cb9113b12c 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -82,6 +82,12 @@ static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = { PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), }, + [ALCHEMY_CPU_AU1300] = { + PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT), + PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT), + PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT), + PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT), + }, }; static struct platform_device au1xx0_uart_device = { @@ -122,10 +128,12 @@ static unsigned long alchemy_ohci_data[][2] __initdata = { [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, + [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT }, }; static unsigned long alchemy_ehci_data[][2] __initdata = { [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, + [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT }, }; static int __init _new_usbres(struct resource **r, struct platform_device **d) @@ -169,8 +177,8 @@ static void __init alchemy_setup_usb(int ctype) printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); - /* setup EHCI0: Au1200 */ - if (ctype == ALCHEMY_CPU_AU1200) { + /* setup EHCI0: Au1200/Au1300 */ + if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) { if (_new_usbres(&res, &pdev)) return; @@ -187,6 +195,25 @@ static void __init alchemy_setup_usb(int ctype) if (platform_device_register(pdev)) printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); } + + /* Au1300: OHCI1 */ + if (ctype == ALCHEMY_CPU_AU1300) { + if (_new_usbres(&res, &pdev)) + return; + + res[0].start = AU1300_USB_OHCI1_PHYS_ADDR; + res[0].end = res[0].start + 0x100 - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = AU1300_USB_INT; + res[1].end = res[1].start; + res[1].flags = IORESOURCE_IRQ; + pdev->name = "au1xxx-ohci"; + pdev->id = 1; + pdev->dev.dma_mask = &alchemy_ohci_dmamask; + + if (platform_device_register(pdev)) + printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n"); + } } /* Macro to help defining the Ethernet MAC resources */ diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index bdd6651e9a4f..0c7fce2a3c12 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -126,6 +126,9 @@ void au_sleep(void) case ALCHEMY_CPU_AU1200: alchemy_sleep_au1550(); break; + case ALCHEMY_CPU_AU1300: + alchemy_sleep_au1300(); + break; } restore_core_regs(); diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S index 77f3c743b716..c7bcc7e5c822 100644 --- a/arch/mips/alchemy/common/sleeper.S +++ b/arch/mips/alchemy/common/sleeper.S @@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550) END(alchemy_sleep_au1550) +/* sleepcode for Au1300 memory controller type */ +LEAF(alchemy_sleep_au1300) + + SETUP_SLEEP + + /* cache following instructions, as memory gets put to sleep */ + la t0, 2f + la t1, 4f + subu t2, t1, t0 + + .set mips3 + +1: cache 0x14, 0(t0) + subu t2, t2, 32 + bgez t2, 1b + addu t0, t0, 32 + + .set mips0 + +2: lui a0, 0xb400 /* mem_xxx */ + + /* disable all ports in mem_sdportcfga */ + sw zero, 0x868(a0) /* mem_sdportcfga */ + sync + + /* disable ODT */ + li t0, 0x03010000 + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sync + + /* precharge */ + li t0, 0x23000400 + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sync + + /* auto refresh */ + sw zero, 0x08c8(a0) /* mem_sdautoref */ + sync + + /* block access to the DDR */ + lw t0, 0x0848(a0) /* mem_sdconfigb */ + li t1, (1 << 7 | 0x3F) + or t0, t0, t1 + sw t0, 0x0848(a0) /* mem_sdconfigb */ + sync + + /* issue the Self Refresh command */ + li t0, 0x10000000 + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sync + + /* wait for sdram to enter self-refresh mode */ + lui t0, 0x0300 +3: lw t1, 0x0850(a0) /* mem_sdstat */ + and t2, t1, t0 + bne t2, t0, 3b + nop + + /* disable SDRAM clocks */ + li t0, ~(3<<28) + lw t1, 0x0840(a0) /* mem_sdconfiga */ + and t1, t1, t0 /* clear CE[1:0] */ + sw t1, 0x0840(a0) /* mem_sdconfiga */ + sync + + DO_SLEEP +4: + +END(alchemy_sleep_au1300) + /* This is where we return upon wakeup. * Reload all of the registers and return. diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index d5da6adbf634..a594a85337d6 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -178,6 +178,7 @@ static int alchemy_m2inttab[] __initdata = { AU1100_RTC_MATCH2_INT, AU1550_RTC_MATCH2_INT, AU1200_RTC_MATCH2_INT, + AU1300_RTC_MATCH2_INT, }; void __init plat_time_init(void) diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c new file mode 100644 index 000000000000..d23b1444d365 --- /dev/null +++ b/arch/mips/alchemy/common/vss.c @@ -0,0 +1,84 @@ +/* + * Au1300 media block power gating (VSS) + * + * This is a stop-gap solution until I have the clock framework integration + * ready. This stuff here really must be handled transparently when clocks + * for various media blocks are enabled/disabled. + */ + +#include +#include +#include + +#define VSS_GATE 0x00 /* gate wait timers */ +#define VSS_CLKRST 0x04 /* clock/block control */ +#define VSS_FTR 0x08 /* footers */ + +#define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c)) + +static DEFINE_SPINLOCK(au1300_vss_lock); + +/* enable a block as outlined in the databook */ +static inline void __enable_block(int block) +{ + void __iomem *base = (void __iomem *)VSS_ADDR(block); + + __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ + wmb(); + + __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ + wmb(); + + /* enable footers in sequence */ + __raw_writel(0x01, base + VSS_FTR); + wmb(); + __raw_writel(0x03, base + VSS_FTR); + wmb(); + __raw_writel(0x07, base + VSS_FTR); + wmb(); + __raw_writel(0x0f, base + VSS_FTR); + wmb(); + + __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ + wmb(); + + __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ + wmb(); + + __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ + wmb(); +} + +/* disable a block as outlined in the databook */ +static inline void __disable_block(int block) +{ + void __iomem *base = (void __iomem *)VSS_ADDR(block); + + __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ + wmb(); + __raw_writel(0, base + VSS_GATE); /* disable FSM */ + wmb(); + __raw_writel(3, base + VSS_CLKRST); /* assert reset */ + wmb(); + __raw_writel(1, base + VSS_CLKRST); /* disable clock */ + wmb(); + __raw_writel(0, base + VSS_FTR); /* disable all footers */ + wmb(); +} + +void au1300_vss_block_control(int block, int enable) +{ + unsigned long flags; + + if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300) + return; + + /* only one block at a time */ + spin_lock_irqsave(&au1300_vss_lock, flags); + if (enable) + __enable_block(block); + else + __disable_block(block); + spin_unlock_irqrestore(&au1300_vss_lock, flags); +} +EXPORT_SYMBOL_GPL(au1300_vss_block_control); diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 2f7f41873f24..79e4a0dad0d9 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -169,6 +169,7 @@ #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 +#define PRID_IMP_NETLOGIC_AU13XX 0x8000 /* * Definitions for 7:0 on legacy processors diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index de24ec57dd2f..65f126217175 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void) #define ALCHEMY_CPU_AU1100 2 #define ALCHEMY_CPU_AU1550 3 #define ALCHEMY_CPU_AU1200 4 +#define ALCHEMY_CPU_AU1300 5 static inline int alchemy_get_cputype(void) { @@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void) case 0x05030000: return ALCHEMY_CPU_AU1200; break; + case 0x800c0000: + return ALCHEMY_CPU_AU1300; + break; } return ALCHEMY_CPU_UNKNOWN; @@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type) { switch (type) { case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1300: return 4; case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1200: @@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void); /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); +void alchemy_sleep_au1300(void); void au_sleep(void); /* USB: drivers/usb/host/alchemy-common.c */ @@ -251,6 +257,7 @@ enum alchemy_usb_block { ALCHEMY_USB_UDC0, ALCHEMY_USB_EHCI0, ALCHEMY_USB_OTG0, + ALCHEMY_USB_OHCI1, }; int alchemy_usb_control(int block, int enable); @@ -263,14 +270,92 @@ struct alchemy_pci_platdata { unsigned long pci_cfg_clr; }; -/* SOC Interrupt numbers */ +/* Multifunction pins: Each of these pins can either be assigned to the + * GPIO controller or a on-chip peripheral. + * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to + * assign one of these to either the GPIO controller or the device. + */ +enum au1300_multifunc_pins { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, + AU1300_PIN_WAKE3, + /* external clock sources for PSCs: 4-5 */ + AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* aux clk input for freqgen 3: 10 */ + AU1300_PIN_FG3AUX, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 29-31 */ + AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, +}; +/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */ +extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio); +extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio); +extern void au1300_set_irq_priority(unsigned int irq, int p); +extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); + +/* Au1300 allows to disconnect certain blocks from internal power supply */ +enum au1300_vss_block { + AU1300_VSS_MPE = 0, + AU1300_VSS_BSA, + AU1300_VSS_GPE, + AU1300_VSS_MGP, +}; + +extern void au1300_vss_block_control(int block, int enable); + + +/* SOC Interrupt numbers */ +/* Au1000-style (IC0/1): 2 controllers with 32 sources each */ #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST +/* Au1300-style (GPIC): 1 controller with up to 128 sources */ +#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) +#define ALCHEMY_GPIC_INT_NUM 128 +#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1) + enum soc_au1000_ints { AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, AU1000_UART0_INT = AU1000_FIRST_INT, @@ -591,24 +676,77 @@ enum soc_au1200_ints { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ +/* Au1300 peripheral interrupt numbers */ +#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) +#define AU1300_UART1_INT (AU1300_FIRST_INT + 17) +#define AU1300_UART2_INT (AU1300_FIRST_INT + 25) +#define AU1300_UART3_INT (AU1300_FIRST_INT + 27) +#define AU1300_SD1_INT (AU1300_FIRST_INT + 32) +#define AU1300_SD2_INT (AU1300_FIRST_INT + 38) +#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) +#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) +#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) +#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) +#define AU1300_NAND_INT (AU1300_FIRST_INT + 62) +#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) +#define AU1300_MMU_INT (AU1300_FIRST_INT + 76) +#define AU1300_MPU_INT (AU1300_FIRST_INT + 77) +#define AU1300_GPU_INT (AU1300_FIRST_INT + 78) +#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) +#define AU1300_TOY_INT (AU1300_FIRST_INT + 80) +#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) +#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) +#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) +#define AU1300_RTC_INT (AU1300_FIRST_INT + 84) +#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) +#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) +#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) +#define AU1300_UART0_INT (AU1300_FIRST_INT + 88) +#define AU1300_SD0_INT (AU1300_FIRST_INT + 89) +#define AU1300_USB_INT (AU1300_FIRST_INT + 90) +#define AU1300_LCD_INT (AU1300_FIRST_INT + 91) +#define AU1300_BSA_INT (AU1300_FIRST_INT + 92) +#define AU1300_MPE_INT (AU1300_FIRST_INT + 93) +#define AU1300_ITE_INT (AU1300_FIRST_INT + 94) +#define AU1300_AES_INT (AU1300_FIRST_INT + 95) +#define AU1300_CIM_INT (AU1300_FIRST_INT + 96) + +/**********************************************************************/ + /* * Physical base addresses for integrated peripherals - * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 + * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 */ #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ +#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */ +#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */ +#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */ +#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */ +#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */ +#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */ +#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */ #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */ #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ -#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ +#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ +#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ -#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ +#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */ +#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */ +#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */ #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ +#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */ #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ +#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */ +#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */ +#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */ +#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */ #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ @@ -622,37 +760,96 @@ enum soc_au1200_ints { #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ -#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ +#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */ #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ +#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */ #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ -#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ -#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ +#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */ +#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ -#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ +#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */ #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ +#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */ +#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */ #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ +#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */ +#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */ +#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */ +#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */ +#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */ +#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */ #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ -#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ +#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */ #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ -#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ -#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ -#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ +#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */ +#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */ +#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */ +/**********************************************************************/ + + +/* + * Au1300 GPIO+INT controller (GPIC) register offsets and bits + * Registers are 128bits (0x10 bytes), divided into 4 "banks". + */ +#define AU1300_GPIC_PINVAL 0x0000 +#define AU1300_GPIC_PINVALCLR 0x0010 +#define AU1300_GPIC_IPEND 0x0020 +#define AU1300_GPIC_PRIENC 0x0030 +#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ +#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ +#define AU1300_GPIC_DMASEL 0x0060 +#define AU1300_GPIC_DEVSEL 0x0080 +#define AU1300_GPIC_DEVCLR 0x0090 +#define AU1300_GPIC_RSTVAL 0x00a0 +/* pin configuration space. one 32bit register for up to 128 IRQs */ +#define AU1300_GPIC_PINCFG 0x1000 + +#define GPIC_GPIO_TO_BIT(gpio) \ + (1 << ((gpio) & 0x1f)) + +#define GPIC_GPIO_BANKOFF(gpio) \ + (((gpio) >> 5) * 4) + +/* Pin Control bits: who owns the pin, what does it do */ +#define GPIC_CFG_PC_GPIN 0 +#define GPIC_CFG_PC_DEV 1 +#define GPIC_CFG_PC_GPOLOW 2 +#define GPIC_CFG_PC_GPOHIGH 3 +#define GPIC_CFG_PC_MASK 3 + +/* assign pin to MIPS IRQ line */ +#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) +#define GPIC_CFG_IL_MASK (3 << 2) + +/* pin interrupt type setup */ +#define GPIC_CFG_IC_OFF (0 << 4) +#define GPIC_CFG_IC_LEVEL_LOW (1 << 4) +#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) +#define GPIC_CFG_IC_EDGE_FALL (5 << 4) +#define GPIC_CFG_IC_EDGE_RISE (6 << 4) +#define GPIC_CFG_IC_EDGE_BOTH (7 << 4) +#define GPIC_CFG_IC_MASK (7 << 4) + +/* allow interrupt to wake cpu from 'wait' */ +#define GPIC_CFG_IDLEWAKE (1 << 7) + +/***********************************************************************/ /* Au1000 SDRAM memory controller register offsets */ #define AU1000_MEM_SDMODE0 0x0000 diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h index 94000a3b6f0b..e221659f1bca 100644 --- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h +++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h @@ -130,8 +130,10 @@ struct au1xmmc_platform_data { #define SD_CONFIG2_DF (0x00000008) #define SD_CONFIG2_DC (0x00000010) #define SD_CONFIG2_xx2 (0x000000e0) +#define SD_CONFIG2_BB (0x00000080) #define SD_CONFIG2_WB (0x00000100) #define SD_CONFIG2_RW (0x00000200) +#define SD_CONFIG2_DP (0x00000400) /* diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 323ce2d145f2..217810e18361 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc { #define AU1200_DSCR_CMD0_PSC1_SYNC 25 #define AU1200_DSCR_CMD0_CIM_SYNC 26 +#define AU1300_DSCR_CMD0_UART0_TX 0 +#define AU1300_DSCR_CMD0_UART0_RX 1 +#define AU1300_DSCR_CMD0_UART1_TX 2 +#define AU1300_DSCR_CMD0_UART1_RX 3 +#define AU1300_DSCR_CMD0_UART2_TX 4 +#define AU1300_DSCR_CMD0_UART2_RX 5 +#define AU1300_DSCR_CMD0_UART3_TX 6 +#define AU1300_DSCR_CMD0_UART3_RX 7 +#define AU1300_DSCR_CMD0_SDMS_TX0 8 +#define AU1300_DSCR_CMD0_SDMS_RX0 9 +#define AU1300_DSCR_CMD0_SDMS_TX1 10 +#define AU1300_DSCR_CMD0_SDMS_RX1 11 +#define AU1300_DSCR_CMD0_AES_TX 12 +#define AU1300_DSCR_CMD0_AES_RX 13 +#define AU1300_DSCR_CMD0_PSC0_TX 14 +#define AU1300_DSCR_CMD0_PSC0_RX 15 +#define AU1300_DSCR_CMD0_PSC1_TX 16 +#define AU1300_DSCR_CMD0_PSC1_RX 17 +#define AU1300_DSCR_CMD0_PSC2_TX 18 +#define AU1300_DSCR_CMD0_PSC2_RX 19 +#define AU1300_DSCR_CMD0_PSC3_TX 20 +#define AU1300_DSCR_CMD0_PSC3_RX 21 +#define AU1300_DSCR_CMD0_LCD 22 +#define AU1300_DSCR_CMD0_NAND_FLASH 23 +#define AU1300_DSCR_CMD0_SDMS_TX2 24 +#define AU1300_DSCR_CMD0_SDMS_RX2 25 +#define AU1300_DSCR_CMD0_CIM_SYNC 26 +#define AU1300_DSCR_CMD0_UDMA 27 +#define AU1300_DSCR_CMD0_DMA_REQ0 28 +#define AU1300_DSCR_CMD0_DMA_REQ1 29 + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h new file mode 100644 index 000000000000..556e1be20bf6 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -0,0 +1,241 @@ +/* + * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles. + * + * Copyright (c) 2009-2011 Manuel Lauss + */ + +#ifndef _GPIO_AU1300_H_ +#define _GPIO_AU1300_H_ + +#include +#include +#include + +/* with the current GPIC design, up to 128 GPIOs are possible. + * The only implementation so far is in the Au1300, which has 75 externally + * available GPIOs. + */ +#define AU1300_GPIO_BASE 0 +#define AU1300_GPIO_NUM 75 +#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) + +#define AU1300_GPIC_ADDR \ + (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) + +static inline int au1300_gpio_get_value(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + int bit; + + gpio -= AU1300_GPIO_BASE; + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; +} + +static inline int au1300_gpio_direction_input(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); + wmb(); + + return 0; +} + +static inline int au1300_gpio_set_value(unsigned int gpio, int v) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL + : AU1300_GPIC_PINVALCLR)); + wmb(); + + return 0; +} + +static inline int au1300_gpio_direction_output(unsigned int gpio, int v) +{ + /* hw switches to output automatically */ + return au1300_gpio_set_value(gpio, v); +} + +static inline int au1300_gpio_to_irq(unsigned int gpio) +{ + return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); +} + +static inline int au1300_irq_to_gpio(unsigned int irq) +{ + return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; +} + +static inline int au1300_gpio_is_valid(unsigned int gpio) +{ + int ret; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); + break; + default: + ret = 0; + } + return ret; +} + +static inline int au1300_gpio_cansleep(unsigned int gpio) +{ + return 0; +} + +/* hardware remembers gpio 0-63 levels on powerup */ +static inline int au1300_gpio_getinitlvl(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long v; + + if (unlikely(gpio > 63)) + return 0; + else if (gpio > 31) { + gpio -= 32; + roff += 4; + } + + v = __raw_readl(roff + AU1300_GPIC_RSTVAL); + return (v >> gpio) & 1; +} + +/**********************************************************************/ + +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifndef CONFIG_GPIOLIB + +#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300 + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(unsigned int gpio) +{ + return au1300_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned int gpio, int v) +{ + return au1300_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(unsigned int gpio) +{ + return au1300_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int v) +{ + au1300_gpio_set_value(gpio, v); +} + +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + +static inline int gpio_is_valid(unsigned int gpio) +{ + return au1300_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(unsigned int gpio) +{ + return au1300_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned int gpio) +{ + return au1300_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return au1300_irq_to_gpio(irq); +} + +static inline int gpio_request(unsigned int gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned int gpio) +{ +} + +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + +#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */ + +#endif /* CONFIG GPIOLIB */ + +#endif /* _GPIO_AU1300_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index fcdc8c4809db..22e7ff17fc48 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -12,6 +12,7 @@ #include #include +#include /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this @@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq) switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: return alchemy_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1300: + return au1300_irq_to_gpio(irq); } return -EINVAL; } diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c7d3cf1ce46e..98383995e6ac 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1014,6 +1014,13 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) { decode_configs(c); + if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { + c->cputype = CPU_ALCHEMY; + __cpu_name[cpu] = "Au1300"; + /* following stuff is not for Alchemy */ + return; + } + c->options = (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_COUNTER | diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index a3afac4be734..cbe7a2fb779f 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -299,11 +299,11 @@ config I2C_AT91 unless your system can cope with those limitations. config I2C_AU1550 - tristate "Au1550/Au1200 SMBus interface" + tristate "Au1550/Au1200/Au1300 SMBus interface" depends on MIPS_ALCHEMY help If you say yes to this option, support will be included for the - Au1550 and Au1200 SMBus interface. + Au1550/Au1200/Au1300 SMBus interface. This driver can also be built as a module. If so, the module will be called i2c-au1550. diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index 5d3b9ae64523..dbd0c8a4e98a 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -153,6 +153,7 @@ static inline int has_dbdma(void) { switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1200: + case ALCHEMY_CPU_AU1300: return 1; default: return 0; @@ -768,11 +769,15 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) config2 = au_readl(HOST_CONFIG2(host)); switch (ios->bus_width) { + case MMC_BUS_WIDTH_8: + config2 |= SD_CONFIG2_BB; + break; case MMC_BUS_WIDTH_4: + config2 &= ~SD_CONFIG2_BB; config2 |= SD_CONFIG2_WB; break; case MMC_BUS_WIDTH_1: - config2 &= ~SD_CONFIG2_WB; + config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB); break; } au_writel(config2, HOST_CONFIG2(host)); @@ -943,7 +948,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) struct mmc_host *mmc; struct au1xmmc_host *host; struct resource *r; - int ret; + int ret, iflag; mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); if (!mmc) { @@ -982,37 +987,43 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "no IRQ defined\n"); goto out3; } - host->irq = r->start; - /* IRQ is shared among both SD controllers */ - ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED, - DRIVER_NAME, host); - if (ret) { - dev_err(&pdev->dev, "cannot grab IRQ\n"); - goto out3; - } mmc->ops = &au1xmmc_ops; mmc->f_min = 450000; mmc->f_max = 24000000; - switch (alchemy_get_cputype()) { - case ALCHEMY_CPU_AU1100: - mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; - mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; - break; - case ALCHEMY_CPU_AU1200: - mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; - mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; - break; - } - mmc->max_blk_size = 2048; mmc->max_blk_count = 512; mmc->ocr_avail = AU1XMMC_OCR; mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; + mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; + + iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */ + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1100: + mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; + break; + case ALCHEMY_CPU_AU1200: + mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; + break; + case ALCHEMY_CPU_AU1300: + iflag = 0; /* nothing is shared */ + mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; + mmc->f_max = 52000000; + if (host->ioarea->start == AU1100_SD0_PHYS_ADDR) + mmc->caps |= MMC_CAP_8_BIT_DATA; + break; + } + + ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host); + if (ret) { + dev_err(&pdev->dev, "cannot grab IRQ\n"); + goto out3; + } host->status = HOST_S_IDLE; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1fd73df5416..369e092bf3d5 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -87,12 +87,12 @@ config SPI_BFIN_SPORT Enable support for a SPI bus via the Blackfin SPORT peripheral. config SPI_AU1550 - tristate "Au1550/Au12x0 SPI Controller" + tristate "Au1550/Au1200/Au1300 SPI Controller" depends on MIPS_ALCHEMY && EXPERIMENTAL select SPI_BITBANG help If you say yes to this option, support will be included for the - Au1550 SPI controller (may also work with Au1200,Au1210,Au1250). + PSC SPI controller found on Au1550, Au1200 and Au1300 series. config SPI_BITBANG tristate "Utilities for Bitbanging SPI masters" diff --git a/drivers/usb/host/alchemy-common.c b/drivers/usb/host/alchemy-common.c index b4192c964d0d..936af8359fb2 100644 --- a/drivers/usb/host/alchemy-common.c +++ b/drivers/usb/host/alchemy-common.c @@ -52,9 +52,263 @@ USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \ USBCFG_OME) +/* Au1300 USB config registers */ +#define USB_DWC_CTRL1 0x00 +#define USB_DWC_CTRL2 0x04 +#define USB_VBUS_TIMER 0x10 +#define USB_SBUS_CTRL 0x14 +#define USB_MSR_ERR 0x18 +#define USB_DWC_CTRL3 0x1C +#define USB_DWC_CTRL4 0x20 +#define USB_OTG_STATUS 0x28 +#define USB_DWC_CTRL5 0x2C +#define USB_DWC_CTRL6 0x30 +#define USB_DWC_CTRL7 0x34 +#define USB_PHY_STATUS 0xC0 +#define USB_INT_STATUS 0xC4 +#define USB_INT_ENABLE 0xC8 + +#define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */ +#define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */ +#define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */ + +#define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */ +#define USB_DWC_CTRL2_PHY0RS 0x02 /* set to enable PHY0 */ +#define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */ + +#define USB_DWC_CTRL3_OHCI1_CKEN (1 << 19) +#define USB_DWC_CTRL3_OHCI0_CKEN (1 << 18) +#define USB_DWC_CTRL3_EHCI0_CKEN (1 << 17) +#define USB_DWC_CTRL3_OTG0_CKEN (1 << 16) + +#define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */ + +#define USB_INTEN_FORCE 0x20 +#define USB_INTEN_PHY 0x10 +#define USB_INTEN_UDC 0x08 +#define USB_INTEN_EHCI 0x04 +#define USB_INTEN_OHCI1 0x02 +#define USB_INTEN_OHCI0 0x01 static DEFINE_SPINLOCK(alchemy_usb_lock); +static inline void __au1300_usb_phyctl(void __iomem *base, int enable) +{ + unsigned long r, s; + + r = __raw_readl(base + USB_DWC_CTRL2); + s = __raw_readl(base + USB_DWC_CTRL3); + + s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN | + USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN; + + if (enable) { + /* simply enable all PHYs */ + r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS | + USB_DWC_CTRL2_PHYRS; + __raw_writel(r, base + USB_DWC_CTRL2); + wmb(); + } else if (!s) { + /* no USB block active, do disable all PHYs */ + r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS | + USB_DWC_CTRL2_PHYRS); + __raw_writel(r, base + USB_DWC_CTRL2); + wmb(); + } +} + +static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) +{ + unsigned long r; + + if (enable) { + __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ + r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN + : USB_DWC_CTRL3_OHCI1_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + __au1300_usb_phyctl(base, enable); /* power up the PHYs */ + + r = __raw_readl(base + USB_INT_ENABLE); + r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + + /* reset the OHCI start clock bit */ + __raw_writel(0, base + USB_DWC_CTRL7); + wmb(); + } else { + r = __raw_readl(base + USB_INT_ENABLE); + r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1); + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL3); + r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN + : USB_DWC_CTRL3_OHCI1_CKEN); + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + __au1300_usb_phyctl(base, enable); + } +} + +static inline void __au1300_ehci_control(void __iomem *base, int enable) +{ + unsigned long r; + + if (enable) { + r = __raw_readl(base + USB_DWC_CTRL3); + r |= USB_DWC_CTRL3_EHCI0_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL1); + r |= USB_DWC_CTRL1_HSTRS; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + __au1300_usb_phyctl(base, enable); + + r = __raw_readl(base + USB_INT_ENABLE); + r |= USB_INTEN_EHCI; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + } else { + r = __raw_readl(base + USB_INT_ENABLE); + r &= ~USB_INTEN_EHCI; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL1); + r &= ~USB_DWC_CTRL1_HSTRS; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL3); + r &= ~USB_DWC_CTRL3_EHCI0_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + __au1300_usb_phyctl(base, enable); + } +} + +static inline void __au1300_udc_control(void __iomem *base, int enable) +{ + unsigned long r; + + if (enable) { + r = __raw_readl(base + USB_DWC_CTRL1); + r |= USB_DWC_CTRL1_DCRS; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + __au1300_usb_phyctl(base, enable); + + r = __raw_readl(base + USB_INT_ENABLE); + r |= USB_INTEN_UDC; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + } else { + r = __raw_readl(base + USB_INT_ENABLE); + r &= ~USB_INTEN_UDC; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL1); + r &= ~USB_DWC_CTRL1_DCRS; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + __au1300_usb_phyctl(base, enable); + } +} + +static inline void __au1300_otg_control(void __iomem *base, int enable) +{ + unsigned long r; + if (enable) { + r = __raw_readl(base + USB_DWC_CTRL3); + r |= USB_DWC_CTRL3_OTG0_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL1); + r &= ~USB_DWC_CTRL1_OTGD; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + __au1300_usb_phyctl(base, enable); + } else { + r = __raw_readl(base + USB_DWC_CTRL1); + r |= USB_DWC_CTRL1_OTGD; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL3); + r &= ~USB_DWC_CTRL3_OTG0_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + __au1300_usb_phyctl(base, enable); + } +} + +static inline int au1300_usb_control(int block, int enable) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); + int ret = 0; + + switch (block) { + case ALCHEMY_USB_OHCI0: + __au1300_ohci_control(base, enable, 0); + break; + case ALCHEMY_USB_OHCI1: + __au1300_ohci_control(base, enable, 1); + break; + case ALCHEMY_USB_EHCI0: + __au1300_ehci_control(base, enable); + break; + case ALCHEMY_USB_UDC0: + __au1300_udc_control(base, enable); + break; + case ALCHEMY_USB_OTG0: + __au1300_otg_control(base, enable); + break; + default: + ret = -ENODEV; + } + return ret; +} + +static inline void au1300_usb_init(void) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); + + /* set some sane defaults. Note: we don't fiddle with DWC_CTRL4 + * here at all: Port 2 routing (EHCI or UDC) must be set either + * by boot firmware or platform init code; I can't autodetect + * a sane setting. + */ + __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */ + wmb(); + __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */ + wmb(); + __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */ + wmb(); + __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */ + wmb(); + /* set coherent access bit */ + __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL); + wmb(); +} static inline void __au1200_ohci_control(void __iomem *base, int enable) { @@ -233,6 +487,9 @@ int alchemy_usb_control(int block, int enable) case ALCHEMY_CPU_AU1200: ret = au1200_usb_control(block, enable); break; + case ALCHEMY_CPU_AU1300: + ret = au1300_usb_control(block, enable); + break; default: ret = -ENODEV; } @@ -281,6 +538,20 @@ static void au1200_usb_pm(int susp) } } +static void au1300_usb_pm(int susp) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); + /* remember Port2 routing */ + if (susp) { + alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4); + } else { + au1300_usb_init(); + __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4); + wmb(); + } +} + static void alchemy_usb_pm(int susp) { switch (alchemy_get_cputype()) { @@ -295,6 +566,9 @@ static void alchemy_usb_pm(int susp) case ALCHEMY_CPU_AU1200: au1200_usb_pm(susp); break; + case ALCHEMY_CPU_AU1300: + au1300_usb_pm(susp); + break; } } @@ -328,6 +602,9 @@ static int __init alchemy_usb_init(void) case ALCHEMY_CPU_AU1200: au1200_usb_init(); break; + case ALCHEMY_CPU_AU1300: + au1300_usb_init(); + break; } register_syscore_ops(&alchemy_usb_pm_ops); diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 9b66df8278f3..95d1a71dccad 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -89,7 +89,7 @@ static const struct hc_driver ohci_au1xxx_hc_driver = { static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) { - int ret; + int ret, unit; struct usb_hcd *hcd; if (usb_disabled()) @@ -120,7 +120,9 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) goto err2; } - if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) { + unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ? + ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0; + if (alchemy_usb_control(unit, 1)) { printk(KERN_INFO "%s: controller init failed!\n", pdev->name); ret = -ENODEV; goto err3; @@ -135,7 +137,7 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) return ret; } - alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); + alchemy_usb_control(unit, 0); err3: iounmap(hcd->regs); err2: @@ -148,9 +150,12 @@ err1: static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev) { struct usb_hcd *hcd = platform_get_drvdata(pdev); + int unit; + unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ? + ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0; usb_remove_hcd(hcd); - alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); + alchemy_usb_control(unit, 0); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index d83e967e4e15..acd4ba555e3a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1763,16 +1763,16 @@ config FB_AU1100 au1100fb:panel=. config FB_AU1200 - bool "Au1200 LCD Driver" + bool "Au1200/Au1300 LCD Driver" depends on (FB = y) && MIPS_ALCHEMY select FB_SYS_FILLRECT select FB_SYS_COPYAREA select FB_SYS_IMAGEBLIT select FB_SYS_FOPS help - This is the framebuffer driver for the AMD Au1200 SOC. It can drive - various panels and CRTs by passing in kernel cmd line option - au1200fb:panel=. + This is the framebuffer driver for the Au1200/Au1300 SOCs. + It can drive various panels and CRTs by passing in kernel cmd line + option au1200fb:panel=. config FB_VT8500 bool "VT8500 LCD Driver" diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index e908a8123110..93323cc0452a 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -1,13 +1,13 @@ ## -## Au1200/Au1550 PSC + DBDMA +## Au1200/Au1550/Au1300 PSC + DBDMA ## config SND_SOC_AU1XPSC - tristate "SoC Audio for Au1200/Au1250/Au1550" + tristate "SoC Audio for Au12xx/Au13xx/Au1550" depends on MIPS_ALCHEMY help This option enables support for the Programmable Serial Controllers in AC97 and I2S mode, and the Descriptor-Based DMA - Controller (DBDMA) as found on the Au1200/Au1250/Au1550 SoC. + Controller (DBDMA) as found on the Au12xx/Au13xx/Au1550 SoC. config SND_SOC_AU1XPSC_I2S tristate From 64cd04d0cffa3b3af0e81aa3112b71f135739e1a Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:03:26 +0000 Subject: [PATCH 008/119] MIPS: Alchemy: Basic support for the DB1300 board. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2867/ Patchwork: https://patchwork.linux-mips.org/patch/2919/ Patchwork: https://patchwork.linux-mips.org/patch/2928/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 8 + arch/mips/alchemy/Platform | 7 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300.c | 787 +++++++++++++++++++++ arch/mips/alchemy/devboards/prom.c | 4 + arch/mips/boot/compressed/uart-alchemy.c | 5 +- arch/mips/configs/db1300_defconfig | 391 ++++++++++ arch/mips/include/asm/mach-db1x00/bcsr.h | 34 +- arch/mips/include/asm/mach-db1x00/db1300.h | 40 ++ arch/mips/include/asm/mach-db1x00/irq.h | 23 + drivers/pcmcia/Kconfig | 4 +- drivers/pcmcia/db1xxx_ss.c | 26 +- drivers/video/au1200fb.c | 36 + sound/soc/au1x/Kconfig | 8 +- sound/soc/au1x/db1200.c | 43 +- 15 files changed, 1398 insertions(+), 19 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1300.c create mode 100644 arch/mips/configs/db1300_defconfig create mode 100644 arch/mips/include/asm/mach-db1x00/db1300.h create mode 100644 arch/mips/include/asm/mach-db1x00/irq.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 766badaef3b0..f9a13beada4a 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -49,6 +49,14 @@ config MIPS_DB1200 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK +config MIPS_DB1300 + bool "NetLogic DB1300 board" + select ALCHEMY_GPIOINT_AU1300 + select DMA_COHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + config MIPS_DB1500 bool "Alchemy DB1500 board" select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 2920af9c2569..4d13e21eaf83 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -67,6 +67,13 @@ platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 +# +# NetLogic DBAu1300 development platform +# +platform-$(CONFIG_MIPS_DB1300) += alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 + # # 4G-Systems eval board # diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 5afaf944868f..2eb75c92a583 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_MIPS_PB1550) += pb1550/ obj-$(CONFIG_MIPS_DB1000) += db1x00/ obj-$(CONFIG_MIPS_DB1100) += db1x00/ obj-$(CONFIG_MIPS_DB1200) += db1200/ +obj-$(CONFIG_MIPS_DB1300) += db1300.o obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c new file mode 100644 index 000000000000..c41788c59278 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300.c @@ -0,0 +1,787 @@ +/* + * DBAu1300 init and platform device setup. + * + * (c) 2009 Manuel Lauss + */ + +#include +#include +#include +#include +#include /* KEY_* codes */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "platform.h" + +static struct i2c_board_info db1300_i2c_devs[] __initdata = { + { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */ + { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ +}; + +/* multifunction pins to assign to GPIO controller */ +static int db1300_gpio_pins[] __initdata = { + AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1, + AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX, + AU1300_PIN_EXTCLK1, + -1, /* terminator */ +}; + +/* multifunction pins to assign to device functions */ +static int db1300_dev_pins[] __initdata = { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0, + /* external clock sources for PSC0 */ + AU1300_PIN_EXTCLK0, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 30-31 */ + AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, + -1, /* terminator */ +}; + +static void __init db1300_gpio_config(void) +{ + int *i; + + i = &db1300_dev_pins[0]; + while (*i != -1) + au1300_pinfunc_to_dev(*i++); + + i = &db1300_gpio_pins[0]; + while (*i != -1) + au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */ + + au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); +} + +char *get_system_type(void) +{ + return "DB1300"; +} + +/**********************************************************************/ + +static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; + + ioaddr &= 0xffffff00; + + if (ctrl & NAND_CLE) { + ioaddr += MEM_STNAND_CMD; + } else if (ctrl & NAND_ALE) { + ioaddr += MEM_STNAND_ADDR; + } else { + /* assume we want to r/w real data by default */ + ioaddr += MEM_STNAND_DATA; + } + this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; + if (cmd != NAND_CMD_NONE) { + __raw_writeb(cmd, this->IO_ADDR_W); + wmb(); + } +} + +static int au1300_nand_device_ready(struct mtd_info *mtd) +{ + return __raw_readl((void __iomem *)MEM_STSTAT) & 1; +} + +static const char *db1300_part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition db1300_nand_parts[] = { + { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +struct platform_nand_data db1300_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(db1300_nand_parts), + .partitions = db1300_nand_parts, + .chip_delay = 20, + .part_probe_types = db1300_part_probes, + }, + .ctrl = { + .dev_ready = au1300_nand_device_ready, + .cmd_ctrl = au1300_nand_cmd_ctrl, + }, +}; + +static struct resource db1300_nand_res[] = { + [0] = { + .start = DB1300_NAND_PHYS_ADDR, + .end = DB1300_NAND_PHYS_ADDR + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1300_nand_dev = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(db1300_nand_res), + .resource = db1300_nand_res, + .id = -1, + .dev = { + .platform_data = &db1300_nand_platdata, + } +}; + +/**********************************************************************/ + +static struct resource db1300_eth_res[] = { + [0] = { + .start = DB1300_ETH_PHYS_ADDR, + .end = DB1300_ETH_PHYS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_ETH_INT, + .end = DB1300_ETH_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config db1300_eth_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device db1300_eth_dev = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(db1300_eth_res), + .resource = db1300_eth_res, + .dev = { + .platform_data = &db1300_eth_config, + }, +}; + +/**********************************************************************/ + +static struct resource au1300_psc1_res[] = { + [0] = { + .start = AU1300_PSC1_PHYS_ADDR, + .end = AU1300_PSC1_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC1_INT, + .end = AU1300_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC1_TX, + .end = AU1300_DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC1_RX, + .end = AU1300_DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_ac97_dev = { + .name = "au1xpsc_ac97", + .id = 1, /* PSC ID. match with AC97 codec ID! */ + .num_resources = ARRAY_SIZE(au1300_psc1_res), + .resource = au1300_psc1_res, +}; + +/**********************************************************************/ + +static struct resource au1300_psc2_res[] = { + [0] = { + .start = AU1300_PSC2_PHYS_ADDR, + .end = AU1300_PSC2_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC2_INT, + .end = AU1300_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC2_TX, + .end = AU1300_DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC2_RX, + .end = AU1300_DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2s_dev = { + .name = "au1xpsc_i2s", + .id = 2, /* PSC ID */ + .num_resources = ARRAY_SIZE(au1300_psc2_res), + .resource = au1300_psc2_res, +}; + +/**********************************************************************/ + +static struct resource au1300_psc3_res[] = { + [0] = { + .start = AU1300_PSC3_PHYS_ADDR, + .end = AU1300_PSC3_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC3_INT, + .end = AU1300_PSC3_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC3_TX, + .end = AU1300_DSCR_CMD0_PSC3_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC3_RX, + .end = AU1300_DSCR_CMD0_PSC3_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1300_psc3_res), + .resource = au1300_psc3_res, +}; + +/**********************************************************************/ + +/* proper key assignments when facing the LCD panel. For key assignments + * according to the schematics swap up with down and left with right. + * I chose to use it to emulate the arrow keys of a keyboard. + */ +static struct gpio_keys_button db1300_5waysw_arrowkeys[] = { + { + .code = KEY_DOWN, + .gpio = AU1300_PIN_LCDPWM0, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-down", + }, + { + .code = KEY_UP, + .gpio = AU1300_PIN_PSC2SYNC1, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-up", + }, + { + .code = KEY_RIGHT, + .gpio = AU1300_PIN_WAKE3, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-right", + }, + { + .code = KEY_LEFT, + .gpio = AU1300_PIN_WAKE2, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-left", + }, + { + .code = KEY_ENTER, + .gpio = AU1300_PIN_WAKE1, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-push", + }, +}; + +static struct gpio_keys_platform_data db1300_5waysw_data = { + .buttons = db1300_5waysw_arrowkeys, + .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys), + .rep = 1, + .name = "db1300-5wayswitch", +}; + +static struct platform_device db1300_5waysw_dev = { + .name = "gpio-keys", + .dev = { + .platform_data = &db1300_5waysw_data, + }, +}; + +/**********************************************************************/ + +static struct platform_device db1300_rtc_dev = { + .name = "rtc-au1xxx", + .id = -1, +}; + +/**********************************************************************/ + +static struct pata_platform_info db1300_ide_info = { + .ioport_shift = DB1300_IDE_REG_SHIFT, +}; + +#define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT) +static struct resource db1300_ide_res[] = { + [0] = { + .start = DB1300_IDE_PHYS_ADDR, + .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START, + .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = DB1300_IDE_INT, + .end = DB1300_IDE_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device db1300_ide_dev = { + .dev = { + .platform_data = &db1300_ide_info, + }, + .name = "pata_platform", + .resource = db1300_ide_res, + .num_resources = ARRAY_SIZE(db1300_ide_res), +}; + +/**********************************************************************/ + +static irqreturn_t db1300_mmc_cd(int irq, void *ptr) +{ + void(*mmc_cd)(struct mmc_host *, unsigned long); + + /* disable the one currently screaming. No other way to shut it up */ + if (irq == DB1300_SD1_INSERT_INT) { + disable_irq_nosync(DB1300_SD1_INSERT_INT); + enable_irq(DB1300_SD1_EJECT_INT); + } else { + disable_irq_nosync(DB1300_SD1_EJECT_INT); + enable_irq(DB1300_SD1_INSERT_INT); + } + + /* link against CONFIG_MMC=m. We can only be called once MMC core has + * initialized the controller, so symbol_get() should always succeed. + */ + mmc_cd = symbol_get(mmc_detect_change); + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + + return IRQ_HANDLED; +} + +static int db1300_mmc_card_readonly(void *mmc_host) +{ + /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */ + return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP; +} + +static int db1300_mmc_card_inserted(void *mmc_host) +{ + return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */ +} + +static int db1300_mmc_cd_setup(void *mmc_host, int en) +{ + int ret; + + if (en) { + ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0, + "sd_insert", mmc_host); + if (ret) + goto out; + + ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0, + "sd_eject", mmc_host); + if (ret) { + free_irq(DB1300_SD1_INSERT_INT, mmc_host); + goto out; + } + + if (db1300_mmc_card_inserted(mmc_host)) + enable_irq(DB1300_SD1_EJECT_INT); + else + enable_irq(DB1300_SD1_INSERT_INT); + + } else { + free_irq(DB1300_SD1_INSERT_INT, mmc_host); + free_irq(DB1300_SD1_EJECT_INT, mmc_host); + } + ret = 0; +out: + return ret; +} + +static void db1300_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); +} + +static struct led_classdev db1300_mmc_led = { + .brightness_set = db1300_mmcled_set, +}; + +struct au1xmmc_platform_data db1300_sd1_platdata = { + .cd_setup = db1300_mmc_cd_setup, + .card_inserted = db1300_mmc_card_inserted, + .card_readonly = db1300_mmc_card_readonly, + .led = &db1300_mmc_led, +}; + +static struct resource au1300_sd1_res[] = { + [0] = { + .start = AU1300_SD1_PHYS_ADDR, + .end = AU1300_SD1_PHYS_ADDR, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_SD1_INT, + .end = AU1300_SD1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_SDMS_TX1, + .end = AU1300_DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_SDMS_RX1, + .end = AU1300_DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_sd1_dev = { + .dev = { + .platform_data = &db1300_sd1_platdata, + }, + .name = "au1xxx-mmc", + .id = 1, + .resource = au1300_sd1_res, + .num_resources = ARRAY_SIZE(au1300_sd1_res), +}; + +/**********************************************************************/ + +static int db1300_movinand_inserted(void *mmc_host) +{ + return 0; /* disable for now, it doesn't work yet */ +} + +static int db1300_movinand_readonly(void *mmc_host) +{ + return 0; +} + +static void db1300_movinand_led_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); +} + +static struct led_classdev db1300_movinand_led = { + .brightness_set = db1300_movinand_led_set, +}; + +struct au1xmmc_platform_data db1300_sd0_platdata = { + .card_inserted = db1300_movinand_inserted, + .card_readonly = db1300_movinand_readonly, + .led = &db1300_movinand_led, + .mask_host_caps = MMC_CAP_NEEDS_POLL, +}; + +static struct resource au1300_sd0_res[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_SD0_INT, + .end = AU1300_SD0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_SDMS_TX0, + .end = AU1300_DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_SDMS_RX0, + .end = AU1300_DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_sd0_dev = { + .dev = { + .platform_data = &db1300_sd0_platdata, + }, + .name = "au1xxx-mmc", + .id = 0, + .resource = au1300_sd0_res, + .num_resources = ARRAY_SIZE(au1300_sd0_res), +}; + +/**********************************************************************/ + +static struct platform_device db1300_wm9715_dev = { + .name = "wm9712-codec", + .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */ +}; + +static struct platform_device db1300_ac97dma_dev = { + .name = "au1xpsc-pcm", + .id = 1, /* PSC ID */ +}; + +static struct platform_device db1300_i2sdma_dev = { + .name = "au1xpsc-pcm", + .id = 2, /* PSC ID */ +}; + +static struct platform_device db1300_sndac97_dev = { + .name = "db1300-ac97", +}; + +static struct platform_device db1300_sndi2s_dev = { + .name = "db1300-i2s", +}; + +/**********************************************************************/ + +static struct resource au1300_lcd_res[] = { + [0] = { + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_LCD_INT, + .end = AU1300_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1300_lcd_dev = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1300_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1300_lcd_res), + .resource = au1300_lcd_res, +}; + +/**********************************************************************/ + +static struct platform_device *db1300_dev[] __initdata = { + &db1300_eth_dev, + &db1300_i2c_dev, + &db1300_5waysw_dev, + &db1300_rtc_dev, + &db1300_nand_dev, + &db1300_ide_dev, + &db1300_sd0_dev, + &db1300_sd1_dev, + &db1300_lcd_dev, + &db1300_ac97_dev, + &db1300_i2s_dev, + &db1300_wm9715_dev, + &db1300_ac97dma_dev, + &db1300_i2sdma_dev, + &db1300_sndac97_dev, + &db1300_sndi2s_dev, +}; + +static int __init db1300_device_init(void) +{ + int swapped, cpldirq; + + /* setup CPLD IRQ muxer */ + cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); + irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH); + bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); + + /* insert/eject IRQs: one always triggers so don't enable them + * when doing request_irq() on them. DB1200 has this bug too. + */ + irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN); + + /* + * setup board + */ + prom_get_ethernet_addr(&db1300_eth_config.mac[0]); + + i2c_register_board_info(0, db1300_i2c_devs, + ARRAY_SIZE(db1300_i2c_devs)); + + /* Audio PSC clock is supplied by codecs (PSC1, 2) */ + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + /* I2C uses internal 48MHz EXTCLK1 */ + __raw_writel(PSC_SEL_CLK_INTCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + + /* enable power to USB ports */ + bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR); + + /* although it is socket #0, it uses the CPLD bits which previous boards + * have used for socket #1. + */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, + DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1); + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; + db1x_register_norflash(64 << 20, 2, swapped); + + return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); +} +device_initcall(db1300_device_init); + + +void __init board_setup(void) +{ + unsigned short whoami; + + db1300_gpio_config(); + bcsr_init(DB1300_BCSR_PHYS_ADDR, + DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t" + "BoardID %d CPLD Rev %d DaughtercardID %d\n", + BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), + BCSR_WHOAMI_DCID(whoami)); + + /* enable UARTs, YAMON only enables #2 */ + alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); + alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); + alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); +} + + +/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ +int board_au1200fb_panel(void) +{ + return 9; /* DB1300_800x480 */ +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, + BCSR_BOARD_LCDBL); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, + BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); + return 0; +} diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index f734833fbdda..3a73f9663b0f 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -61,5 +61,9 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c index eb063e6dead9..3112df8f90db 100644 --- a/arch/mips/boot/compressed/uart-alchemy.c +++ b/arch/mips/boot/compressed/uart-alchemy.c @@ -2,6 +2,9 @@ void putc(char c) { - /* all current (Jan. 2010) in-kernel boards */ +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig new file mode 100644 index 000000000000..c38b190151c4 --- /dev/null +++ b/arch/mips/configs/db1300_defconfig @@ -0,0 +1,391 @@ +CONFIG_MIPS=y +CONFIG_MIPS_ALCHEMY=y +CONFIG_ALCHEMY_GPIOINT_AU1300=y +CONFIG_MIPS_DB1300=y +CONFIG_SOC_AU1300=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +CONFIG_GENERIC_GPIO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_CPU_MIPS32_R1=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_32BIT=y +CONFIG_PAGE_SIZE_4KB=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="-db1300" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_LZMA=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_FHANDLE=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_TINY_RCU=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_SLAB=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_INLINE_SPIN_UNLOCK=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_MMU=y +CONFIG_PCCARD=y +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_TRAD_SIGNALS=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_INET_TUNNEL=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_UB=y +CONFIG_HAVE_IDE=y +CONFIG_IDE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +CONFIG_BLK_DEV_IDECS=y +CONFIG_IDE_TASK_IOCTL=y +CONFIG_IDE_PROC_FS=y +CONFIG_BLK_DEV_PLATFORM=y +CONFIG_SCSI_MOD=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_SMSC_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_SMSC911X=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_WM97XX=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_SMBUS=y +CONFIG_I2C_AU1550=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_AU1550=y +CONFIG_SPI_BITBANG=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +CONFIG_SENSORS_ADM1025=y +CONFIG_FB=y +CONFIG_FB_AU1200=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_CACHE_LZO=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_I2S=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +CONFIG_SND_SOC_DB1300=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_WM8731=y +CONFIG_SND_SOC_WM9712=y +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_AU1XXX=y +CONFIG_EXT2_FS=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_GENERIC_ACL=y +CONFIG_FAT_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +CONFIG_JFFS2_CMODE_PRIORITY=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="video=au1200fb:panel:bs console=tty console=ttyS2,115200" +CONFIG_DEBUG_ZBOOT=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y +CONFIG_BITREVERSE=y +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 618d2de02ed3..0ef630071304 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -34,6 +34,8 @@ #define PB1200_BCSR_PHYS_ADDR 0x0D800000 #define PB1200_BCSR_HEXLED_OFS 0x00400000 +#define DB1300_BCSR_PHYS_ADDR 0x19800000 +#define DB1300_BCSR_HEXLED_OFS 0x00400000 enum bcsr_id { /* BCSR base 1 */ @@ -105,6 +107,7 @@ enum bcsr_whoami_boards { BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, BCSR_WHOAMI_PB1200_DDR2, BCSR_WHOAMI_DB1200, + BCSR_WHOAMI_DB1300, }; /* STATUS reg. Unless otherwise noted, they're valid on all boards. @@ -118,12 +121,12 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_SRAMWIDTH 0x0080 #define BCSR_STATUS_FLASHBUSY 0x0100 #define BCSR_STATUS_ROMBUSY 0x0400 -#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ +#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */ #define BCSR_STATUS_SD1WP 0x0800 #define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ #define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 -#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ -#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ +#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */ +#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */ #define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ #define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ #define BCSR_STATUS_FLASHDEN 0xC000 @@ -133,6 +136,11 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ #define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ +#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */ +#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */ +#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */ +#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */ +#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */ /* DB/PB1000,1100,1500,1550 */ #define BCSR_RESETS_PHY0 0x0001 @@ -160,12 +168,12 @@ enum bcsr_whoami_boards { #define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ -/* DB/PB1200 */ +/* DB/PB1200/1300 */ #define BCSR_RESETS_ETH 0x0001 #define BCSR_RESETS_CAMERA 0x0002 #define BCSR_RESETS_DC 0x0004 #define BCSR_RESETS_IDE 0x0008 -#define BCSR_RESETS_TV 0x0010 /* DB1200 */ +#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */ /* Not resets but in the same register */ #define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ #define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ @@ -174,13 +182,22 @@ enum bcsr_whoami_boards { #define BCSR_RESETS_SPISEL 0x4000 #define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ +#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */ +#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */ +#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */ +#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */ +#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */ +#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */ +#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ + #define BCSR_BOARD_LCDVEE 0x0001 #define BCSR_BOARD_LCDVDD 0x0002 #define BCSR_BOARD_LCDBL 0x0004 #define BCSR_BOARD_CAMSNAP 0x0010 #define BCSR_BOARD_CAMPWR 0x0020 #define BCSR_BOARD_SD0PWR 0x0040 - +#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */ +#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */ #define BCSR_SWITCHES_DIP 0x00FF #define BCSR_SWITCHES_DIP_1 0x0080 @@ -214,7 +231,10 @@ enum bcsr_whoami_boards { #define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ #define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ #define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ - +#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */ +#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */ +#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */ +#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */ diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h new file mode 100644 index 000000000000..7fe5fb3ba877 --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/db1300.h @@ -0,0 +1,40 @@ +/* + * NetLogic DB1300 board constants + */ + +#ifndef _DB1300_H_ +#define _DB1300_H_ + +/* FPGA (external mux) interrupt sources */ +#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1) +#define DB1300_IDE_INT (DB1300_FIRST_INT + 0) +#define DB1300_ETH_INT (DB1300_FIRST_INT + 1) +#define DB1300_CF_INT (DB1300_FIRST_INT + 2) +#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) +#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) +#define DB1300_DC_INT (DB1300_FIRST_INT + 6) +#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) +#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) +#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) +#define DB1300_AC97_INT (DB1300_FIRST_INT + 10) +#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) +#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) +#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) +#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) +#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) +#define DB1300_LAST_INT (DB1300_FIRST_INT + 15) + +/* SMSC9210 CS */ +#define DB1300_ETH_PHYS_ADDR 0x19000000 +#define DB1300_ETH_PHYS_END 0x197fffff + +/* ATA CS */ +#define DB1300_IDE_PHYS_ADDR 0x18800000 +#define DB1300_IDE_REG_SHIFT 5 +#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) + +/* NAND CS */ +#define DB1300_NAND_PHYS_ADDR 0x20000000 +#define DB1300_NAND_PHYS_END 0x20000fff + +#endif /* _DB1300_H_ */ diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h new file mode 100644 index 000000000000..15b26693238f --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/irq.h @@ -0,0 +1,23 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_IRQ_H +#define __ASM_MACH_GENERIC_IRQ_H + + +#ifdef NR_IRQS +#undef NR_IRQS +#endif + +#ifndef MIPS_CPU_IRQ_BASE +#define MIPS_CPU_IRQ_BASE 0 +#endif + +/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */ +#define NR_IRQS 152 + +#endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index c022b5cedcf9..f9e3fb3a285b 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -161,8 +161,8 @@ config PCMCIA_ALCHEMY_DEVBOARD select 64BIT_PHYS_ADDR help Enable this driver of you want PCMCIA support on your Alchemy - Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200 board. - NOT suitable for the PB1000! + Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200, DB1300 + board. NOT suitable for the PB1000! This driver is also available as a module called db1xxx_ss.ko diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c index 3e49df6d5e3b..5b7c22784aff 100644 --- a/drivers/pcmcia/db1xxx_ss.c +++ b/drivers/pcmcia/db1xxx_ss.c @@ -7,7 +7,7 @@ /* This is a fairly generic PCMCIA socket driver suitable for the * following Alchemy Development boards: - * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200. + * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200, Db1300 * * The Db1000 is used as a reference: Per-socket card-, carddetect- and * statuschange IRQs connected to SoC GPIOs, control and status register @@ -18,6 +18,7 @@ * - Pb1100/Pb1500: single socket only; voltage key bits VS are * at STATUS[5:4] (instead of STATUS[1:0]). * - Au1200-based: additional card-eject irqs, irqs not gpios! + * - Db1300: Db1200-like, no pwr ctrl, single socket (#1). */ #include @@ -59,11 +60,17 @@ struct db1x_pcmcia_sock { #define BOARD_TYPE_DEFAULT 0 /* most boards */ #define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */ #define BOARD_TYPE_PB1100 2 /* VS bits slightly different */ +#define BOARD_TYPE_DB1300 3 /* no power control */ int board_type; }; #define to_db1x_socket(x) container_of(x, struct db1x_pcmcia_sock, socket) +static int db1300_card_inserted(struct db1x_pcmcia_sock *sock) +{ + return bcsr_read(BCSR_SIGSTAT) & (1 << 8); +} + /* DB/PB1200: check CPLD SIGSTATUS register bit 10/12 */ static int db1200_card_inserted(struct db1x_pcmcia_sock *sock) { @@ -84,6 +91,8 @@ static int db1x_card_inserted(struct db1x_pcmcia_sock *sock) switch (sock->board_type) { case BOARD_TYPE_DB1200: return db1200_card_inserted(sock); + case BOARD_TYPE_DB1300: + return db1300_card_inserted(sock); default: return db1000_card_inserted(sock); } @@ -160,7 +169,8 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) * ejection handler have been registered and the currently * active one disabled. */ - if (sock->board_type == BOARD_TYPE_DB1200) { + if ((sock->board_type == BOARD_TYPE_DB1200) || + (sock->board_type == BOARD_TYPE_DB1300)) { ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq, IRQF_DISABLED, "pcmcia_insert", sock); if (ret) @@ -174,7 +184,7 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) } /* enable the currently silent one */ - if (db1200_card_inserted(sock)) + if (db1x_card_inserted(sock)) enable_irq(sock->eject_irq); else enable_irq(sock->insert_irq); @@ -270,7 +280,8 @@ static int db1x_pcmcia_configure(struct pcmcia_socket *skt, } /* create new voltage code */ - cr_set |= ((v << 2) | p) << (sock->nr * 8); + if (sock->board_type != BOARD_TYPE_DB1300) + cr_set |= ((v << 2) | p) << (sock->nr * 8); changed = state->flags ^ sock->old_flags; @@ -343,6 +354,10 @@ static int db1x_pcmcia_get_status(struct pcmcia_socket *skt, /* if Vcc is not zero, we have applied power to a card */ status |= GET_VCC(cr, sock->nr) ? SS_POWERON : 0; + /* DB1300: power always on, but don't tell when no card present */ + if ((sock->board_type == BOARD_TYPE_DB1300) && (status & SS_DETECT)) + status = SS_POWERON | SS_3VCARD | SS_DETECT; + /* reset de-asserted? then we're ready */ status |= (GET_RESET(cr, sock->nr)) ? SS_READY : SS_RESET; @@ -419,6 +434,9 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev) case BCSR_WHOAMI_PB1200 ... BCSR_WHOAMI_DB1200: sock->board_type = BOARD_TYPE_DB1200; break; + case BCSR_WHOAMI_DB1300: + sock->board_type = BOARD_TYPE_DB1300; + break; default: printk(KERN_INFO "db1xxx-ss: unknown board %d!\n", bid); ret = -ENODEV; diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c index 72005598040f..6c4342f1d9b4 100644 --- a/drivers/video/au1200fb.c +++ b/drivers/video/au1200fb.c @@ -639,6 +639,42 @@ static struct panel_settings known_lcd_panels[] = 856, 856, 480, 480, }, + [9] = { + .name = "DB1300_800x480", + .monspecs = { + .modedb = NULL, + .modedb_len = 0, + .hfmin = 30000, + .hfmax = 70000, + .vfmin = 60, + .vfmax = 60, + .dclkmin = 6000000, + .dclkmax = 28000000, + .input = FB_DISP_RGB, + }, + .mode_screen = LCD_SCREEN_SX_N(800) | + LCD_SCREEN_SY_N(480), + .mode_horztiming = LCD_HORZTIMING_HPW_N(5) | + LCD_HORZTIMING_HND1_N(16) | + LCD_HORZTIMING_HND2_N(8), + .mode_verttiming = LCD_VERTTIMING_VPW_N(4) | + LCD_VERTTIMING_VND1_N(8) | + LCD_VERTTIMING_VND2_N(5), + .mode_clkcontrol = LCD_CLKCONTROL_PCD_N(1) | + LCD_CLKCONTROL_IV | + LCD_CLKCONTROL_IH, + .mode_pwmdiv = 0x00000000, + .mode_pwmhi = 0x00000000, + .mode_outmask = 0x00FFFFFF, + .mode_fifoctrl = 0x2f2f2f2f, + .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ + .mode_backlight = 0x00000000, + .mode_auxpll = (48/12) * 2, + .device_init = board_au1200fb_panel_init, + .device_shutdown = board_au1200fb_panel_shutdown, + 800, 800, + 480, 480, + }, }; #define NUM_PANELS (ARRAY_SIZE(known_lcd_panels)) diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 93323cc0452a..78b664921cb3 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -51,12 +51,14 @@ config SND_SOC_DB1000 of boards (DB1000/DB1500/DB1100). config SND_SOC_DB1200 - tristate "DB1200 AC97+I2S audio support" + tristate "DB1200/DB1300 Audio support" depends on SND_SOC_AU1XPSC select SND_SOC_AU1XPSC_AC97 select SND_SOC_AC97_CODEC + select SND_SOC_WM9712 select SND_SOC_AU1XPSC_I2S select SND_SOC_WM8731 help - Select this option to enable audio (AC97 or I2S) on the - Alchemy/AMD/RMI DB1200 demoboard. + Select this option to enable audio (AC97 and I2S) on the + Alchemy/AMD/RMI/NetLogic Db1200 and Db1300 evaluation boards. + If you need Db1300 touchscreen support, you definitely want to say Y. diff --git a/sound/soc/au1x/db1200.c b/sound/soc/au1x/db1200.c index 289312c14b99..ca2335afe6b6 100644 --- a/sound/soc/au1x/db1200.c +++ b/sound/soc/au1x/db1200.c @@ -1,5 +1,5 @@ /* - * DB1200 ASoC audio fabric support code. + * DB1200/DB1300 ASoC audio fabric support code. * * (c) 2008-2011 Manuel Lauss * @@ -28,6 +28,12 @@ static struct platform_device_id db1200_pids[] = { }, { .name = "db1200-i2s", .driver_data = 1, + }, { + .name = "db1300-ac97", + .driver_data = 2, + }, { + .name = "db1300-i2s", + .driver_data = 3, }, {}, }; @@ -49,6 +55,21 @@ static struct snd_soc_card db1200_ac97_machine = { .num_links = 1, }; +static struct snd_soc_dai_link db1300_ac97_dai = { + .name = "AC97", + .stream_name = "AC97 HiFi", + .codec_dai_name = "wm9712-hifi", + .cpu_dai_name = "au1xpsc_ac97.1", + .platform_name = "au1xpsc-pcm.1", + .codec_name = "wm9712-codec.1", +}; + +static struct snd_soc_card db1300_ac97_machine = { + .name = "DB1300_AC97", + .dai_link = &db1300_ac97_dai, + .num_links = 1, +}; + /*------------------------- I2S PART ---------------------------*/ static int db1200_i2s_startup(struct snd_pcm_substream *substream) @@ -98,11 +119,29 @@ static struct snd_soc_card db1200_i2s_machine = { .num_links = 1, }; +static struct snd_soc_dai_link db1300_i2s_dai = { + .name = "WM8731", + .stream_name = "WM8731 PCM", + .codec_dai_name = "wm8731-hifi", + .cpu_dai_name = "au1xpsc_i2s.2", + .platform_name = "au1xpsc-pcm.2", + .codec_name = "wm8731.0-001b", + .ops = &db1200_i2s_wm8731_ops, +}; + +static struct snd_soc_card db1300_i2s_machine = { + .name = "DB1300_I2S", + .dai_link = &db1300_i2s_dai, + .num_links = 1, +}; + /*------------------------- COMMON PART ---------------------------*/ static struct snd_soc_card *db1200_cards[] __devinitdata = { &db1200_ac97_machine, &db1200_i2s_machine, + &db1300_ac97_machine, + &db1300_i2s_machine, }; static int __devinit db1200_audio_probe(struct platform_device *pdev) @@ -147,5 +186,5 @@ module_init(db1200_audio_load); module_exit(db1200_audio_unload); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("DB1200 ASoC audio support"); +MODULE_DESCRIPTION("DB1200/DB1300 ASoC audio support"); MODULE_AUTHOR("Manuel Lauss"); From f869d42e580f6260b5c29b5ab5c5cfcfd32a0756 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:16 +0000 Subject: [PATCH 009/119] MIPS: Alchemy: Improved DB1550 support, with audio and serial busses. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2868/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 2 +- arch/mips/alchemy/devboards/Makefile | 2 +- arch/mips/alchemy/devboards/db1550.c | 506 ++++++++++++++++++ .../alchemy/devboards/db1x00/board_setup.c | 24 +- arch/mips/alchemy/devboards/db1x00/platform.c | 61 +-- arch/mips/configs/db1550_defconfig | 288 +++++++--- arch/mips/include/asm/mach-db1x00/bcsr.h | 2 +- arch/mips/include/asm/mach-db1x00/db1x00.h | 16 - sound/soc/au1x/Kconfig | 4 +- sound/soc/au1x/db1200.c | 34 +- 10 files changed, 763 insertions(+), 176 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1550.c diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index f9a13beada4a..a1b995ff517b 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -71,7 +71,7 @@ config MIPS_DB1550 bool "Alchemy DB1550 board" select ALCHEMY_GPIOINT_AU1000 select HW_HAS_PCI - select DMA_NONCOHERENT + select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 2eb75c92a583..3467ec94d8b1 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -13,4 +13,4 @@ obj-$(CONFIG_MIPS_DB1100) += db1x00/ obj-$(CONFIG_MIPS_DB1200) += db1200/ obj-$(CONFIG_MIPS_DB1300) += db1300.o obj-$(CONFIG_MIPS_DB1500) += db1x00/ -obj-$(CONFIG_MIPS_DB1550) += db1x00/ +obj-$(CONFIG_MIPS_DB1550) += db1550.o diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c new file mode 100644 index 000000000000..a4755b0570a1 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1550.c @@ -0,0 +1,506 @@ +/* + * Alchemy Db1550 board support + * + * (c) 2011 Manuel Lauss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "platform.h" + + +const char *get_system_type(void) +{ + return "DB1550"; +} + +static void __init db1550_hw_setup(void) +{ + void __iomem *base; + + alchemy_gpio_direction_output(203, 0); /* red led on */ + + /* complete SPI setup: link psc0_intclk to a 48MHz source, + * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) + */ + base = (void __iomem *)SYS_CLKSRC; + __raw_writel(__raw_readl(base) | 0x000001e0, base); + base = (void __iomem *)SYS_PINFUNC; + __raw_writel(__raw_readl(base) | 1, base); + wmb(); + + /* reset the AC97 codec now, the reset time in the psc-ac97 driver + * is apparently too short although it's ridiculous as it is. + */ + base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR); + __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE, + base + PSC_SEL_OFFSET); + __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET); + wmb(); + __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); + wmb(); + + alchemy_gpio_direction_output(202, 0); /* green led on */ +} + +void __init board_setup(void) +{ + unsigned short whoami; + + bcsr_init(DB1550_BCSR_PHYS_ADDR, + DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d" + " Board-ID %d Daughtercard ID %d\n", + (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); + + db1550_hw_setup(); +} + +/*****************************************************************************/ + +static struct mtd_partition db1550_spiflash_parts[] = { + { + .name = "spi_flash", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data db1550_spiflash_data = { + .name = "s25fl010", + .parts = db1550_spiflash_parts, + .nr_parts = ARRAY_SIZE(db1550_spiflash_parts), + .type = "m25p10", +}; + +static struct spi_board_info db1550_spi_devs[] __initdata = { + { + /* TI TMP121AIDBVR temp sensor */ + .modalias = "tmp121", + .max_speed_hz = 2400000, + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_0, + }, + { + /* Spansion S25FL001D0FMA SPI flash */ + .modalias = "m25p80", + .max_speed_hz = 2400000, + .bus_num = 0, + .chip_select = 1, + .mode = SPI_MODE_0, + .platform_data = &db1550_spiflash_data, + }, +}; + +static struct i2c_board_info db1550_i2c_devs[] __initdata = { + { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */ + { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */ + { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */ +}; + +/**********************************************************************/ + +static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; + + ioaddr &= 0xffffff00; + + if (ctrl & NAND_CLE) { + ioaddr += MEM_STNAND_CMD; + } else if (ctrl & NAND_ALE) { + ioaddr += MEM_STNAND_ADDR; + } else { + /* assume we want to r/w real data by default */ + ioaddr += MEM_STNAND_DATA; + } + this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; + if (cmd != NAND_CMD_NONE) { + __raw_writeb(cmd, this->IO_ADDR_W); + wmb(); + } +} + +static int au1550_nand_device_ready(struct mtd_info *mtd) +{ + return __raw_readl((void __iomem *)MEM_STSTAT) & 1; +} + +static const char *db1550_part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition db1550_nand_parts[] = { + { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +struct platform_nand_data db1550_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(db1550_nand_parts), + .partitions = db1550_nand_parts, + .chip_delay = 20, + .part_probe_types = db1550_part_probes, + }, + .ctrl = { + .dev_ready = au1550_nand_device_ready, + .cmd_ctrl = au1550_nand_cmd_ctrl, + }, +}; + +static struct resource db1550_nand_res[] = { + [0] = { + .start = 0x20000000, + .end = 0x200000ff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1550_nand_dev = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(db1550_nand_res), + .resource = db1550_nand_res, + .id = -1, + .dev = { + .platform_data = &db1550_nand_platdata, + } +}; + +/**********************************************************************/ + +static struct resource au1550_psc0_res[] = { + [0] = { + .start = AU1550_PSC0_PHYS_ADDR, + .end = AU1550_PSC0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC0_INT, + .end = AU1550_PSC0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC0_TX, + .end = AU1550_DSCR_CMD0_PSC0_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC0_RX, + .end = AU1550_DSCR_CMD0_PSC0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) +{ + if (cs) + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL); + else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0); +} + +static struct au1550_spi_info db1550_spi_platdata = { + .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */ + .num_chipselect = 2, + .activate_cs = db1550_spi_cs_en, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1550_spi_dev = { + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1550_spi_platdata, + }, + .name = "au1550-spi", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1550_psc0_res), + .resource = au1550_psc0_res, +}; + +/**********************************************************************/ + +static struct resource au1550_psc1_res[] = { + [0] = { + .start = AU1550_PSC1_PHYS_ADDR, + .end = AU1550_PSC1_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC1_INT, + .end = AU1550_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC1_TX, + .end = AU1550_DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC1_RX, + .end = AU1550_DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1550_ac97_dev = { + .name = "au1xpsc_ac97", + .id = 1, /* PSC ID */ + .num_resources = ARRAY_SIZE(au1550_psc1_res), + .resource = au1550_psc1_res, +}; + + +static struct resource au1550_psc2_res[] = { + [0] = { + .start = AU1550_PSC2_PHYS_ADDR, + .end = AU1550_PSC2_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC2_INT, + .end = AU1550_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC2_TX, + .end = AU1550_DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC2_RX, + .end = AU1550_DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1550_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1550_psc2_res), + .resource = au1550_psc2_res, +}; + +/**********************************************************************/ + +static struct resource au1550_psc3_res[] = { + [0] = { + .start = AU1550_PSC3_PHYS_ADDR, + .end = AU1550_PSC3_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC3_INT, + .end = AU1550_PSC3_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC3_TX, + .end = AU1550_DSCR_CMD0_PSC3_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC3_RX, + .end = AU1550_DSCR_CMD0_PSC3_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1550_i2s_dev = { + .name = "au1xpsc_i2s", + .id = 3, /* PSC ID */ + .num_resources = ARRAY_SIZE(au1550_psc3_res), + .resource = au1550_psc3_res, +}; + +/**********************************************************************/ + +static struct platform_device db1550_stac_dev = { + .name = "ac97-codec", + .id = 1, /* on PSC1 */ +}; + +static struct platform_device db1550_ac97dma_dev = { + .name = "au1xpsc-pcm", + .id = 1, /* on PSC3 */ +}; + +static struct platform_device db1550_i2sdma_dev = { + .name = "au1xpsc-pcm", + .id = 3, /* on PSC3 */ +}; + +static struct platform_device db1550_sndac97_dev = { + .name = "db1550-ac97", +}; + +static struct platform_device db1550_sndi2s_dev = { + .name = "db1550-i2s", +}; + +/**********************************************************************/ + +static struct platform_device db1550_rtc_dev = { + .name = "rtc-au1xxx", + .id = -1, +}; + +/**********************************************************************/ + +static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 11) + return (pin == 1) ? AU1550_PCI_INTC : 0xff; + if (slot == 12) { + switch (pin) { + case 1: return AU1550_PCI_INTB; + case 2: return AU1550_PCI_INTC; + case 3: return AU1550_PCI_INTD; + case 4: return AU1550_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1550_PCI_INTA; + case 2: return AU1550_PCI_INTB; + case 3: return AU1550_PCI_INTC; + case 4: return AU1550_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata db1550_pci_pd = { + .board_map_irq = db1550_map_pci_irq, +}; + +static struct platform_device db1550_pci_host_dev = { + .dev.platform_data = &db1550_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +/**********************************************************************/ + +static struct platform_device *db1550_devs[] __initdata = { + &db1550_rtc_dev, + &db1550_nand_dev, + &db1550_i2c_dev, + &db1550_ac97_dev, + &db1550_spi_dev, + &db1550_i2s_dev, + &db1550_stac_dev, + &db1550_ac97dma_dev, + &db1550_i2sdma_dev, + &db1550_sndac97_dev, + &db1550_sndi2s_dev, +}; + +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +static int __init db1550_pci_init(void) +{ + return platform_device_register(&db1550_pci_host_dev); +} +arch_initcall(db1550_pci_init); + +static int __init db1550_dev_init(void) +{ + int swapped; + + irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ + irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ + irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */ + irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */ + irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ + irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ + + i2c_register_board_info(0, db1550_i2c_devs, + ARRAY_SIZE(db1550_i2c_devs)); + spi_register_board_info(db1550_spi_devs, + ARRAY_SIZE(db1550_i2c_devs)); + + /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */ + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + /* SPI/I2C use internally supplied 50MHz source */ + __raw_writel(PSC_SEL_CLK_INTCLK, + (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + __raw_writel(PSC_SEL_CLK_INTCLK, + (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1550_GPIO3_INT, AU1550_GPIO0_INT, + /*AU1550_GPIO21_INT*/0, 0, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + AU1550_GPIO5_INT, AU1550_GPIO1_INT, + /*AU1550_GPIO22_INT*/0, 0, 1); + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + db1x_register_norflash(128 << 20, 4, swapped); + + return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); +} +device_initcall(db1550_dev_init); diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 8a222b3eba32..2dbebcba0206 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -48,11 +48,6 @@ const char *get_system_type(void) void __init board_setup(void) { - unsigned long bcsr1, bcsr2; - - bcsr1 = DB1000_BCSR_PHYS_ADDR; - bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS; - #ifdef CONFIG_MIPS_DB1000 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); #endif @@ -62,15 +57,9 @@ void __init board_setup(void) #ifdef CONFIG_MIPS_DB1100 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); #endif -#ifdef CONFIG_MIPS_DB1550 - printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); - - bcsr1 = DB1550_BCSR_PHYS_ADDR; - bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS; -#endif - /* initialize board register space */ - bcsr_init(bcsr1, bcsr2); + bcsr_init(DB1000_BCSR_PHYS_ADDR, + DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); #if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) { @@ -92,14 +81,7 @@ void __init board_setup(void) static int __init db1x00_init_irq(void) { -#if defined(CONFIG_MIPS_DB1550) - irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ - irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ -#elif defined(CONFIG_MIPS_DB1500) +#if defined(CONFIG_MIPS_DB1500) irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 677414d5f5b4..67b36e8a4c98 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -34,7 +34,6 @@ struct pci_dev; * CD0/1 GPIO0/3 * STSCHG0/1 GPIO1/4 * CARD0/1 GPIO2/5 - * Db1550: 0/1, 21/22, 3/5 */ #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) @@ -46,7 +45,6 @@ struct pci_dev; #define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT #define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ #elif defined(CONFIG_MIPS_DB1100) #define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT #define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT @@ -54,7 +52,6 @@ struct pci_dev; #define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT #define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ #elif defined(CONFIG_MIPS_DB1500) #define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT #define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT @@ -62,20 +59,8 @@ struct pci_dev; #define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT #define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#elif defined(CONFIG_MIPS_DB1550) -#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT -#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT -#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT -#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT -#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#endif -#ifdef CONFIG_PCI -#ifdef CONFIG_MIPS_DB1500 -static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) { if ((slot < 12) || (slot > 13) || pin == 0) return -1; @@ -91,34 +76,6 @@ static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) } return -1; } -#endif - -#ifdef CONFIG_MIPS_DB1550 -static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 11) || (slot > 13) || pin == 0) - return -1; - if (slot == 11) - return (pin == 1) ? AU1550_PCI_INTC : 0xff; - if (slot == 12) { - switch (pin) { - case 1: return AU1550_PCI_INTB; - case 2: return AU1550_PCI_INTC; - case 3: return AU1550_PCI_INTD; - case 4: return AU1550_PCI_INTA; - } - } - if (slot == 13) { - switch (pin) { - case 1: return AU1550_PCI_INTA; - case 2: return AU1550_PCI_INTB; - case 3: return AU1550_PCI_INTC; - case 4: return AU1550_PCI_INTD; - } - } - return -1; -} -#endif static struct resource alchemy_pci_host_res[] = { [0] = { @@ -128,24 +85,24 @@ static struct resource alchemy_pci_host_res[] = { }, }; -static struct alchemy_pci_platdata db1xxx_pci_pd = { - .board_map_irq = db1xxx_map_pci_irq, +static struct alchemy_pci_platdata db1500_pci_pd = { + .board_map_irq = db1500_map_pci_irq, }; -static struct platform_device db1xxx_pci_host_dev = { - .dev.platform_data = &db1xxx_pci_pd, +static struct platform_device db1500_pci_host_dev = { + .dev.platform_data = &db1500_pci_pd, .name = "alchemy-pci", .id = 0, .num_resources = ARRAY_SIZE(alchemy_pci_host_res), .resource = alchemy_pci_host_res, }; -static int __init db15x0_pci_init(void) +static int __init db1500_pci_init(void) { - return platform_device_register(&db1xxx_pci_host_dev); + return platform_device_register(&db1500_pci_host_dev); } /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ -arch_initcall(db15x0_pci_init); +arch_initcall(db1500_pci_init); #endif #ifdef CONFIG_MIPS_DB1100 @@ -244,7 +201,7 @@ static int __init db1xxx_dev_init(void) platform_device_register(&alchemy_ac97c_dev); platform_device_register(&db1x00_audio_dev); - db1x_register_norflash(BOARD_FLASH_SIZE, 4 /* 32bit */, F_SWAPPED); + db1x_register_norflash(0x02000000, 4 /* 32bit */, F_SWAPPED); return 0; } device_initcall(db1xxx_dev_init); diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 798a553c9e80..36cda27725e7 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -1,145 +1,262 @@ +CONFIG_MIPS=y CONFIG_MIPS_ALCHEMY=y CONFIG_MIPS_DB1550=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_GPIO=y +CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set +CONFIG_HZ=100 CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="-db1550" +CONFIG_LOCALVERSION_AUTO=y CONFIG_KERNEL_LZMA=y +CONFIG_DEFAULT_HOSTNAME="db1550" +CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_FHANDLE=y +CONFIG_AUDIT=y CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" CONFIG_PCI=y CONFIG_PCCARD=y -# CONFIG_CARDBUS is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_MISC=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y CONFIG_PM_RUNTIME=y +CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_XFRM=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_INET_TUNNEL=y +CONFIG_INET_LRO=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_DNS_RESOLVER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_AU1550=y -CONFIG_BLK_DEV_UB=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set -CONFIG_IDE_TASK_IOCTL=y -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -CONFIG_BLK_DEV_HPT366=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MISC_DEVICES=y +CONFIG_EEPROM_AT24=y +CONFIG_SCSI_MOD=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_ATA=y +CONFIG_ATA_SFF=y +CONFIG_ATA_BMDMA=y +CONFIG_PATA_HPT37X=y +CONFIG_PATA_PCMCIA=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_NET_ETHERNET=y CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=y +CONFIG_PCMCIA_PCNET=y +CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_DEVKMEM=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_DEVPORT=y CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set CONFIG_I2C_AU1550=y CONFIG_SPI=y +CONFIG_SPI_MASTER=y CONFIG_SPI_AU1550=y -# CONFIG_HWMON is not set -# CONFIG_VGA_ARB is not set -# CONFIG_VGA_CONSOLE is not set +CONFIG_SPI_BITBANG=y +CONFIG_HWMON=y +CONFIG_SENSORS_ADM1025=y +CONFIG_SENSORS_LM70=y +CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y CONFIG_SND=y -CONFIG_SND_HRTIMER=y -CONFIG_SND_DYNAMIC_MINORS=y -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_PCI is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_MIPS is not set -# CONFIG_SND_PCMCIA is not set +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_AU1XPSC=y -# CONFIG_HID_SUPPORT is not set +CONFIG_SND_SOC_AU1XPSC_I2S=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +CONFIG_SND_SOC_DB1200=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_SND_SOC_WM8731=y +CONFIG_SND_SOC_WM9712=y +CONFIG_AC97_BUS=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y -# CONFIG_JFFS2_FS_POSIX_ACL is not set -# CONFIG_JFFS2_FS_SECURITY is not set CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_RUBIN=y +CONFIG_JFFS2_CMODE_PRIORITY=y CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=y CONFIG_ROOT_NFS=y +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_USE_NEW_IDMAPPER=y +CONFIG_NFSD=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_852=y @@ -148,10 +265,21 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_FRAME_WARN=1024 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="noirqdebug console=ttyS0,115200 root=/dev/sda1 rootfstype=ext4" CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_BITREVERSE=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_BCH=y +CONFIG_NLATTR=y diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 0ef630071304..bb9fc23d853a 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -163,7 +163,7 @@ enum bcsr_whoami_boards { #define BCSR_BOARD_GPIO200RST 0x0400 #define BCSR_BOARD_PCICLKOUT 0x0800 #define BCSR_BOARD_PCICFG 0x1000 -#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ +#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */ #define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ #define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index a5affb0568ef..51f1ebf0df9a 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -29,22 +29,6 @@ #include -#ifdef CONFIG_MIPS_DB1550 - -#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX - -#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR -#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR -#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR -#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR - -#define NAND_PHYS_ADDR 0x20000000 - -#endif - /* * NAND defines * diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 78b664921cb3..a56104040e83 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -51,7 +51,7 @@ config SND_SOC_DB1000 of boards (DB1000/DB1500/DB1100). config SND_SOC_DB1200 - tristate "DB1200/DB1300 Audio support" + tristate "DB1200/DB1300/DB1550 Audio support" depends on SND_SOC_AU1XPSC select SND_SOC_AU1XPSC_AC97 select SND_SOC_AC97_CODEC @@ -60,5 +60,5 @@ config SND_SOC_DB1200 select SND_SOC_WM8731 help Select this option to enable audio (AC97 and I2S) on the - Alchemy/AMD/RMI/NetLogic Db1200 and Db1300 evaluation boards. + Alchemy/AMD/RMI/NetLogic Db1200, Db1550 and Db1300 evaluation boards. If you need Db1300 touchscreen support, you definitely want to say Y. diff --git a/sound/soc/au1x/db1200.c b/sound/soc/au1x/db1200.c index ca2335afe6b6..44ad11827364 100644 --- a/sound/soc/au1x/db1200.c +++ b/sound/soc/au1x/db1200.c @@ -1,5 +1,5 @@ /* - * DB1200/DB1300 ASoC audio fabric support code. + * DB1200/DB1300/DB1550 ASoC audio fabric support code. * * (c) 2008-2011 Manuel Lauss * @@ -34,6 +34,12 @@ static struct platform_device_id db1200_pids[] = { }, { .name = "db1300-i2s", .driver_data = 3, + }, { + .name = "db1550-ac97", + .driver_data = 4, + }, { + .name = "db1550-i2s", + .driver_data = 5, }, {}, }; @@ -70,6 +76,12 @@ static struct snd_soc_card db1300_ac97_machine = { .num_links = 1, }; +static struct snd_soc_card db1550_ac97_machine = { + .name = "DB1550_AC97", + .dai_link = &db1200_ac97_dai, + .num_links = 1, +}; + /*------------------------- I2S PART ---------------------------*/ static int db1200_i2s_startup(struct snd_pcm_substream *substream) @@ -135,6 +147,22 @@ static struct snd_soc_card db1300_i2s_machine = { .num_links = 1, }; +static struct snd_soc_dai_link db1550_i2s_dai = { + .name = "WM8731", + .stream_name = "WM8731 PCM", + .codec_dai_name = "wm8731-hifi", + .cpu_dai_name = "au1xpsc_i2s.3", + .platform_name = "au1xpsc-pcm.3", + .codec_name = "wm8731.0-001b", + .ops = &db1200_i2s_wm8731_ops, +}; + +static struct snd_soc_card db1550_i2s_machine = { + .name = "DB1550_I2S", + .dai_link = &db1550_i2s_dai, + .num_links = 1, +}; + /*------------------------- COMMON PART ---------------------------*/ static struct snd_soc_card *db1200_cards[] __devinitdata = { @@ -142,6 +170,8 @@ static struct snd_soc_card *db1200_cards[] __devinitdata = { &db1200_i2s_machine, &db1300_ac97_machine, &db1300_i2s_machine, + &db1550_ac97_machine, + &db1550_i2s_machine, }; static int __devinit db1200_audio_probe(struct platform_device *pdev) @@ -186,5 +216,5 @@ module_init(db1200_audio_load); module_exit(db1200_audio_unload); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("DB1200/DB1300 ASoC audio support"); +MODULE_DESCRIPTION("DB1200/DB1300/DB1550 ASoC audio support"); MODULE_AUTHOR("Manuel Lauss"); From 8e026910fcd46c3cfcdf5cff7ebba013bb8ec85c Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:21 +0000 Subject: [PATCH 010/119] MIPS: Alchemy: merge GPR/MTX-1/XXS1500 board code into single files Most of these files are have more comments than real code; merge them all into single board-.c files. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2869/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Makefile | 3 + arch/mips/alchemy/Platform | 8 +- .../alchemy/{gpr/platform.c => board-gpr.c} | 81 ++++++++- .../{mtx-1/platform.c => board-mtx1.c} | 93 ++++++++++- arch/mips/alchemy/board-xxs1500.c | 154 ++++++++++++++++++ arch/mips/alchemy/gpr/Makefile | 8 - arch/mips/alchemy/gpr/board_setup.c | 75 --------- arch/mips/alchemy/gpr/init.c | 63 ------- arch/mips/alchemy/mtx-1/Makefile | 9 - arch/mips/alchemy/mtx-1/board_setup.c | 94 ----------- arch/mips/alchemy/mtx-1/init.c | 66 -------- arch/mips/alchemy/xxs1500/Makefile | 8 - arch/mips/alchemy/xxs1500/board_setup.c | 93 ----------- arch/mips/alchemy/xxs1500/init.c | 63 ------- arch/mips/alchemy/xxs1500/platform.c | 63 ------- 15 files changed, 326 insertions(+), 555 deletions(-) create mode 100644 arch/mips/alchemy/Makefile rename arch/mips/alchemy/{gpr/platform.c => board-gpr.c} (75%) rename arch/mips/alchemy/{mtx-1/platform.c => board-mtx1.c} (71%) create mode 100644 arch/mips/alchemy/board-xxs1500.c delete mode 100644 arch/mips/alchemy/gpr/Makefile delete mode 100644 arch/mips/alchemy/gpr/board_setup.c delete mode 100644 arch/mips/alchemy/gpr/init.c delete mode 100644 arch/mips/alchemy/mtx-1/Makefile delete mode 100644 arch/mips/alchemy/mtx-1/board_setup.c delete mode 100644 arch/mips/alchemy/mtx-1/init.c delete mode 100644 arch/mips/alchemy/xxs1500/Makefile delete mode 100644 arch/mips/alchemy/xxs1500/board_setup.c delete mode 100644 arch/mips/alchemy/xxs1500/init.c delete mode 100644 arch/mips/alchemy/xxs1500/platform.c diff --git a/arch/mips/alchemy/Makefile b/arch/mips/alchemy/Makefile new file mode 100644 index 000000000000..aac3b179bbc0 --- /dev/null +++ b/arch/mips/alchemy/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_MIPS_GPR) += board-gpr.o +obj-$(CONFIG_MIPS_MTX1) += board-mtx1.o +obj-$(CONFIG_MIPS_XXS1500) += board-xxs1500.o diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 4d13e21eaf83..c032f5b5f889 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -75,21 +75,21 @@ cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 # -# 4G-Systems eval board +# 4G-Systems MTX-1 "MeshCube" wireless router # -platform-$(CONFIG_MIPS_MTX1) += alchemy/mtx-1/ +platform-$(CONFIG_MIPS_MTX1) += alchemy/ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 # # MyCable eval board # -platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/ +platform-$(CONFIG_MIPS_XXS1500) += alchemy/ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 # # Trapeze ITS GRP board # -platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/ +platform-$(CONFIG_MIPS_GPR) += alchemy/ load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 # boards can specify their own in one of their include dirs. diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/board-gpr.c similarity index 75% rename from arch/mips/alchemy/gpr/platform.c rename to arch/mips/alchemy/board-gpr.c index 982ce85db60d..ba3259086b9d 100644 --- a/arch/mips/alchemy/gpr/platform.c +++ b/arch/mips/alchemy/board-gpr.c @@ -1,5 +1,5 @@ /* - * GPR board platform device registration + * GPR board platform device registration (Au1550) * * Copyright (C) 2010 Wolfgang Grandegger * @@ -18,16 +18,89 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include +#include +#include #include +#include #include #include #include #include #include #include - +#include +#include #include +#include + +const char *get_system_type(void) +{ + return "GPR"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +} + +static void gpr_reset(char *c) +{ + /* switch System-LED to orange (red# and green# on) */ + alchemy_gpio_direction_output(4, 0); + alchemy_gpio_direction_output(5, 0); + + /* trigger watchdog to reset board in 200ms */ + printk(KERN_EMERG "Triggering watchdog soft reset...\n"); + raw_local_irq_disable(); + alchemy_gpio_direction_output(1, 0); + udelay(1); + alchemy_gpio_set_value(1, 1); + while (1) + cpu_wait(); +} + +static void gpr_power_off(void) +{ + while (1) + cpu_wait(); +} + +void __init board_setup(void) +{ + printk(KERN_INFO "Trapeze ITS GPR board\n"); + + pm_power_off = gpr_power_off; + _machine_halt = gpr_power_off; + _machine_restart = gpr_reset; + + /* Enable UART1/3 */ + alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); + alchemy_uart_enable(AU1000_UART1_PHYS_ADDR); + + /* Take away Reset of UMTS-card */ + alchemy_gpio_direction_output(215, 1); +} /* * Watchdog @@ -152,7 +225,7 @@ static struct i2c_gpio_platform_data gpr_i2c_data = { .scl_is_open_drain = 1, .udelay = 2, /* ~100 kHz */ .timeout = HZ, - }; +}; static struct platform_device gpr_i2c_device = { .name = "i2c-gpio", @@ -184,7 +257,7 @@ static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) else if ((slot == 0) && (pin == 2)) return AU1550_PCI_INTB; - return -1; + return 0xff; } static struct alchemy_pci_platdata gpr_pci_pd = { diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/board-mtx1.c similarity index 71% rename from arch/mips/alchemy/mtx-1/platform.c rename to arch/mips/alchemy/board-mtx1.c index cc47b6868ca3..295f1a95f745 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/board-mtx1.c @@ -1,5 +1,5 @@ /* - * MTX-1 platform devices registration + * MTX-1 platform devices registration (Au1500) * * Copyright (C) 2007-2009, Florian Fainelli * @@ -19,6 +19,8 @@ */ #include +#include +#include #include #include #include @@ -27,8 +29,85 @@ #include #include #include - +#include +#include +#include #include +#include + +const char *get_system_type(void) +{ + return "MTX-1"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +} + +static void mtx1_reset(char *c) +{ + /* Jump to the reset vector */ + __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); +} + +static void mtx1_power_off(void) +{ + while (1) + asm volatile ( + " .set mips32 \n" + " wait \n" + " .set mips0 \n"); +} + +void __init board_setup(void) +{ +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + /* Enable USB power switch */ + alchemy_gpio_direction_output(204, 0); +#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ + + /* Initialize sys_pinfunc */ + au_writel(SYS_PF_NI2, SYS_PINFUNC); + + /* Initialize GPIO */ + au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR); + alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ + alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ + alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ + alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ + + /* Enable LED and set it to green */ + alchemy_gpio_direction_output(211, 1); /* green on */ + alchemy_gpio_direction_output(212, 0); /* red off */ + + pm_power_off = mtx1_power_off; + _machine_halt = mtx1_power_off; + _machine_restart = mtx1_reset; + + printk(KERN_INFO "4G Systems MTX-1 Board\n"); +} + +/******************************************************************************/ static struct gpio_keys_button mtx1_gpio_button[] = { { @@ -195,7 +274,6 @@ static struct platform_device mtx1_pci_host = { .resource = alchemy_pci_host_res, }; - static struct __initdata platform_device * mtx1_devs[] = { &mtx1_pci_host, &mtx1_gpio_leds, @@ -206,13 +284,19 @@ static struct __initdata platform_device * mtx1_devs[] = { static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = { .phy_search_highest_addr = 1, - .phy1_search_mac0 = 1, + .phy1_search_mac0 = 1, }; static int __init mtx1_register_devices(void) { int rc; + irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); + au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata); rc = gpio_request(mtx1_gpio_button[0].gpio, @@ -226,5 +310,4 @@ static int __init mtx1_register_devices(void) out: return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); } - arch_initcall(mtx1_register_devices); diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c new file mode 100644 index 000000000000..bd5513650293 --- /dev/null +++ b/arch/mips/alchemy/board-xxs1500.c @@ -0,0 +1,154 @@ +/* + * BRIEF MODULE DESCRIPTION + * MyCable XXS1500 board support + * + * Copyright 2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const char *get_system_type(void) +{ + return "XXS1500"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) + memsize = 0x04000000; + + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +} + +static void xxs1500_reset(char *c) +{ + /* Jump to the reset vector */ + __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); +} + +static void xxs1500_power_off(void) +{ + while (1) + asm volatile ( + " .set mips32 \n" + " wait \n" + " .set mips0 \n"); +} + +void __init board_setup(void) +{ + u32 pin_func; + + pm_power_off = xxs1500_power_off; + _machine_halt = xxs1500_power_off; + _machine_restart = xxs1500_reset; + + alchemy_gpio1_input_enable(); + alchemy_gpio2_enable(); + + /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ + pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; + pin_func |= SYS_PF_UR3; + au_writel(pin_func, SYS_PINFUNC); + + /* Enable UART */ + alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); + /* Enable DTR (MCR bit 0) = USB power up */ + __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); + wmb(); +} + +/******************************************************************************/ + +static struct resource xxs1500_pcmcia_res[] = { + { + .name = "pcmcia-io", + .flags = IORESOURCE_MEM, + .start = AU1000_PCMCIA_IO_PHYS_ADDR, + .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, + }, + { + .name = "pcmcia-attr", + .flags = IORESOURCE_MEM, + .start = AU1000_PCMCIA_ATTR_PHYS_ADDR, + .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + }, + { + .name = "pcmcia-mem", + .flags = IORESOURCE_MEM, + .start = AU1000_PCMCIA_MEM_PHYS_ADDR, + .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + }, +}; + +static struct platform_device xxs1500_pcmcia_dev = { + .name = "xxs1500_pcmcia", + .id = -1, + .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res), + .resource = xxs1500_pcmcia_res, +}; + +static struct platform_device *xxs1500_devs[] __initdata = { + &xxs1500_pcmcia_dev, +}; + +static int __init xxs1500_dev_init(void) +{ + irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO207_INT, IRQ_TYPE_LEVEL_LOW); + + irq_set_irq_type(AU1500_GPIO0_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO1_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO2_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO4_INT, IRQ_TYPE_LEVEL_LOW); /* CF irq */ + irq_set_irq_type(AU1500_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); + + return platform_add_devices(xxs1500_devs, + ARRAY_SIZE(xxs1500_devs)); +} +device_initcall(xxs1500_dev_init); diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile deleted file mode 100644 index cb73fe256dce..000000000000 --- a/arch/mips/alchemy/gpr/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2003 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# -# Makefile for Trapeze ITS GPR board. -# - -obj-y += board_setup.o init.o platform.o diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c deleted file mode 100644 index dea45c78fdcd..000000000000 --- a/arch/mips/alchemy/gpr/board_setup.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2010 Wolfgang Grandegger - * - * Copyright 2000-2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include - -static void gpr_reset(char *c) -{ - /* switch System-LED to orange (red# and green# on) */ - alchemy_gpio_direction_output(4, 0); - alchemy_gpio_direction_output(5, 0); - - /* trigger watchdog to reset board in 200ms */ - printk(KERN_EMERG "Triggering watchdog soft reset...\n"); - raw_local_irq_disable(); - alchemy_gpio_direction_output(1, 0); - udelay(1); - alchemy_gpio_set_value(1, 1); - while (1) - cpu_wait(); -} - -static void gpr_power_off(void) -{ - while (1) - cpu_wait(); -} - -void __init board_setup(void) -{ - printk(KERN_INFO "Trapeze ITS GPR board\n"); - - pm_power_off = gpr_power_off; - _machine_halt = gpr_power_off; - _machine_restart = gpr_reset; - - /* Enable UART1/3 */ - alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); - alchemy_uart_enable(AU1000_UART1_PHYS_ADDR); - - /* Take away Reset of UMTS-card */ - alchemy_gpio_direction_output(215, 1); -} diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c deleted file mode 100644 index 229aafae680c..000000000000 --- a/arch/mips/alchemy/gpr/init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2010 Wolfgang Grandegger - * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include - -#include -#include - -#include - -const char *get_system_type(void) -{ - return "GPR"; -} - -void __init prom_init(void) -{ - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - - prom_init_cmdline(); - - memsize_str = prom_getenv("memsize"); - if (!memsize_str) - memsize = 0x04000000; - else - strict_strtoul(memsize_str, 0, &memsize); - add_memory_region(0, memsize, BOOT_MEM_RAM); -} - -void prom_putchar(unsigned char c) -{ - alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -} diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile deleted file mode 100644 index 81b540ceaf88..000000000000 --- a/arch/mips/alchemy/mtx-1/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright 2003 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# Bruno Randolf -# -# Makefile for 4G Systems MTX-1 board. -# - -obj-y += init.o board_setup.o platform.o diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c deleted file mode 100644 index 851a5ab4c8f2..000000000000 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * 4G Systems MTX-1 board setup. - * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * Bruno Randolf - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include - -#include -#include - -#include - -static void mtx1_reset(char *c) -{ - /* Jump to the reset vector */ - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -static void mtx1_power_off(void) -{ - while (1) - asm volatile ( - " .set mips32 \n" - " wait \n" - " .set mips0 \n"); -} - -void __init board_setup(void) -{ -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - /* Enable USB power switch */ - alchemy_gpio_direction_output(204, 0); -#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ - - /* Initialize sys_pinfunc */ - au_writel(SYS_PF_NI2, SYS_PINFUNC); - - /* Initialize GPIO */ - au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR); - alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ - alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ - alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ - alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ - - /* Enable LED and set it to green */ - alchemy_gpio_direction_output(211, 1); /* green on */ - alchemy_gpio_direction_output(212, 0); /* red off */ - - pm_power_off = mtx1_power_off; - _machine_halt = mtx1_power_off; - _machine_restart = mtx1_reset; - - printk(KERN_INFO "4G Systems MTX-1 Board\n"); -} - -static int __init mtx1_init_irq(void) -{ - irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); - irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); - - return 0; -} -arch_initcall(mtx1_init_irq); diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c deleted file mode 100644 index 2e81cc7f3422..000000000000 --- a/arch/mips/alchemy/mtx-1/init.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * 4G Systems MTX-1 board setup - * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * Bruno Randolf - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include - -#include -#include - -#include - -const char *get_system_type(void) -{ - return "MTX-1"; -} - -void __init prom_init(void) -{ - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - - prom_init_cmdline(); - - memsize_str = prom_getenv("memsize"); - if (!memsize_str) - memsize = 0x04000000; - else - strict_strtoul(memsize_str, 0, &memsize); - add_memory_region(0, memsize, BOOT_MEM_RAM); -} - -void prom_putchar(unsigned char c) -{ - alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -} diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile deleted file mode 100644 index 91defcf4f335..000000000000 --- a/arch/mips/alchemy/xxs1500/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2003 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# -# Makefile for MyCable XXS1500 board. -# - -obj-y += init.o board_setup.o platform.o diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c deleted file mode 100644 index 3fa83f72e014..000000000000 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2000-2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include - -static void xxs1500_reset(char *c) -{ - /* Jump to the reset vector */ - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -static void xxs1500_power_off(void) -{ - while (1) - asm volatile ( - " .set mips32 \n" - " wait \n" - " .set mips0 \n"); -} - -void __init board_setup(void) -{ - u32 pin_func; - - pm_power_off = xxs1500_power_off; - _machine_halt = xxs1500_power_off; - _machine_restart = xxs1500_reset; - - alchemy_gpio1_input_enable(); - alchemy_gpio2_enable(); - - /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ - pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; - pin_func |= SYS_PF_UR3; - au_writel(pin_func, SYS_PINFUNC); - - /* Enable UART */ - alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); - /* Enable DTR (MCR bit 0) = USB power up */ - __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); - wmb(); -} - -static int __init xxs1500_init_irq(void) -{ - irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); - irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); - - irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ - irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); - - return 0; -} -arch_initcall(xxs1500_init_irq); diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c deleted file mode 100644 index 0ee02cfa989d..000000000000 --- a/arch/mips/alchemy/xxs1500/init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * XXS1500 board setup - * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include - -#include -#include - -#include - -const char *get_system_type(void) -{ - return "XXS1500"; -} - -void __init prom_init(void) -{ - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - - prom_init_cmdline(); - - memsize_str = prom_getenv("memsize"); - if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) - memsize = 0x04000000; - - add_memory_region(0, memsize, BOOT_MEM_RAM); -} - -void prom_putchar(unsigned char c) -{ - alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -} diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c deleted file mode 100644 index 06a3a459b8aa..000000000000 --- a/arch/mips/alchemy/xxs1500/platform.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * XXS1500 board platform device registration - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -#include - -static struct resource xxs1500_pcmcia_res[] = { - { - .name = "pcmcia-io", - .flags = IORESOURCE_MEM, - .start = AU1000_PCMCIA_IO_PHYS_ADDR, - .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, - }, - { - .name = "pcmcia-attr", - .flags = IORESOURCE_MEM, - .start = AU1000_PCMCIA_ATTR_PHYS_ADDR, - .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - }, - { - .name = "pcmcia-mem", - .flags = IORESOURCE_MEM, - .start = AU1000_PCMCIA_MEM_PHYS_ADDR, - .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - }, -}; - -static struct platform_device xxs1500_pcmcia_dev = { - .name = "xxs1500_pcmcia", - .id = -1, - .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res), - .resource = xxs1500_pcmcia_res, -}; - -static struct platform_device *xxs1500_devs[] __initdata = { - &xxs1500_pcmcia_dev, -}; - -static int __init xxs1500_dev_init(void) -{ - return platform_add_devices(xxs1500_devs, - ARRAY_SIZE(xxs1500_devs)); -} -device_initcall(xxs1500_dev_init); From 7c4b24da07d99b5473de7cc7ba3f67d85b889bc0 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:21 +0000 Subject: [PATCH 011/119] MIPS: Alchemy: merge devboard code into single per-board files. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2884/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/Makefile | 16 +- .../devboards/{db1200/platform.c => db1200.c} | 95 ++++++++-- arch/mips/alchemy/devboards/db1200/Makefile | 1 - arch/mips/alchemy/devboards/db1200/setup.c | 81 -------- .../devboards/{db1x00/platform.c => db1x00.c} | 63 ++++++- arch/mips/alchemy/devboards/db1x00/Makefile | 8 - .../alchemy/devboards/db1x00/board_setup.c | 108 ----------- .../{pb1100/board_setup.c => pb1100.c} | 92 ++++++--- arch/mips/alchemy/devboards/pb1100/Makefile | 8 - arch/mips/alchemy/devboards/pb1100/platform.c | 77 -------- .../devboards/{pb1200/platform.c => pb1200.c} | 135 +++++++++++++- arch/mips/alchemy/devboards/pb1200/Makefile | 5 - .../alchemy/devboards/pb1200/board_setup.c | 174 ------------------ .../{pb1500/board_setup.c => pb1500.c} | 113 +++++++++--- arch/mips/alchemy/devboards/pb1500/Makefile | 8 - arch/mips/alchemy/devboards/pb1500/platform.c | 94 ---------- .../devboards/{pb1550/platform.c => pb1550.c} | 46 ++++- arch/mips/alchemy/devboards/pb1550/Makefile | 8 - .../alchemy/devboards/pb1550/board_setup.c | 80 -------- 19 files changed, 464 insertions(+), 748 deletions(-) rename arch/mips/alchemy/devboards/{db1200/platform.c => db1200.c} (85%) delete mode 100644 arch/mips/alchemy/devboards/db1200/Makefile delete mode 100644 arch/mips/alchemy/devboards/db1200/setup.c rename arch/mips/alchemy/devboards/{db1x00/platform.c => db1x00.c} (77%) delete mode 100644 arch/mips/alchemy/devboards/db1x00/Makefile delete mode 100644 arch/mips/alchemy/devboards/db1x00/board_setup.c rename arch/mips/alchemy/devboards/{pb1100/board_setup.c => pb1100.c} (55%) delete mode 100644 arch/mips/alchemy/devboards/pb1100/Makefile delete mode 100644 arch/mips/alchemy/devboards/pb1100/platform.c rename arch/mips/alchemy/devboards/{pb1200/platform.c => pb1200.c} (70%) delete mode 100644 arch/mips/alchemy/devboards/pb1200/Makefile delete mode 100644 arch/mips/alchemy/devboards/pb1200/board_setup.c rename arch/mips/alchemy/devboards/{pb1500/board_setup.c => pb1500.c} (51%) delete mode 100644 arch/mips/alchemy/devboards/pb1500/Makefile delete mode 100644 arch/mips/alchemy/devboards/pb1500/platform.c rename arch/mips/alchemy/devboards/{pb1550/platform.c => pb1550.c} (78%) delete mode 100644 arch/mips/alchemy/devboards/pb1550/Makefile delete mode 100644 arch/mips/alchemy/devboards/pb1550/board_setup.c diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 3467ec94d8b1..f5628523c694 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -4,13 +4,13 @@ obj-y += prom.o bcsr.o platform.o obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_MIPS_PB1100) += pb1100/ -obj-$(CONFIG_MIPS_PB1200) += pb1200/ -obj-$(CONFIG_MIPS_PB1500) += pb1500/ -obj-$(CONFIG_MIPS_PB1550) += pb1550/ -obj-$(CONFIG_MIPS_DB1000) += db1x00/ -obj-$(CONFIG_MIPS_DB1100) += db1x00/ -obj-$(CONFIG_MIPS_DB1200) += db1200/ +obj-$(CONFIG_MIPS_PB1100) += pb1100.o +obj-$(CONFIG_MIPS_PB1200) += pb1200.o +obj-$(CONFIG_MIPS_PB1500) += pb1500.o +obj-$(CONFIG_MIPS_PB1550) += pb1550.o +obj-$(CONFIG_MIPS_DB1000) += db1x00.o +obj-$(CONFIG_MIPS_DB1100) += db1x00.o +obj-$(CONFIG_MIPS_DB1200) += db1200.o obj-$(CONFIG_MIPS_DB1300) += db1300.o -obj-$(CONFIG_MIPS_DB1500) += db1x00/ +obj-$(CONFIG_MIPS_DB1500) += db1x00.o obj-$(CONFIG_MIPS_DB1550) += db1550.o diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200.c similarity index 85% rename from arch/mips/alchemy/devboards/db1200/platform.c rename to arch/mips/alchemy/devboards/db1200.c index c61867c93c4a..43f5f1be9d68 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -1,7 +1,7 @@ /* * DBAu1200 board platform device registration * - * Copyright (C) 2008-2009 Manuel Lauss + * Copyright (C) 2008-2011 Manuel Lauss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -33,14 +34,64 @@ #include #include #include - +#include #include #include #include #include #include -#include "../platform.h" +#include "platform.h" + + +const char *get_system_type(void) +{ + return "DB1200"; +} + +void __init board_setup(void) +{ + unsigned long freq0, clksrc, div, pfc; + unsigned short whoami; + + bcsr_init(DB1200_BCSR_PHYS_ADDR, + DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d" + " Board-ID %d Daughtercard ID %d\n", + (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); + + /* SMBus/SPI on PSC0, Audio on PSC1 */ + pfc = __raw_readl((void __iomem *)SYS_PINFUNC); + pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); + pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); + pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ + __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); + wmb(); + + /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from + * CPU clock; all other clock generators off/unused. + */ + div = (get_au1x00_speed() + 25000000) / 50000000; + if (div & 1) + div++; + div = ((div >> 1) - 1) & 0xff; + + freq0 = div << SYS_FC_FRDIV0_BIT; + __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); + wmb(); + freq0 |= SYS_FC_FE0; /* enable F0 */ + __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); + wmb(); + + /* psc0_intclk comes 1:1 from F0 */ + clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; + __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); + wmb(); +} + +/******************************************************************************/ static struct mtd_partition db1200_spiflash_parts[] = { { @@ -78,18 +129,9 @@ static struct spi_board_info db1200_spi_devs[] __initdata = { }; static struct i2c_board_info db1200_i2c_devs[] __initdata = { - { - /* AT24C04-10 I2C eeprom */ - I2C_BOARD_INFO("24c04", 0x52), - }, - { - /* Philips NE1619 temp/voltage sensor (adm1025 drv) */ - I2C_BOARD_INFO("ne1619", 0x2d), - }, - { - /* I2S audio codec WM8731 */ - I2C_BOARD_INFO("wm8731", 0x1b), - }, + { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */ + { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ + { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */ }; /**********************************************************************/ @@ -206,7 +248,7 @@ static struct platform_device db1200_eth_dev = { static struct resource db1200_ide_res[] = { [0] = { .start = DB1200_IDE_PHYS_ADDR, - .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, + .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -221,13 +263,13 @@ static struct resource db1200_ide_res[] = { }, }; -static u64 ide_dmamask = DMA_BIT_MASK(32); +static u64 au1200_ide_dmamask = DMA_BIT_MASK(32); static struct platform_device db1200_ide_dev = { .name = "au1200-ide", .id = 0, .dev = { - .dma_mask = &ide_dmamask, + .dma_mask = &au1200_ide_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(db1200_ide_res), @@ -533,6 +575,21 @@ static int __init db1200_dev_init(void) unsigned short sw; int swapped; + /* GPIO7 is low-level triggered CPLD cascade */ + irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); + bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); + + /* insert/eject pairs: one of both is always screaming. To avoid + * issues they must not be automatically enabled when initially + * requested. + */ + irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); + i2c_register_board_info(0, db1200_i2c_devs, ARRAY_SIZE(db1200_i2c_devs)); spi_register_board_info(db1200_spi_devs, @@ -595,7 +652,7 @@ static int __init db1200_dev_init(void) /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ __raw_writel(PSC_SEL_CLK_SERCLK, - (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); db1x_register_pcmcia_socket( diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile deleted file mode 100644 index 17840a5e2738..000000000000 --- a/arch/mips/alchemy/devboards/db1200/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += setup.o platform.o diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c deleted file mode 100644 index 4a8980027ecf..000000000000 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Alchemy/AMD/RMI DB1200 board setup. - * - * Licensed under the terms outlined in the file COPYING in the root of - * this source archive. - */ - -#include -#include -#include -#include -#include -#include -#include - -const char *get_system_type(void) -{ - return "Alchemy Db1200"; -} - -void __init board_setup(void) -{ - unsigned long freq0, clksrc, div, pfc; - unsigned short whoami; - - bcsr_init(DB1200_BCSR_PHYS_ADDR, - DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); - - whoami = bcsr_read(BCSR_WHOAMI); - printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d" - " Board-ID %d Daughtercard ID %d\n", - (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); - - /* SMBus/SPI on PSC0, Audio on PSC1 */ - pfc = __raw_readl((void __iomem *)SYS_PINFUNC); - pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); - pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); - pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ - __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); - wmb(); - - /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from - * CPU clock; all other clock generators off/unused. - */ - div = (get_au1x00_speed() + 25000000) / 50000000; - if (div & 1) - div++; - div = ((div >> 1) - 1) & 0xff; - - freq0 = div << SYS_FC_FRDIV0_BIT; - __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); - wmb(); - freq0 |= SYS_FC_FE0; /* enable F0 */ - __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); - wmb(); - - /* psc0_intclk comes 1:1 from F0 */ - clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; - __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); - wmb(); -} - -static int __init db1200_arch_init(void) -{ - /* GPIO7 is low-level triggered CPLD cascade */ - irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); - bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); - - /* insert/eject pairs: one of both is always screaming. To avoid - * issues they must not be automatically enabled when initially - * requested. - */ - irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); - return 0; -} -arch_initcall(db1200_arch_init); diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00.c similarity index 77% rename from arch/mips/alchemy/devboards/db1x00/platform.c rename to arch/mips/alchemy/devboards/db1x00.c index 67b36e8a4c98..589ae2435cbe 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00.c @@ -1,7 +1,8 @@ /* - * DBAu1xxx board platform device registration + * DBAu1000/1500/1100 board support * - * Copyright (C) 2009 Manuel Lauss + * Copyright 2000, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,20 +19,61 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include #include #include -#include #include - +#include #include #include #include -#include "../platform.h" +#include +#include +#include "platform.h" struct pci_dev; +const char *get_system_type(void) +{ + return "Alchemy Db1x00"; +} + +void __init board_setup(void) +{ +#ifdef CONFIG_MIPS_DB1000 + printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1500 + printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1100 + printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); +#endif + /* initialize board register space */ + bcsr_init(DB1000_BCSR_PHYS_ADDR, + DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); + +#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) + { + u32 pin_func; + + /* Set IRFIRSEL instead of GPIO15 */ + pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; + au_writel(pin_func, SYS_PINFUNC); + /* Power off until the driver is in use */ + bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, + BCSR_RESETS_IRDA_MODE_OFF); + } +#endif + bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ + + /* Enable GPIO[31:0] inputs */ + alchemy_gpio1_input_enable(); +} + /* DB1xxx PCMCIA interrupt sources: - * CD0/1 GPIO0/3 + * CD0/1 GPIO0/3 * STSCHG0/1 GPIO1/4 * CARD0/1 GPIO2/5 */ @@ -174,6 +216,13 @@ static struct platform_device db1x00_audio_dev = { static int __init db1xxx_dev_init(void) { + irq_set_irq_type(DB1XXX_PCMCIA_CD0, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(DB1XXX_PCMCIA_CD1, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(DB1XXX_PCMCIA_CARD0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(DB1XXX_PCMCIA_CARD1, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(DB1XXX_PCMCIA_STSCHG0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(DB1XXX_PCMCIA_STSCHG1, IRQ_TYPE_LEVEL_LOW); + db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, @@ -201,7 +250,7 @@ static int __init db1xxx_dev_init(void) platform_device_register(&alchemy_ac97c_dev); platform_device_register(&db1x00_audio_dev); - db1x_register_norflash(0x02000000, 4 /* 32bit */, F_SWAPPED); + db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED); return 0; } device_initcall(db1xxx_dev_init); diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile deleted file mode 100644 index 613c0c0c8be9..000000000000 --- a/arch/mips/alchemy/devboards/db1x00/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# -# Makefile for the Alchemy Semiconductor DBAu1xx0 boards. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c deleted file mode 100644 index 2dbebcba0206..000000000000 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Alchemy Db1x00 board setup. - * - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -const char *get_system_type(void) -{ - return "Alchemy Db1x00"; -} - - -void __init board_setup(void) -{ -#ifdef CONFIG_MIPS_DB1000 - printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1500 - printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1100 - printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); -#endif - /* initialize board register space */ - bcsr_init(DB1000_BCSR_PHYS_ADDR, - DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); - -#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) - { - u32 pin_func; - - /* Set IRFIRSEL instead of GPIO15 */ - pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; - au_writel(pin_func, SYS_PINFUNC); - /* Power off until the driver is in use */ - bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, - BCSR_RESETS_IRDA_MODE_OFF); - } -#endif - bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ - - /* Enable GPIO[31:0] inputs */ - alchemy_gpio1_input_enable(); -} - -static int __init db1x00_init_irq(void) -{ -#if defined(CONFIG_MIPS_DB1500) - irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ -#elif defined(CONFIG_MIPS_DB1100) - irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ -#elif defined(CONFIG_MIPS_DB1000) - irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ -#endif - return 0; -} -arch_initcall(db1x00_init_irq); diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100.c similarity index 55% rename from arch/mips/alchemy/devboards/pb1100/board_setup.c rename to arch/mips/alchemy/devboards/pb1100.c index d108fd573aaf..cff50d05ddd4 100644 --- a/arch/mips/alchemy/devboards/pb1100/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1100.c @@ -1,42 +1,37 @@ /* - * Copyright 2002, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. + * Pb1100 board platform device registration * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright (C) 2009 Manuel Lauss * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include -#include #include - +#include +#include #include #include - #include - +#include "platform.h" const char *get_system_type(void) { - return "Alchemy Pb1100"; + return "PB1100"; } void __init board_setup(void) @@ -115,13 +110,58 @@ void __init board_setup(void) } } -static int __init pb1100_init_irq(void) +/******************************************************************************/ + +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; + +static int __init pb1100_dev_init(void) { + int swapped; + irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ + /* PCMCIA. single socket, identical to Pb1500 */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */ + /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&au1100_lcd_device); + return 0; } -arch_initcall(pb1100_init_irq); +device_initcall(pb1100_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile deleted file mode 100644 index 7e3756c83fe5..000000000000 --- a/arch/mips/alchemy/devboards/pb1100/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2001, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# -# Makefile for the Alchemy Semiconductor Pb1100 board. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c deleted file mode 100644 index 9c57c01a68c4..000000000000 --- a/arch/mips/alchemy/devboards/pb1100/platform.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Pb1100 board platform device registration - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include - -#include -#include - -#include "../platform.h" - -static struct resource au1100_lcd_resources[] = { - [0] = { - .start = AU1100_LCD_PHYS_ADDR, - .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1100_LCD_INT, - .end = AU1100_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1100_lcd_device = { - .name = "au1100-lcd", - .id = 0, - .dev = { - .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1100_lcd_resources), - .resource = au1100_lcd_resources, -}; - -static int __init pb1100_dev_init(void) -{ - int swapped; - - /* PCMCIA. single socket, identical to Pb1500 */ - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */ - /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; - db1x_register_norflash(64 * 1024 * 1024, 4, swapped); - platform_device_register(&au1100_lcd_device); - - return 0; -} -device_initcall(pb1100_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200.c similarity index 70% rename from arch/mips/alchemy/devboards/pb1200/platform.c rename to arch/mips/alchemy/devboards/pb1200.c index 54f7f7b0676e..a1b64977b471 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200.c @@ -20,17 +20,97 @@ #include #include +#include #include #include #include - #include #include #include #include #include +#include +#include "platform.h" -#include "../platform.h" + +const char *get_system_type(void) +{ + return "PB1200"; +} + +void __init board_setup(void) +{ + printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); + bcsr_init(PB1200_BCSR_PHYS_ADDR, + PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); + +#if 0 + { + u32 pin_func; + + /* + * Enable PSC1 SYNC for AC97. Normaly done in audio driver, + * but it is board specific code, so put it here. + */ + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; + au_writel(pin_func, SYS_PINFUNC); + + au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ + au_sync(); + } +#endif + +#if defined(CONFIG_I2C_AU1550) + { + u32 freq0, clksrc; + u32 pin_func; + + /* Select SMBus in CPLD */ + bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); + + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); + /* Set GPIOs correctly */ + pin_func |= 2 << 17; + au_writel(pin_func, SYS_PINFUNC); + au_sync(); + + /* The I2C driver depends on 50 MHz clock */ + freq0 = au_readl(SYS_FREQCTRL0); + au_sync(); + freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); + freq0 |= 3 << SYS_FC_FRDIV1_BIT; + /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */ + au_writel(freq0, SYS_FREQCTRL0); + au_sync(); + freq0 |= SYS_FC_FE1; + au_writel(freq0, SYS_FREQCTRL0); + au_sync(); + + clksrc = au_readl(SYS_CLKSRC); + au_sync(); + clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK); + /* Bit 22 is EXTCLK0 for PSC0 */ + clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT; + au_writel(clksrc, SYS_CLKSRC); + au_sync(); + } +#endif + + /* + * The Pb1200 development board uses external MUX for PSC0 to + * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI + */ +#ifdef CONFIG_I2C_AU1550 + bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); +#endif + au_sync(); +} + +/******************************************************************************/ static int mmc_activity; @@ -183,7 +263,7 @@ static struct platform_device pb1200_mmc1_dev = { static struct resource ide_resources[] = { [0] = { .start = IDE_PHYS_ADDR, - .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, + .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, .flags = IORESOURCE_MEM }, [1] = { @@ -198,13 +278,13 @@ static struct resource ide_resources[] = { }, }; -static u64 ide_dmamask = DMA_BIT_MASK(32); +static u64 au1200_ide_dmamask = DMA_BIT_MASK(32); static struct platform_device ide_device = { .name = "au1200-ide", .id = 0, .dev = { - .dma_mask = &ide_dmamask, + .dma_mask = &au1200_ide_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(ide_resources), @@ -310,6 +390,29 @@ static int __init board_register_devices(void) { int swapped; + /* We have a problem with CPLD rev 3. */ + if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n"); + printk(KERN_ERR "updated to latest revision. This software will\n"); + printk(KERN_ERR "not work on anything less than CPLD rev 4.\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + panic("Game over. Your score is 0."); + } + + irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); + bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); + db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, @@ -337,3 +440,25 @@ static int __init board_register_devices(void) ARRAY_SIZE(board_platform_devices)); } device_initcall(board_register_devices); + + +int board_au1200fb_panel(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile deleted file mode 100644 index 18c1bd53e4c0..000000000000 --- a/arch/mips/alchemy/devboards/pb1200/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c deleted file mode 100644 index 6d06b07c2381..000000000000 --- a/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Alchemy Pb1200/Db1200 board setup. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include - -#include -#include - -#ifdef CONFIG_MIPS_PB1200 -#include -#endif - -#ifdef CONFIG_MIPS_DB1200 -#include -#define PB1200_INT_BEGIN DB1200_INT_BEGIN -#define PB1200_INT_END DB1200_INT_END -#endif - -#include - -const char *get_system_type(void) -{ - return "Alchemy Pb1200"; -} - -void __init board_setup(void) -{ - printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); - bcsr_init(PB1200_BCSR_PHYS_ADDR, - PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); - -#if 0 - { - u32 pin_func; - - /* - * Enable PSC1 SYNC for AC97. Normaly done in audio driver, - * but it is board specific code, so put it here. - */ - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; - au_writel(pin_func, SYS_PINFUNC); - - au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ - au_sync(); - } -#endif - -#if defined(CONFIG_I2C_AU1550) - { - u32 freq0, clksrc; - u32 pin_func; - - /* Select SMBus in CPLD */ - bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); - - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); - /* Set GPIOs correctly */ - pin_func |= 2 << 17; - au_writel(pin_func, SYS_PINFUNC); - au_sync(); - - /* The I2C driver depends on 50 MHz clock */ - freq0 = au_readl(SYS_FREQCTRL0); - au_sync(); - freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); - freq0 |= 3 << SYS_FC_FRDIV1_BIT; - /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */ - au_writel(freq0, SYS_FREQCTRL0); - au_sync(); - freq0 |= SYS_FC_FE1; - au_writel(freq0, SYS_FREQCTRL0); - au_sync(); - - clksrc = au_readl(SYS_CLKSRC); - au_sync(); - clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK); - /* Bit 22 is EXTCLK0 for PSC0 */ - clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT; - au_writel(clksrc, SYS_CLKSRC); - au_sync(); - } -#endif - - /* - * The Pb1200 development board uses external MUX for PSC0 to - * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI - */ -#ifdef CONFIG_I2C_AU1550 - bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); -#endif - au_sync(); -} - -static int __init pb1200_init_irq(void) -{ - /* We have a problem with CPLD rev 3. */ - if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n"); - printk(KERN_ERR "updated to latest revision. This software will\n"); - printk(KERN_ERR "not work on anything less than CPLD rev 4.\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - panic("Game over. Your score is 0."); - } - - irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); - bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); - - return 0; -} -arch_initcall(pb1200_init_irq); - - -int board_au1200fb_panel(void) -{ - return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; -} - -int board_au1200fb_panel_init(void) -{ - /* Apply power */ - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); - /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */ - return 0; -} - -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL, 0); - /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */ - return 0; -} diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500.c similarity index 51% rename from arch/mips/alchemy/devboards/pb1500/board_setup.c rename to arch/mips/alchemy/devboards/pb1500.c index 37c1883b5ea9..e7b807b3ec51 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500.c @@ -1,41 +1,37 @@ /* - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. + * Pb1500 board support. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright (C) 2009 Manuel Lauss * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include +#include #include #include #include - +#include #include #include - #include +#include "platform.h" const char *get_system_type(void) { - return "Alchemy Pb1500"; + return "PB1500"; } void __init board_setup(void) @@ -123,17 +119,80 @@ void __init board_setup(void) } } -static int __init pb1500_init_irq(void) +/******************************************************************************/ + +static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) { - irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ - irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata pb1500_pci_pd = { + .board_map_irq = pb1500_map_pci_irq, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device pb1500_pci_host = { + .dev.platform_data = &pb1500_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +static int __init pb1500_dev_init(void) +{ + int swapped; + + irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ + irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ + irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); + /* PCMCIA. single socket, identical to Pb1100 */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */ + /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&pb1500_pci_host); + return 0; } -arch_initcall(pb1500_init_irq); +arch_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile deleted file mode 100644 index e83b151b5b63..000000000000 --- a/arch/mips/alchemy/devboards/pb1500/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2001, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# -# Makefile for the Alchemy Semiconductor Pb1500 board. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c deleted file mode 100644 index 1e52a01bac00..000000000000 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Pb1500 board platform device registration - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -#include "../platform.h" - -static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 12) || (slot > 13) || pin == 0) - return -1; - if (slot == 12) - return (pin == 1) ? AU1500_PCI_INTA : 0xff; - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - case 3: return AU1500_PCI_INTC; - case 4: return AU1500_PCI_INTD; - } - } - return -1; -} - -static struct resource alchemy_pci_host_res[] = { - [0] = { - .start = AU1500_PCI_PHYS_ADDR, - .end = AU1500_PCI_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct alchemy_pci_platdata pb1500_pci_pd = { - .board_map_irq = pb1500_map_pci_irq, - .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | - PCI_CONFIG_CH | -#if defined(__MIPSEB__) - PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, -#else - 0, -#endif -}; - -static struct platform_device pb1500_pci_host = { - .dev.platform_data = &pb1500_pci_pd, - .name = "alchemy-pci", - .id = 0, - .num_resources = ARRAY_SIZE(alchemy_pci_host_res), - .resource = alchemy_pci_host_res, -}; - -static int __init pb1500_dev_init(void) -{ - int swapped; - - /* PCMCIA. single socket, identical to Pb1100 */ - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */ - /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; - db1x_register_norflash(64 * 1024 * 1024, 4, swapped); - platform_device_register(&pb1500_pci_host); - - return 0; -} -arch_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550.c similarity index 78% rename from arch/mips/alchemy/devboards/pb1550/platform.c rename to arch/mips/alchemy/devboards/pb1550.c index a4604b8a349e..e4a00a56a20f 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550.c @@ -1,7 +1,7 @@ /* - * Pb1550 board platform device registration + * Pb1550 board support. * - * Copyright (C) 2009 Manuel Lauss + * Copyright (C) 2009-2011 Manuel Lauss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,13 +20,43 @@ #include #include +#include #include #include #include -#include +#include #include +#include "platform.h" -#include "../platform.h" +const char *get_system_type(void) +{ + return "PB1550"; +} + +void __init board_setup(void) +{ + u32 pin_func; + + bcsr_init(PB1550_BCSR_PHYS_ADDR, + PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); + + alchemy_gpio2_enable(); + + /* + * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, + * but it is board specific code, so put it here. + */ + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; + au_writel(pin_func, SYS_PINFUNC); + + bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ + + printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); +} + +/******************************************************************************/ static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) { @@ -105,6 +135,14 @@ static int __init pb1550_dev_init(void) { int swapped; + irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); + + /* enable both PCMCIA card irqs in the shared line */ + alchemy_gpio2_enable_int(201); + alchemy_gpio2_enable_int(202); + /* Pb1550, like all others, also has statuschange irqs; however they're * wired up on one of the Au1550's shared GPIO201_205 line, which also * services the PCMCIA card interrupts. So we ignore statuschange and diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile deleted file mode 100644 index 9661b6ec5dd3..000000000000 --- a/arch/mips/alchemy/devboards/pb1550/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# -# Makefile for the Alchemy Semiconductor Pb1550 board. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c deleted file mode 100644 index 0f62d1e3df24..000000000000 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Alchemy Pb1550 board setup. - * - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include - -#include -#include -#include -#include - -#include - -const char *get_system_type(void) -{ - return "Alchemy Pb1550"; -} - -void __init board_setup(void) -{ - u32 pin_func; - - bcsr_init(PB1550_BCSR_PHYS_ADDR, - PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); - - alchemy_gpio2_enable(); - - /* - * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, - * but it is board specific code, so put it here. - */ - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; - au_writel(pin_func, SYS_PINFUNC); - - bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ - - printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); -} - -static int __init pb1550_init_irq(void) -{ - irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); - - /* enable both PCMCIA card irqs in the shared line */ - alchemy_gpio2_enable_int(201); - alchemy_gpio2_enable_int(202); - - return 0; -} -arch_initcall(pb1550_init_irq); From a9b71a8f0f42efe1a21154667ca02305c950d30a Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:21 +0000 Subject: [PATCH 012/119] MIPS: Alchemy: move au1200fb global functions to platform data au1200fb calls 3 functions which have to be defined in board code. Fix this ugliness with the introduction of platform_data. Signed-off-by: Manuel Lauss Cc: linux-fbdev@vger.kernel.org To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2871/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/db1200.c | 51 ++-- arch/mips/alchemy/devboards/db1300.c | 52 ++-- arch/mips/alchemy/devboards/pb1200.c | 55 +++-- arch/mips/include/asm/mach-au1x00/au1200fb.h | 14 ++ drivers/video/au1200fb.c | 241 +++++++++---------- 5 files changed, 213 insertions(+), 200 deletions(-) create mode 100644 arch/mips/include/asm/mach-au1x00/au1200fb.h diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index 43f5f1be9d68..e2cc5f921538 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -422,6 +423,33 @@ static struct platform_device db1200_mmc0_dev = { /**********************************************************************/ +static int db1200fb_panel_index(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +static int db1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +static int db1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} + +static struct au1200fb_platdata db1200fb_pd = { + .panel_index = db1200fb_panel_index, + .panel_init = db1200fb_panel_init, + .panel_shutdown = db1200fb_panel_shutdown, +}; + static struct resource au1200_lcd_res[] = { [0] = { .start = AU1200_LCD_PHYS_ADDR, @@ -443,6 +471,7 @@ static struct platform_device au1200_lcd_dev = { .dev = { .dma_mask = &au1200_lcd_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1200fb_pd, }, .num_resources = ARRAY_SIZE(au1200_lcd_res), .resource = au1200_lcd_res, @@ -681,25 +710,3 @@ static int __init db1200_dev_init(void) return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); } device_initcall(db1200_dev_init); - -/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ -int board_au1200fb_panel(void) -{ - return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; -} - -int board_au1200fb_panel_init(void) -{ - /* Apply power */ - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); - return 0; -} - -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL, 0); - return 0; -} diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index c41788c59278..7f3dacb60ea5 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -636,6 +637,33 @@ static struct platform_device db1300_sndi2s_dev = { /**********************************************************************/ +static int db1300fb_panel_index(void) +{ + return 9; /* DB1300_800x480 */ +} + +static int db1300fb_panel_init(void) +{ + /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, + BCSR_BOARD_LCDBL); + return 0; +} + +static int db1300fb_panel_shutdown(void) +{ + /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, + BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); + return 0; +} + +static struct au1200fb_platdata db1300fb_pd = { + .panel_index = db1300fb_panel_index, + .panel_init = db1300fb_panel_init, + .panel_shutdown = db1300fb_panel_shutdown, +}; + static struct resource au1300_lcd_res[] = { [0] = { .start = AU1200_LCD_PHYS_ADDR, @@ -657,6 +685,7 @@ static struct platform_device db1300_lcd_dev = { .dev = { .dma_mask = &au1300_lcd_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1300fb_pd, }, .num_resources = ARRAY_SIZE(au1300_lcd_res), .resource = au1300_lcd_res, @@ -762,26 +791,3 @@ void __init board_setup(void) alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); } - - -/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ -int board_au1200fb_panel(void) -{ - return 9; /* DB1300_800x480 */ -} - -int board_au1200fb_panel_init(void) -{ - /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, - BCSR_BOARD_LCDBL); - return 0; -} - -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, - BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); - return 0; -} diff --git a/arch/mips/alchemy/devboards/pb1200.c b/arch/mips/alchemy/devboards/pb1200.c index a1b64977b471..a2676c95053b 100644 --- a/arch/mips/alchemy/devboards/pb1200.c +++ b/arch/mips/alchemy/devboards/pb1200.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -351,6 +352,33 @@ static struct platform_device pb1200_i2c_dev = { .resource = au1200_psc0_res, }; +static int pb1200fb_panel_index(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +static int pb1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +static int pb1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} + +static struct au1200fb_platdata pb1200fb_pd = { + .panel_index = pb1200fb_panel_index, + .panel_init = pb1200fb_panel_init, + .panel_shutdown = pb1200fb_panel_shutdown, +}; + static struct resource au1200_lcd_res[] = { [0] = { .start = AU1200_LCD_PHYS_ADDR, @@ -366,12 +394,13 @@ static struct resource au1200_lcd_res[] = { static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); -static struct platform_device au1200_lcd_dev = { +static struct platform_device pb1200_lcd_dev = { .name = "au1200-lcd", .id = 0, .dev = { .dma_mask = &au1200_lcd_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &pb1200fb_pd, }, .num_resources = ARRAY_SIZE(au1200_lcd_res), .resource = au1200_lcd_res, @@ -383,7 +412,7 @@ static struct platform_device *board_platform_devices[] __initdata = { &pb1200_i2c_dev, &pb1200_mmc0_dev, &pb1200_mmc1_dev, - &au1200_lcd_dev, + &pb1200_lcd_dev, }; static int __init board_register_devices(void) @@ -440,25 +469,3 @@ static int __init board_register_devices(void) ARRAY_SIZE(board_platform_devices)); } device_initcall(board_register_devices); - - -int board_au1200fb_panel(void) -{ - return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; -} - -int board_au1200fb_panel_init(void) -{ - /* Apply power */ - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); - return 0; -} - -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL, 0); - return 0; -} diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h new file mode 100644 index 000000000000..b3c87cc64bb9 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h @@ -0,0 +1,14 @@ +/* + * platform data for au1200fb driver. + */ + +#ifndef _AU1200FB_PLAT_H_ +#define _AU1200FB_PLAT_H_ + +struct au1200fb_platdata { + int (*panel_index)(void); + int (*panel_init)(void); + int (*panel_shutdown)(void); +}; + +#endif diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c index 6c4342f1d9b4..04e4479d5afd 100644 --- a/drivers/video/au1200fb.c +++ b/drivers/video/au1200fb.c @@ -44,6 +44,7 @@ #include #include +#include /* platform_data */ #include "au1200fb.h" #define DRIVER_NAME "au1200fb" @@ -143,6 +144,7 @@ struct au1200_lcd_iodata_t { /* Private, per-framebuffer management information (independent of the panel itself) */ struct au1200fb_device { struct fb_info *fb_info; /* FB driver info record */ + struct au1200fb_platdata *pd; int plane; unsigned char* fb_mem; /* FrameBuffer memory map */ @@ -201,9 +203,6 @@ struct window_settings { #define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01 #endif -extern int board_au1200fb_panel_init (void); -extern int board_au1200fb_panel_shutdown (void); - /* * Default window configurations */ @@ -334,8 +333,6 @@ struct panel_settings uint32 mode_toyclksrc; uint32 mode_backlight; uint32 mode_auxpll; - int (*device_init)(void); - int (*device_shutdown)(void); #define Xres min_xres #define Yres min_yres u32 min_xres; /* Minimum horizontal resolution */ @@ -385,8 +382,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 320, 320, 240, 240, }, @@ -415,8 +410,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 640, 480, 640, 480, }, @@ -445,8 +438,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 800, 800, 600, 600, }, @@ -475,8 +466,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 6, /* 72MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 1024, 1024, 768, 768, }, @@ -505,8 +494,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 10, /* 120MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 1280, 1280, 1024, 1024, }, @@ -535,8 +522,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 1024, 1024, 768, 768, }, @@ -568,8 +553,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 640, 480, 640, 480, }, @@ -601,8 +584,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 320, 320, 240, 240, }, @@ -634,8 +615,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 856, 856, 480, 480, }, @@ -670,8 +649,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = (48/12) * 2, - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 800, 800, 480, 480, }, @@ -800,7 +777,8 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane, return 0; } -static void au1200_setpanel (struct panel_settings *newpanel) +static void au1200_setpanel(struct panel_settings *newpanel, + struct au1200fb_platdata *pd) { /* * Perform global setup/init of LCD controller @@ -834,8 +812,8 @@ static void au1200_setpanel (struct panel_settings *newpanel) the controller, the clock cannot be turned off before first shutting down the controller. */ - if (panel->device_shutdown != NULL) - panel->device_shutdown(); + if (pd->panel_shutdown) + pd->panel_shutdown(); } /* Newpanel == NULL indicates a shutdown operation only */ @@ -888,7 +866,8 @@ static void au1200_setpanel (struct panel_settings *newpanel) au_sync(); /* Call init of panel */ - if (panel->device_init != NULL) panel->device_init(); + if (pd->panel_init) + pd->panel_init(); /* FIX!!!! not appropriate on panel change!!! Global setup/init */ lcd->intenable = 0; @@ -1221,6 +1200,8 @@ static int au1200fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, */ static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi) { + struct au1200fb_device *fbdev = fbi->par; + /* Short-circuit screen blanking */ if (noblanking) return 0; @@ -1230,13 +1211,13 @@ static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi) case FB_BLANK_UNBLANK: case FB_BLANK_NORMAL: /* printk("turn on panel\n"); */ - au1200_setpanel(panel); + au1200_setpanel(panel, fbdev->pd); break; case FB_BLANK_VSYNC_SUSPEND: case FB_BLANK_HSYNC_SUSPEND: case FB_BLANK_POWERDOWN: /* printk("turn off panel\n"); */ - au1200_setpanel(NULL); + au1200_setpanel(NULL, fbdev->pd); break; default: break; @@ -1464,6 +1445,7 @@ static void get_window(unsigned int plane, static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) { + struct au1200fb_device *fbdev = info->par; int plane; int val; @@ -1508,7 +1490,7 @@ static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, struct panel_settings *newpanel; panel_index = iodata.global.panel_choice; newpanel = &known_lcd_panels[panel_index]; - au1200_setpanel(newpanel); + au1200_setpanel(newpanel, fbdev->pd); } break; @@ -1624,22 +1606,102 @@ static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev) /*-------------------------------------------------------------------------*/ -/* AU1200 LCD controller device driver */ +static int au1200fb_setup(struct au1200fb_platdata *pd) +{ + char *options = NULL; + char *this_opt, *endptr; + int num_panels = ARRAY_SIZE(known_lcd_panels); + int panel_idx = -1; + + fb_get_options(DRIVER_NAME, &options); + + if (!options) + goto out; + + while ((this_opt = strsep(&options, ",")) != NULL) { + /* Panel option - can be panel name, + * "bs" for board-switch, or number/index */ + if (!strncmp(this_opt, "panel:", 6)) { + int i; + long int li; + char *endptr; + this_opt += 6; + /* First check for index, which allows + * to short circuit this mess */ + li = simple_strtol(this_opt, &endptr, 0); + if (*endptr == '\0') + panel_idx = (int)li; + else if (strcmp(this_opt, "bs") == 0) + panel_idx = pd->panel_index(); + else { + for (i = 0; i < num_panels; i++) { + if (!strcmp(this_opt, + known_lcd_panels[i].name)) { + panel_idx = i; + break; + } + } + } + if ((panel_idx < 0) || (panel_idx >= num_panels)) + print_warn("Panel %s not supported!", this_opt); + else + panel_index = panel_idx; + + } else if (strncmp(this_opt, "nohwcursor", 10) == 0) + nohwcursor = 1; + else if (strncmp(this_opt, "devices:", 8) == 0) { + this_opt += 8; + device_count = simple_strtol(this_opt, &endptr, 0); + if ((device_count < 0) || + (device_count > MAX_DEVICE_COUNT)) + device_count = MAX_DEVICE_COUNT; + } else if (strncmp(this_opt, "wincfg:", 7) == 0) { + this_opt += 7; + window_index = simple_strtol(this_opt, &endptr, 0); + if ((window_index < 0) || + (window_index >= ARRAY_SIZE(windows))) + window_index = DEFAULT_WINDOW_INDEX; + } else if (strncmp(this_opt, "off", 3) == 0) + return 1; + else + print_warn("Unsupported option \"%s\"", this_opt); + } + +out: + return 0; +} + +/* AU1200 LCD controller device driver */ static int __devinit au1200fb_drv_probe(struct platform_device *dev) { struct au1200fb_device *fbdev; + struct au1200fb_platdata *pd; struct fb_info *fbi = NULL; unsigned long page; int bpp, plane, ret, irq; + print_info("" DRIVER_DESC ""); + + pd = dev->dev.platform_data; + if (!pd) + return -ENODEV; + + /* Setup driver with options */ + if (au1200fb_setup(pd)) + return -ENODEV; + + /* Point to the panel selected */ + panel = &known_lcd_panels[panel_index]; + win = &windows[window_index]; + + printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name); + printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name); + /* shut gcc up */ ret = 0; fbdev = NULL; - /* Kickstart the panel */ - au1200_setpanel(panel); - for (plane = 0; plane < device_count; ++plane) { bpp = winbpp(win->w[plane].mode_winctrl1); if (win->w[plane].xres == 0) @@ -1655,6 +1717,7 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev) _au1200fb_infos[plane] = fbi; fbdev = fbi->par; fbdev->fb_info = fbi; + fbdev->pd = pd; fbdev->plane = plane; @@ -1716,6 +1779,11 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev) goto failed; } + platform_set_drvdata(dev, pd); + + /* Kickstart the panel */ + au1200_setpanel(panel, pd); + return 0; failed: @@ -1735,12 +1803,13 @@ failed: static int __devexit au1200fb_drv_remove(struct platform_device *dev) { + struct au1200fb_platdata *pd = platform_get_drvdata(dev); struct au1200fb_device *fbdev; struct fb_info *fbi; int plane; /* Turn off the panel */ - au1200_setpanel(NULL); + au1200_setpanel(NULL, pd); for (plane = 0; plane < device_count; ++plane) { fbi = _au1200fb_infos[plane]; @@ -1768,7 +1837,8 @@ static int __devexit au1200fb_drv_remove(struct platform_device *dev) #ifdef CONFIG_PM static int au1200fb_drv_suspend(struct device *dev) { - au1200_setpanel(NULL); + struct au1200fb_platdata *pd = dev_get_drvdata(dev); + au1200_setpanel(NULL, pd); lcd->outmask = 0; au_sync(); @@ -1778,11 +1848,12 @@ static int au1200fb_drv_suspend(struct device *dev) static int au1200fb_drv_resume(struct device *dev) { + struct au1200fb_platdata *pd = dev_get_drvdata(dev); struct fb_info *fbi; int i; /* Kickstart the panel */ - au1200_setpanel(panel); + au1200_setpanel(panel, pd); for (i = 0; i < device_count; i++) { fbi = _au1200fb_infos[i]; @@ -1817,100 +1888,8 @@ static struct platform_driver au1200fb_driver = { /*-------------------------------------------------------------------------*/ -/* Kernel driver */ - -static int au1200fb_setup(void) -{ - char *options = NULL; - char *this_opt, *endptr; - int num_panels = ARRAY_SIZE(known_lcd_panels); - int panel_idx = -1; - - fb_get_options(DRIVER_NAME, &options); - - if (options) { - while ((this_opt = strsep(&options,",")) != NULL) { - /* Panel option - can be panel name, - * "bs" for board-switch, or number/index */ - if (!strncmp(this_opt, "panel:", 6)) { - int i; - long int li; - char *endptr; - this_opt += 6; - /* First check for index, which allows - * to short circuit this mess */ - li = simple_strtol(this_opt, &endptr, 0); - if (*endptr == '\0') { - panel_idx = (int)li; - } - else if (strcmp(this_opt, "bs") == 0) { - extern int board_au1200fb_panel(void); - panel_idx = board_au1200fb_panel(); - } - - else - for (i = 0; i < num_panels; i++) { - if (!strcmp(this_opt, known_lcd_panels[i].name)) { - panel_idx = i; - break; - } - } - - if ((panel_idx < 0) || (panel_idx >= num_panels)) { - print_warn("Panel %s not supported!", this_opt); - } - else - panel_index = panel_idx; - } - - else if (strncmp(this_opt, "nohwcursor", 10) == 0) { - nohwcursor = 1; - } - - else if (strncmp(this_opt, "devices:", 8) == 0) { - this_opt += 8; - device_count = simple_strtol(this_opt, - &endptr, 0); - if ((device_count < 0) || - (device_count > MAX_DEVICE_COUNT)) - device_count = MAX_DEVICE_COUNT; - } - - else if (strncmp(this_opt, "wincfg:", 7) == 0) { - this_opt += 7; - window_index = simple_strtol(this_opt, - &endptr, 0); - if ((window_index < 0) || - (window_index >= ARRAY_SIZE(windows))) - window_index = DEFAULT_WINDOW_INDEX; - } - - else if (strncmp(this_opt, "off", 3) == 0) - return 1; - /* Unsupported option */ - else { - print_warn("Unsupported option \"%s\"", this_opt); - } - } - } - return 0; -} - static int __init au1200fb_init(void) { - print_info("" DRIVER_DESC ""); - - /* Setup driver with options */ - if (au1200fb_setup()) - return -ENODEV; - - /* Point to the panel selected */ - panel = &known_lcd_panels[panel_index]; - win = &windows[window_index]; - - printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name); - printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name); - return platform_driver_register(&au1200fb_driver); } From 6f7c8623db005889ee35a602e0c2564ea06cd3ff Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:22 +0000 Subject: [PATCH 013/119] MIPS: Alchemy: Merge PB1200 support into DB1200 code. The PB1200 is basically a DB1200 with additional MMC and camera sockets and different base addresses for external hardware (CPLD, IDE, Net, NAND). This patch implements the missing PB1200 features in DB1200 support code and runtime board detection. Tested on DB1200 only. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2880/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 10 +- arch/mips/alchemy/Platform | 9 +- arch/mips/alchemy/devboards/Makefile | 1 - arch/mips/alchemy/devboards/db1200.c | 245 ++++++++++- arch/mips/alchemy/devboards/pb1200.c | 471 --------------------- arch/mips/configs/pb1200_defconfig | 170 -------- arch/mips/include/asm/mach-db1x00/db1200.h | 11 +- arch/mips/include/asm/mach-pb1x00/pb1200.h | 139 ------ 8 files changed, 238 insertions(+), 818 deletions(-) delete mode 100644 arch/mips/alchemy/devboards/pb1200.c delete mode 100644 arch/mips/configs/pb1200_defconfig delete mode 100644 arch/mips/include/asm/mach-pb1x00/pb1200.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index a1b995ff517b..e1b3be787f80 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -42,7 +42,7 @@ config MIPS_DB1100 select SYS_HAS_EARLY_PRINTK config MIPS_DB1200 - bool "Alchemy DB1200 board" + bool "Alchemy DB1200/PB1200 board" select ALCHEMY_GPIOINT_AU1000 select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE @@ -85,14 +85,6 @@ config MIPS_PB1100 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_PB1200 - bool "Alchemy PB1200 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select MIPS_DISABLE_OBSOLETE_IDE - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_PB1500 bool "Alchemy PB1500 board" select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index c032f5b5f889..bbdcc150d04d 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -25,13 +25,6 @@ platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/ cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 -# -# AMD Alchemy Pb1200 eval board -# -platform-$(CONFIG_MIPS_PB1200) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 -load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 - # # AMD Alchemy Db1000 eval board # @@ -61,7 +54,7 @@ cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 # -# AMD Alchemy Db1200 eval board +# AMD Alchemy Db1200/Pb1200 eval boards # platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index f5628523c694..2fbf17909200 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -5,7 +5,6 @@ obj-y += prom.o bcsr.o platform.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MIPS_PB1100) += pb1100.o -obj-$(CONFIG_MIPS_PB1200) += pb1200.o obj-$(CONFIG_MIPS_PB1500) += pb1500.o obj-$(CONFIG_MIPS_PB1550) += pb1550.o obj-$(CONFIG_MIPS_DB1000) += db1x00.o diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index e2cc5f921538..ec481f33aecc 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -1,5 +1,5 @@ /* - * DBAu1200 board platform device registration + * DBAu1200/PBAu1200 board platform device registration * * Copyright (C) 2008-2011 Manuel Lauss * @@ -44,10 +44,41 @@ #include "platform.h" +static const char *board_type_str(void) +{ + switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { + case BCSR_WHOAMI_PB1200_DDR1: + case BCSR_WHOAMI_PB1200_DDR2: + return "PB1200"; + case BCSR_WHOAMI_DB1200: + return "DB1200"; + default: + return "(unknown)"; + } +} const char *get_system_type(void) { - return "DB1200"; + return board_type_str(); +} + +static int __init detect_board(void) +{ + int bid; + + /* try the PB1200 first */ + bcsr_init(PB1200_BCSR_PHYS_ADDR, + PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); + bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + if ((bid == BCSR_WHOAMI_PB1200_DDR1) || + (bid == BCSR_WHOAMI_PB1200_DDR2)) + return 0; + + /* okay, try the DB1200 then */ + bcsr_init(DB1200_BCSR_PHYS_ADDR, + DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); + bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + return bid == BCSR_WHOAMI_DB1200 ? 0 : 1; } void __init board_setup(void) @@ -55,12 +86,14 @@ void __init board_setup(void) unsigned long freq0, clksrc, div, pfc; unsigned short whoami; - bcsr_init(DB1200_BCSR_PHYS_ADDR, - DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); + if (detect_board()) { + printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n"); + return; + } whoami = bcsr_read(BCSR_WHOAMI); - printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d" - " Board-ID %d Daughtercard ID %d\n", + printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" + " Board-ID %d Daughtercard ID %d\n", board_type_str(), (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); /* SMBus/SPI on PSC0, Audio on PSC1 */ @@ -96,7 +129,7 @@ void __init board_setup(void) static struct mtd_partition db1200_spiflash_parts[] = { { - .name = "DB1200 SPI flash", + .name = "spi_flash", .offset = 0, .size = MTDPART_SIZ_FULL, }, @@ -376,12 +409,109 @@ static struct led_classdev db1200_mmc_led = { .brightness_set = db1200_mmcled_set, }; -static struct au1xmmc_platform_data db1200mmc_platdata = { - .cd_setup = db1200_mmc_cd_setup, - .set_power = db1200_mmc_set_power, - .card_inserted = db1200_mmc_card_inserted, - .card_readonly = db1200_mmc_card_readonly, - .led = &db1200_mmc_led, +/* -- */ + +static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) +{ + void(*mmc_cd)(struct mmc_host *, unsigned long); + + if (irq == PB1200_SD1_INSERT_INT) { + disable_irq_nosync(PB1200_SD1_INSERT_INT); + enable_irq(PB1200_SD1_EJECT_INT); + } else { + disable_irq_nosync(PB1200_SD1_EJECT_INT); + enable_irq(PB1200_SD1_INSERT_INT); + } + + /* link against CONFIG_MMC=m */ + mmc_cd = symbol_get(mmc_detect_change); + if (mmc_cd) { + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + } + + return IRQ_HANDLED; +} + +static int pb1200_mmc1_cd_setup(void *mmc_host, int en) +{ + int ret; + + if (en) { + ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0, + "sd1_insert", mmc_host); + if (ret) + goto out; + + ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0, + "sd1_eject", mmc_host); + if (ret) { + free_irq(PB1200_SD1_INSERT_INT, mmc_host); + goto out; + } + + if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) + enable_irq(PB1200_SD1_EJECT_INT); + else + enable_irq(PB1200_SD1_INSERT_INT); + + } else { + free_irq(PB1200_SD1_INSERT_INT, mmc_host); + free_irq(PB1200_SD1_EJECT_INT, mmc_host); + } + ret = 0; +out: + return ret; +} + +static void pb1200_mmc1led_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); +} + +static struct led_classdev pb1200_mmc1_led = { + .brightness_set = pb1200_mmc1led_set, +}; + +static void pb1200_mmc1_set_power(void *mmc_host, int state) +{ + if (state) { + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); + msleep(400); /* stabilization time */ + } else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); +} + +static int pb1200_mmc1_card_readonly(void *mmc_host) +{ + return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; +} + +static int pb1200_mmc1_card_inserted(void *mmc_host) +{ + return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; +} + + +static struct au1xmmc_platform_data db1200_mmc_platdata[2] = { + [0] = { + .cd_setup = db1200_mmc_cd_setup, + .set_power = db1200_mmc_set_power, + .card_inserted = db1200_mmc_card_inserted, + .card_readonly = db1200_mmc_card_readonly, + .led = &db1200_mmc_led, + }, + [1] = { + .cd_setup = pb1200_mmc1_cd_setup, + .set_power = pb1200_mmc1_set_power, + .card_inserted = pb1200_mmc1_card_inserted, + .card_readonly = pb1200_mmc1_card_readonly, + .led = &pb1200_mmc1_led, + }, }; static struct resource au1200_mmc0_resources[] = { @@ -415,12 +545,47 @@ static struct platform_device db1200_mmc0_dev = { .dev = { .dma_mask = &au1xxx_mmc_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &db1200mmc_platdata, + .platform_data = &db1200_mmc_platdata[0], }, .num_resources = ARRAY_SIZE(au1200_mmc0_resources), .resource = au1200_mmc0_resources, }; +static struct resource au1200_mmc1_res[] = { + [0] = { + .start = AU1100_SD1_PHYS_ADDR, + .end = AU1100_SD1_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_SDMS_TX1, + .end = AU1200_DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_SDMS_RX1, + .end = AU1200_DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device pb1200_mmc1_dev = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1200_mmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1200_mmc1_res), + .resource = au1200_mmc1_res, +}; + /**********************************************************************/ static int db1200fb_panel_index(void) @@ -598,14 +763,50 @@ static struct platform_device *db1200_devs[] __initdata = { &db1200_sound_dev, }; +static struct platform_device *pb1200_devs[] __initdata = { + &pb1200_mmc1_dev, +}; + +/* Some peripheral base addresses differ on the PB1200 */ +static int __init pb1200_res_fixup(void) +{ + /* CPLD Revs earlier than 4 cause problems */ + if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n"); + printk(KERN_ERR "the board updated to latest revisions.\n"); + printk(KERN_ERR "This software will not work reliably\n"); + printk(KERN_ERR "on anything older than CPLD rev 4.!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + return 1; + } + + db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; + db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; + db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; + db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; + db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; + db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; + return 0; +} + static int __init db1200_dev_init(void) { unsigned long pfc; unsigned short sw; - int swapped; + int swapped, bid; + + bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + if ((bid == BCSR_WHOAMI_PB1200_DDR1) || + (bid == BCSR_WHOAMI_PB1200_DDR2)) { + if (pb1200_res_fixup()) + return -ENODEV; + } /* GPIO7 is low-level triggered CPLD cascade */ - irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); /* insert/eject pairs: one of both is always screaming. To avoid @@ -626,6 +827,7 @@ static int __init db1200_dev_init(void) /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) + * or S12 on the PB1200. */ /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however @@ -640,7 +842,7 @@ static int __init db1200_dev_init(void) gpio_request(215, "otg-vbus"); gpio_direction_output(215, 1); - printk(KERN_INFO "DB1200 device configuration:\n"); + printk(KERN_INFO "%s device configuration:\n", board_type_str()); sw = bcsr_read(BCSR_SWITCHES); if (sw & BCSR_SWITCHES_DIP_8) { @@ -707,6 +909,13 @@ static int __init db1200_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(64 << 20, 2, swapped); - return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); + platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); + + /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ + if ((bid == BCSR_WHOAMI_PB1200_DDR1) || + (bid == BCSR_WHOAMI_PB1200_DDR2)) + platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); + + return 0; } device_initcall(db1200_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1200.c b/arch/mips/alchemy/devboards/pb1200.c deleted file mode 100644 index a2676c95053b..000000000000 --- a/arch/mips/alchemy/devboards/pb1200.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Pb1200/DBAu1200 board platform device registration - * - * Copyright (C) 2008 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "platform.h" - - -const char *get_system_type(void) -{ - return "PB1200"; -} - -void __init board_setup(void) -{ - printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); - bcsr_init(PB1200_BCSR_PHYS_ADDR, - PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); - -#if 0 - { - u32 pin_func; - - /* - * Enable PSC1 SYNC for AC97. Normaly done in audio driver, - * but it is board specific code, so put it here. - */ - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; - au_writel(pin_func, SYS_PINFUNC); - - au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ - au_sync(); - } -#endif - -#if defined(CONFIG_I2C_AU1550) - { - u32 freq0, clksrc; - u32 pin_func; - - /* Select SMBus in CPLD */ - bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); - - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); - /* Set GPIOs correctly */ - pin_func |= 2 << 17; - au_writel(pin_func, SYS_PINFUNC); - au_sync(); - - /* The I2C driver depends on 50 MHz clock */ - freq0 = au_readl(SYS_FREQCTRL0); - au_sync(); - freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); - freq0 |= 3 << SYS_FC_FRDIV1_BIT; - /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */ - au_writel(freq0, SYS_FREQCTRL0); - au_sync(); - freq0 |= SYS_FC_FE1; - au_writel(freq0, SYS_FREQCTRL0); - au_sync(); - - clksrc = au_readl(SYS_CLKSRC); - au_sync(); - clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK); - /* Bit 22 is EXTCLK0 for PSC0 */ - clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT; - au_writel(clksrc, SYS_CLKSRC); - au_sync(); - } -#endif - - /* - * The Pb1200 development board uses external MUX for PSC0 to - * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI - */ -#ifdef CONFIG_I2C_AU1550 - bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); -#endif - au_sync(); -} - -/******************************************************************************/ - -static int mmc_activity; - -static void pb1200mmc0_set_power(void *mmc_host, int state) -{ - if (state) - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); - else - bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); - - msleep(1); -} - -static int pb1200mmc0_card_readonly(void *mmc_host) -{ - return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; -} - -static int pb1200mmc0_card_inserted(void *mmc_host) -{ - return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; -} - -static void pb1200_mmcled_set(struct led_classdev *led, - enum led_brightness brightness) -{ - if (brightness != LED_OFF) { - if (++mmc_activity == 1) - bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); - } else { - if (--mmc_activity == 0) - bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); - } -} - -static struct led_classdev pb1200mmc_led = { - .brightness_set = pb1200_mmcled_set, -}; - -static void pb1200mmc1_set_power(void *mmc_host, int state) -{ - if (state) - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); - else - bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); - - msleep(1); -} - -static int pb1200mmc1_card_readonly(void *mmc_host) -{ - return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; -} - -static int pb1200mmc1_card_inserted(void *mmc_host) -{ - return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; -} - -static struct au1xmmc_platform_data pb1200mmc_platdata[2] = { - [0] = { - .set_power = pb1200mmc0_set_power, - .card_inserted = pb1200mmc0_card_inserted, - .card_readonly = pb1200mmc0_card_readonly, - .cd_setup = NULL, /* use poll-timer in driver */ - .led = &pb1200mmc_led, - }, - [1] = { - .set_power = pb1200mmc1_set_power, - .card_inserted = pb1200mmc1_card_inserted, - .card_readonly = pb1200mmc1_card_readonly, - .cd_setup = NULL, /* use poll-timer in driver */ - .led = &pb1200mmc_led, - }, -}; - -static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); - -static struct resource au1200_mmc0_res[] = { - [0] = { - .start = AU1100_SD0_PHYS_ADDR, - .end = AU1100_SD0_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_SDMS_TX0, - .end = AU1200_DSCR_CMD0_SDMS_TX0, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_SDMS_RX0, - .end = AU1200_DSCR_CMD0_SDMS_RX0, - .flags = IORESOURCE_DMA, - } -}; - -static struct platform_device pb1200_mmc0_dev = { - .name = "au1xxx-mmc", - .id = 0, - .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &pb1200mmc_platdata[0], - }, - .num_resources = ARRAY_SIZE(au1200_mmc0_res), - .resource = au1200_mmc0_res, -}; - -static struct resource au1200_mmc1_res[] = { - [0] = { - .start = AU1100_SD1_PHYS_ADDR, - .end = AU1100_SD1_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_SDMS_TX1, - .end = AU1200_DSCR_CMD0_SDMS_TX1, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_SDMS_RX1, - .end = AU1200_DSCR_CMD0_SDMS_RX1, - .flags = IORESOURCE_DMA, - } -}; - -static struct platform_device pb1200_mmc1_dev = { - .name = "au1xxx-mmc", - .id = 1, - .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &pb1200mmc_platdata[1], - }, - .num_resources = ARRAY_SIZE(au1200_mmc1_res), - .resource = au1200_mmc1_res, -}; - - -static struct resource ide_resources[] = { - [0] = { - .start = IDE_PHYS_ADDR, - .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = IDE_INT, - .end = IDE_INT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = AU1200_DSCR_CMD0_DMA_REQ1, - .end = AU1200_DSCR_CMD0_DMA_REQ1, - .flags = IORESOURCE_DMA, - }, -}; - -static u64 au1200_ide_dmamask = DMA_BIT_MASK(32); - -static struct platform_device ide_device = { - .name = "au1200-ide", - .id = 0, - .dev = { - .dma_mask = &au1200_ide_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(ide_resources), - .resource = ide_resources -}; - -static struct smc91x_platdata smc_data = { - .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91c111_resources[] = { - [0] = { - .name = "smc91x-regs", - .start = SMC91C111_PHYS_ADDR, - .end = SMC91C111_PHYS_ADDR + 0xf, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = SMC91C111_INT, - .end = SMC91C111_INT, - .flags = IORESOURCE_IRQ - }, -}; - -static struct platform_device smc91c111_device = { - .dev = { - .platform_data = &smc_data, - }, - .name = "smc91x", - .id = -1, - .num_resources = ARRAY_SIZE(smc91c111_resources), - .resource = smc91c111_resources -}; - -static struct resource au1200_psc0_res[] = { - [0] = { - .start = AU1550_PSC0_PHYS_ADDR, - .end = AU1550_PSC0_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_PSC0_INT, - .end = AU1200_PSC0_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_PSC0_TX, - .end = AU1200_DSCR_CMD0_PSC0_TX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_PSC0_RX, - .end = AU1200_DSCR_CMD0_PSC0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device pb1200_i2c_dev = { - .name = "au1xpsc_smbus", - .id = 0, /* bus number */ - .num_resources = ARRAY_SIZE(au1200_psc0_res), - .resource = au1200_psc0_res, -}; - -static int pb1200fb_panel_index(void) -{ - return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; -} - -static int pb1200fb_panel_init(void) -{ - /* Apply power */ - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); - return 0; -} - -static int pb1200fb_panel_shutdown(void) -{ - /* Remove power */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL, 0); - return 0; -} - -static struct au1200fb_platdata pb1200fb_pd = { - .panel_index = pb1200fb_panel_index, - .panel_init = pb1200fb_panel_init, - .panel_shutdown = pb1200fb_panel_shutdown, -}; - -static struct resource au1200_lcd_res[] = { - [0] = { - .start = AU1200_LCD_PHYS_ADDR, - .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_LCD_INT, - .end = AU1200_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device pb1200_lcd_dev = { - .name = "au1200-lcd", - .id = 0, - .dev = { - .dma_mask = &au1200_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &pb1200fb_pd, - }, - .num_resources = ARRAY_SIZE(au1200_lcd_res), - .resource = au1200_lcd_res, -}; - -static struct platform_device *board_platform_devices[] __initdata = { - &ide_device, - &smc91c111_device, - &pb1200_i2c_dev, - &pb1200_mmc0_dev, - &pb1200_mmc1_dev, - &pb1200_lcd_dev, -}; - -static int __init board_register_devices(void) -{ - int swapped; - - /* We have a problem with CPLD rev 3. */ - if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n"); - printk(KERN_ERR "updated to latest revision. This software will\n"); - printk(KERN_ERR "not work on anything less than CPLD rev 4.\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - panic("Game over. Your score is 0."); - } - - irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); - bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - PB1200_PC0_INT, PB1200_PC0_INSERT_INT, - /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0); - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, - PB1200_PC1_INT, PB1200_PC1_INSERT_INT, - /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1); - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; - db1x_register_norflash(128 * 1024 * 1024, 2, swapped); - - return platform_add_devices(board_platform_devices, - ARRAY_SIZE(board_platform_devices)); -} -device_initcall(board_register_devices); diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig deleted file mode 100644 index dcbe2704e5ed..000000000000 --- a/arch/mips/configs/pb1200_defconfig +++ /dev/null @@ -1,170 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_PB1200=y -CONFIG_KSM=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-pb1200" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_UB=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_BLK_DEV_IDECD=y -CONFIG_IDE_TASK_IOCTL=y -# CONFIG_IDE_PROC_FS is not set -CONFIG_BLK_DEV_IDE_AU1XXX=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_AU1550=y -CONFIG_SPI=y -CONFIG_SPI_AU1550=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_SENSORS_ADM1025=y -CONFIG_SENSORS_LM70=y -CONFIG_FB=y -CONFIG_FB_AU1200=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_8x16=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_MIPS is not set -# CONFIG_SND_USB is not set -# CONFIG_SND_PCMCIA is not set -CONFIG_SND_SOC=y -CONFIG_SND_SOC_AU1XPSC=y -CONFIG_SND_SOC_DB1200=y -CONFIG_HIDRAW=y -CONFIG_USB_HIDDEV=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_OHCI_HCD=y -CONFIG_MMC=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_AU1X=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=y -CONFIG_VFAT_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_EFI_PARTITION=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0,115200" -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 7a39657108c4..b2a8319521e5 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -43,15 +43,20 @@ #define BCSR_INT_PC1EJECT 0x0800 #define BCSR_INT_SD0INSERT 0x1000 #define BCSR_INT_SD0EJECT 0x2000 +#define BCSR_INT_SD1INSERT 0x4000 +#define BCSR_INT_SD1EJECT 0x8000 -#define IDE_PHYS_ADDR 0x18800000 #define IDE_REG_SHIFT 5 -#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR +#define DB1200_IDE_PHYS_ADDR 0x18800000 #define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) #define DB1200_ETH_PHYS_ADDR 0x19000300 #define DB1200_NAND_PHYS_ADDR 0x20000000 +#define PB1200_IDE_PHYS_ADDR 0x0C800000 +#define PB1200_ETH_PHYS_ADDR 0x0D000300 +#define PB1200_NAND_PHYS_ADDR 0x1C000000 + /* * External Interrupts for DBAu1200 as of 8/6/2004. * Bit positions in the CPLD registers can be calculated by taking @@ -77,6 +82,8 @@ enum external_db1200_ints { DB1200_PC1_EJECT_INT, DB1200_SD0_INSERT_INT, DB1200_SD0_EJECT_INT, + PB1200_SD1_INSERT_INT, + PB1200_SD1_EJECT_INT, DB1200_INT_END = DB1200_INT_BEGIN + 15, }; diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h deleted file mode 100644 index 374416adb65b..000000000000 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * AMD Alchemy Pb1200 Reference Board - * Board Registers defines. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1200_H -#define __ASM_PB1200_H - -#include -#include -#include - -#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX - -/* - * SPI and SMB are muxed on the Pb1200 board. - * Refer to board documentation. - */ -#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR -#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR -/* - * AC97 and I2S are muxed on the Pb1200 board. - * Refer to board documentation. - */ -#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR -#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR - - -#define BCSR_SYSTEM_VDDI 0x001F -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - -/* Bit positions for the different interrupt sources */ -#define BCSR_INT_IDE 0x0001 -#define BCSR_INT_ETH 0x0002 -#define BCSR_INT_PC0 0x0004 -#define BCSR_INT_PC0STSCHG 0x0008 -#define BCSR_INT_PC1 0x0010 -#define BCSR_INT_PC1STSCHG 0x0020 -#define BCSR_INT_DC 0x0040 -#define BCSR_INT_FLASHBUSY 0x0080 -#define BCSR_INT_PC0INSERT 0x0100 -#define BCSR_INT_PC0EJECT 0x0200 -#define BCSR_INT_PC1INSERT 0x0400 -#define BCSR_INT_PC1EJECT 0x0800 -#define BCSR_INT_SD0INSERT 0x1000 -#define BCSR_INT_SD0EJECT 0x2000 -#define BCSR_INT_SD1INSERT 0x4000 -#define BCSR_INT_SD1EJECT 0x8000 - -#define SMC91C111_PHYS_ADDR 0x0D000300 -#define SMC91C111_INT PB1200_ETH_INT - -#define IDE_PHYS_ADDR 0x0C800000 -#define IDE_REG_SHIFT 5 -#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) -#define IDE_INT PB1200_IDE_INT - -#define NAND_PHYS_ADDR 0x1C000000 - -/* - * Timing values as described in databook, * ns value stripped of - * lower 2 bits. - * These defines are here rather than an Au1200 generic file because - * the parts chosen on another board may be different and may require - * different timings. - */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) - -/* Bitfield shift amounts */ -#define NAND_T_H_SHIFT 0 -#define NAND_T_PUL_SHIFT 4 -#define NAND_T_SU_SHIFT 8 -#define NAND_T_WH_SHIFT 12 - -#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) - -/* - * External Interrupts for Pb1200 as of 8/6/2004. - * Bit positions in the CPLD registers can be calculated by taking - * the interrupt define and subtracting the PB1200_INT_BEGIN value. - * - * Example: IDE bis pos is = 64 - 64 - * ETH bit pos is = 65 - 64 - */ -enum external_pb1200_ints { - PB1200_INT_BEGIN = AU1000_MAX_INTR + 1, - - PB1200_IDE_INT = PB1200_INT_BEGIN, - PB1200_ETH_INT, - PB1200_PC0_INT, - PB1200_PC0_STSCHG_INT, - PB1200_PC1_INT, - PB1200_PC1_STSCHG_INT, - PB1200_DC_INT, - PB1200_FLASHBUSY_INT, - PB1200_PC0_INSERT_INT, - PB1200_PC0_EJECT_INT, - PB1200_PC1_INSERT_INT, - PB1200_PC1_EJECT_INT, - PB1200_SD0_INSERT_INT, - PB1200_SD0_EJECT_INT, - PB1200_SD1_INSERT_INT, - PB1200_SD1_EJECT_INT, - - PB1200_INT_END = PB1200_INT_BEGIN + 15 -}; - -/* NAND chip select */ -#define NAND_CS 1 - -#endif /* __ASM_PB1200_H */ From f59c811f8c44e60a59783e3337594da638a48dff Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:22 +0000 Subject: [PATCH 014/119] MIPS: Alchemy: one kernel for DB1000/DB1500/DB1100 These 3 boards are very similar; with this patch a single kernel image which runs on all three can be built. Tested on DB1500 and DB1100. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2872/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 21 +- arch/mips/alchemy/Platform | 16 +- arch/mips/alchemy/devboards/Makefile | 4 +- .../alchemy/devboards/{db1x00.c => db1000.c} | 135 ++++--- arch/mips/alchemy/devboards/prom.c | 4 +- arch/mips/configs/db1000_defconfig | 369 +++++++++++++++--- arch/mips/configs/db1100_defconfig | 122 ------ arch/mips/configs/db1500_defconfig | 128 ------ drivers/net/irda/au1k_ir.c | 10 +- drivers/video/au1100fb.c | 12 - 10 files changed, 390 insertions(+), 431 deletions(-) rename arch/mips/alchemy/devboards/{db1x00.c => db1000.c} (69%) delete mode 100644 arch/mips/configs/db1100_defconfig delete mode 100644 arch/mips/configs/db1500_defconfig diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index e1b3be787f80..0faaab24376e 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -27,17 +27,12 @@ config MIPS_MTX1 select SYS_HAS_EARLY_PRINTK config MIPS_DB1000 - bool "Alchemy DB1000 board" + bool "Alchemy DB1000/DB1500/DB1100 boards" select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - -config MIPS_DB1100 - bool "Alchemy DB1100 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK @@ -57,16 +52,6 @@ config MIPS_DB1300 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_DB1500 - bool "Alchemy DB1500 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - select MIPS_DISABLE_OBSOLETE_IDE - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_DB1550 bool "Alchemy DB1550 board" select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index bbdcc150d04d..33f80e8cbd69 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -26,26 +26,12 @@ cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 # -# AMD Alchemy Db1000 eval board +# AMD Alchemy Db1000/Db1500/Db1100 eval boards # platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 -# -# AMD Alchemy Db1100 eval board -# -platform-$(CONFIG_MIPS_DB1100) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 - -# -# AMD Alchemy Db1500 eval board -# -platform-$(CONFIG_MIPS_DB1500) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 - # # AMD Alchemy Db1550 eval board # diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 2fbf17909200..3c37fb303364 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -7,9 +7,7 @@ obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MIPS_PB1100) += pb1100.o obj-$(CONFIG_MIPS_PB1500) += pb1500.o obj-$(CONFIG_MIPS_PB1550) += pb1550.o -obj-$(CONFIG_MIPS_DB1000) += db1x00.o -obj-$(CONFIG_MIPS_DB1100) += db1x00.o +obj-$(CONFIG_MIPS_DB1000) += db1000.o obj-$(CONFIG_MIPS_DB1200) += db1200.o obj-$(CONFIG_MIPS_DB1300) += db1300.o -obj-$(CONFIG_MIPS_DB1500) += db1x00.o obj-$(CONFIG_MIPS_DB1550) += db1550.o diff --git a/arch/mips/alchemy/devboards/db1x00.c b/arch/mips/alchemy/devboards/db1000.c similarity index 69% rename from arch/mips/alchemy/devboards/db1x00.c rename to arch/mips/alchemy/devboards/db1000.c index 589ae2435cbe..57ed5f1c4919 100644 --- a/arch/mips/alchemy/devboards/db1x00.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -32,28 +32,37 @@ #include #include "platform.h" +#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) + struct pci_dev; +static const char *board_type_str(void) +{ + switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { + case BCSR_WHOAMI_DB1000: + return "DB1000"; + case BCSR_WHOAMI_DB1500: + return "DB1500"; + case BCSR_WHOAMI_DB1100: + return "DB1100"; + default: + return "(unknown)"; + } +} + const char *get_system_type(void) { - return "Alchemy Db1x00"; + return board_type_str(); } void __init board_setup(void) { -#ifdef CONFIG_MIPS_DB1000 - printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1500 - printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1100 - printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); -#endif /* initialize board register space */ bcsr_init(DB1000_BCSR_PHYS_ADDR, DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); + printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str()); + #if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) { u32 pin_func; @@ -72,35 +81,6 @@ void __init board_setup(void) alchemy_gpio1_input_enable(); } -/* DB1xxx PCMCIA interrupt sources: - * CD0/1 GPIO0/3 - * STSCHG0/1 GPIO1/4 - * CARD0/1 GPIO2/5 - */ - -#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) - -#if defined(CONFIG_MIPS_DB1000) -#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT -#elif defined(CONFIG_MIPS_DB1100) -#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT -#elif defined(CONFIG_MIPS_DB1500) -#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) { @@ -141,13 +121,14 @@ static struct platform_device db1500_pci_host_dev = { static int __init db1500_pci_init(void) { - return platform_device_register(&db1500_pci_host_dev); + if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1500) + return platform_device_register(&db1500_pci_host_dev); + return 0; } /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ arch_initcall(db1500_pci_init); -#endif -#ifdef CONFIG_MIPS_DB1100 + static struct resource au1100_lcd_resources[] = { [0] = { .start = AU1100_LCD_PHYS_ADDR, @@ -173,7 +154,6 @@ static struct platform_device au1100_lcd_device = { .num_resources = ARRAY_SIZE(au1100_lcd_resources), .resource = au1100_lcd_resources, }; -#endif static struct resource alchemy_ac97c_res[] = { [0] = { @@ -214,14 +194,53 @@ static struct platform_device db1x00_audio_dev = { .name = "db1000-audio", }; -static int __init db1xxx_dev_init(void) +static struct platform_device *db1x00_devs[] = { + &db1x00_codec_dev, + &alchemy_ac97c_dma_dev, + &alchemy_ac97c_dev, + &db1x00_audio_dev, +}; + +static struct platform_device *db1100_devs[] = { + &au1100_lcd_device, +}; + +static int __init db1000_dev_init(void) { - irq_set_irq_type(DB1XXX_PCMCIA_CD0, IRQ_TYPE_EDGE_BOTH); - irq_set_irq_type(DB1XXX_PCMCIA_CD1, IRQ_TYPE_EDGE_BOTH); - irq_set_irq_type(DB1XXX_PCMCIA_CARD0, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(DB1XXX_PCMCIA_CARD1, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(DB1XXX_PCMCIA_STSCHG0, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(DB1XXX_PCMCIA_STSCHG1, IRQ_TYPE_LEVEL_LOW); + int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + int c0, c1, d0, d1, s0, s1; + + if (board == BCSR_WHOAMI_DB1500) { + c0 = AU1500_GPIO2_INT; + c1 = AU1500_GPIO5_INT; + d0 = AU1500_GPIO0_INT; + d1 = AU1500_GPIO3_INT; + s0 = AU1500_GPIO1_INT; + s1 = AU1500_GPIO4_INT; + } else if (board == BCSR_WHOAMI_DB1100) { + c0 = AU1100_GPIO2_INT; + c1 = AU1100_GPIO5_INT; + d0 = AU1100_GPIO0_INT; + d1 = AU1100_GPIO3_INT; + s0 = AU1100_GPIO1_INT; + s1 = AU1100_GPIO4_INT; + platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); + } else if (board == BCSR_WHOAMI_DB1000) { + c0 = AU1000_GPIO2_INT; + c1 = AU1000_GPIO5_INT; + d0 = AU1000_GPIO0_INT; + d1 = AU1000_GPIO3_INT; + s0 = AU1000_GPIO1_INT; + s1 = AU1000_GPIO4_INT; + } else + return 0; /* unknown board, no further dev setup to do */ + + irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, @@ -230,8 +249,7 @@ static int __init db1xxx_dev_init(void) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR, AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0, - /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0); + c0, d0, /*s0*/0, 0, 0); db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, @@ -240,17 +258,10 @@ static int __init db1xxx_dev_init(void) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, - /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); -#ifdef CONFIG_MIPS_DB1100 - platform_device_register(&au1100_lcd_device); -#endif - platform_device_register(&db1x00_codec_dev); - platform_device_register(&alchemy_ac97c_dma_dev); - platform_device_register(&alchemy_ac97c_dev); - platform_device_register(&db1x00_audio_dev); + c1, d1, /*s1*/0, 0, 1); + platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED); return 0; } -device_initcall(db1xxx_dev_init); +device_initcall(db1000_dev_init); diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index 3a73f9663b0f..93a22107cc41 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -34,8 +34,8 @@ #include #if defined(CONFIG_MIPS_DB1000) || \ - defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) + defined(CONFIG_MIPS_PB1100) || \ + defined(CONFIG_MIPS_PB1500) #define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 #else /* Au1550/Au1200-based develboards */ diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 4044c9e0fb73..17a36c125172 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -1,118 +1,359 @@ +CONFIG_MIPS=y CONFIG_MIPS_ALCHEMY=y +CONFIG_MIPS_DB1000=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1000" +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="-db1x00" +CONFIG_LOCALVERSION_AUTO=y CONFIG_KERNEL_LZMA=y +CONFIG_DEFAULT_HOSTNAME="db1x00" +CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_FHANDLE=y +CONFIG_AUDIT=y CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SYSCTL=y CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_SLABINFO=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_FREEZER=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y CONFIG_PCCARD=y +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y CONFIG_PM_RUNTIME=y +CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_XFRM=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_NET_IPIP=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_LRO=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_STP=y +CONFIG_GARP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_LLC=y +CONFIG_LLC2=y +CONFIG_DNS_RESOLVER=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +CONFIG_MTD_CFI_I8=y +CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_PHYSMAP=y -# CONFIG_MISC_DEVICES is not set +CONFIG_SCSI_MOD=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_SFF=y +CONFIG_ATA_BMDMA=y +CONFIG_PATA_HPT37X=y +CONFIG_PATA_PCMCIA=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_FIREWIRE=y +CONFIG_FIREWIRE_OHCI=y +CONFIG_FIREWIRE_OHCI_DEBUG=y +CONFIG_FIREWIRE_NET=y CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_NET_ETHERNET=y CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=y +CONFIG_PCMCIA_PCNET=y +CONFIG_PPP=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOE=y +CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_DEVKMEM=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_TTY_PRINTK=y +CONFIG_DEVPORT=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_AU1100=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x16=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XAUDIO=y +CONFIG_SND_SOC_AU1XAC97C=y +CONFIG_SND_SOC_DB1000=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_USB_HID=y +CONFIG_USB_SUPPORT=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_GENERIC_ACL=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y CONFIG_TMPFS=y -CONFIG_CRAMFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +CONFIG_JFFS2_CMODE_PRIORITY=y CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=y CONFIG_ROOT_NFS=y +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_USE_NEW_IDMAPPER=y +CONFIG_NFSD=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="noirqdebug rootwait root=/dev/sda1 rootfstype=ext4 console=ttyS0,115200 video=au1100fb:panel:CRT_800x600_16" CONFIG_DEBUG_ZBOOT=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig deleted file mode 100644 index c6b49938ee84..000000000000 --- a/arch/mips/configs/db1100_defconfig +++ /dev/null @@ -1,122 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_DB1100=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1100" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_IDE_TASK_IOCTL=y -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FB_AU1100=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_8x16=y -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig deleted file mode 100644 index b6e21c7cb6bd..000000000000 --- a/arch/mips/configs/db1500_defconfig +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_DB1500=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1500" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCI=y -CONFIG_PCCARD=y -# CONFIG_CARDBUS is not set -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -CONFIG_BLK_DEV_HPT366=y -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_PCI is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_ARB is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index d1a77ef9b9e8..670bb0591217 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c @@ -32,7 +32,7 @@ #include #include #include -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) #include #else #error au1k_ir: unsupported board @@ -274,7 +274,7 @@ static int au1k_irda_net_init(struct net_device *dev) aup->tx_db_inuse[i] = pDB; } -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) /* power on */ bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, BCSR_RESETS_IRDA_MODE_FULL); @@ -662,7 +662,7 @@ au1k_irda_set_speed(struct net_device *dev, int speed) u32 control; int ret = 0, timeout = 10, i; volatile ring_dest_t *ptxd; -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) unsigned long irda_resets; #endif @@ -711,14 +711,14 @@ au1k_irda_set_speed(struct net_device *dev, int speed) } if (speed == 4000000) { -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_FIR_SEL); #else /* Pb1000 and Pb1100 */ writel(1<<13, CPLD_AUX1); #endif } else { -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) bcsr_mod(BCSR_RESETS, BCSR_RESETS_FIR_SEL, 0); #else /* Pb1000 and Pb1100 */ writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c index 649cb35de4ed..de9da6774fd9 100644 --- a/drivers/video/au1100fb.c +++ b/drivers/video/au1100fb.c @@ -60,18 +60,6 @@ #include "au1100fb.h" -/* - * Sanity check. If this is a new Au1100 based board, search for - * the PB1100 ifdefs to make sure you modify the code accordingly. - */ -#if defined(CONFIG_MIPS_PB1100) - #include -#elif defined(CONFIG_MIPS_DB1100) - #include -#else - #error "Unknown Au1100 board, Au1100 FB driver not supported" -#endif - #define DRIVER_NAME "au1100fb" #define DRIVER_DESC "LCD controller driver for AU1100 processors" From c9af5144ce5e6270a8bffad348cf2f20648f5f67 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:22 +0000 Subject: [PATCH 015/119] MIPS: Alchemy: MMC for DB1100 This patch hooks up the 2 MMC sockets on the DB1100 board. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2873/ Patchwork: https://patchwork.linux-mips.org/patch/2920/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/db1000.c | 202 +++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c index 57ed5f1c4919..a3a448033037 100644 --- a/arch/mips/alchemy/devboards/db1000.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -23,10 +23,14 @@ #include #include #include +#include +#include +#include #include #include #include #include +#include #include #include #include @@ -194,6 +198,198 @@ static struct platform_device db1x00_audio_dev = { .name = "db1000-audio", }; +/******************************************************************************/ + +static irqreturn_t db1100_mmc_cd(int irq, void *ptr) +{ + void (*mmc_cd)(struct mmc_host *, unsigned long); + /* link against CONFIG_MMC=m */ + mmc_cd = symbol_get(mmc_detect_change); + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + + return IRQ_HANDLED; +} + +static int db1100_mmc_cd_setup(void *mmc_host, int en) +{ + int ret = 0; + + if (en) { + irq_set_irq_type(AU1100_GPIO19_INT, IRQ_TYPE_EDGE_BOTH); + ret = request_irq(AU1100_GPIO19_INT, db1100_mmc_cd, 0, + "sd0_cd", mmc_host); + } else + free_irq(AU1100_GPIO19_INT, mmc_host); + return ret; +} + +static int db1100_mmc1_cd_setup(void *mmc_host, int en) +{ + int ret = 0; + + if (en) { + irq_set_irq_type(AU1100_GPIO20_INT, IRQ_TYPE_EDGE_BOTH); + ret = request_irq(AU1100_GPIO20_INT, db1100_mmc_cd, 0, + "sd1_cd", mmc_host); + } else + free_irq(AU1100_GPIO20_INT, mmc_host); + return ret; +} + +static int db1100_mmc_card_readonly(void *mmc_host) +{ + /* testing suggests that this bit is inverted */ + return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1; +} + +static int db1100_mmc_card_inserted(void *mmc_host) +{ + return !alchemy_gpio_get_value(19); +} + +static void db1100_mmc_set_power(void *mmc_host, int state) +{ + if (state) { + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); + msleep(400); /* stabilization time */ + } else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); +} + +static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b) +{ + if (b != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); +} + +static struct led_classdev db1100_mmc_led = { + .brightness_set = db1100_mmcled_set, +}; + +static int db1100_mmc1_card_readonly(void *mmc_host) +{ + return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0; +} + +static int db1100_mmc1_card_inserted(void *mmc_host) +{ + return !alchemy_gpio_get_value(20); +} + +static void db1100_mmc1_set_power(void *mmc_host, int state) +{ + if (state) { + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); + msleep(400); /* stabilization time */ + } else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); +} + +static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b) +{ + if (b != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); +} + +static struct led_classdev db1100_mmc1_led = { + .brightness_set = db1100_mmc1led_set, +}; + +static struct au1xmmc_platform_data db1100_mmc_platdata[2] = { + [0] = { + .cd_setup = db1100_mmc_cd_setup, + .set_power = db1100_mmc_set_power, + .card_inserted = db1100_mmc_card_inserted, + .card_readonly = db1100_mmc_card_readonly, + .led = &db1100_mmc_led, + }, + [1] = { + .cd_setup = db1100_mmc1_cd_setup, + .set_power = db1100_mmc1_set_power, + .card_inserted = db1100_mmc1_card_inserted, + .card_readonly = db1100_mmc1_card_readonly, + .led = &db1100_mmc1_led, + }, +}; + +static struct resource au1100_mmc0_resources[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_SD_INT, + .end = AU1100_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DMA_ID_SD0_TX, + .end = DMA_ID_SD0_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMA_ID_SD0_RX, + .end = DMA_ID_SD0_RX, + .flags = IORESOURCE_DMA, + } +}; + +static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1100_mmc0_dev = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1100_mmc_platdata[0], + }, + .num_resources = ARRAY_SIZE(au1100_mmc0_resources), + .resource = au1100_mmc0_resources, +}; + +static struct resource au1100_mmc1_res[] = { + [0] = { + .start = AU1100_SD1_PHYS_ADDR, + .end = AU1100_SD1_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_SD_INT, + .end = AU1100_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DMA_ID_SD1_TX, + .end = DMA_ID_SD1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMA_ID_SD1_RX, + .end = DMA_ID_SD1_RX, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device db1100_mmc1_dev = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1100_mmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1100_mmc1_res), + .resource = au1100_mmc1_res, +}; + + static struct platform_device *db1x00_devs[] = { &db1x00_codec_dev, &alchemy_ac97c_dma_dev, @@ -203,6 +399,8 @@ static struct platform_device *db1x00_devs[] = { static struct platform_device *db1100_devs[] = { &au1100_lcd_device, + &db1100_mmc0_dev, + &db1100_mmc1_dev, }; static int __init db1000_dev_init(void) @@ -224,6 +422,10 @@ static int __init db1000_dev_init(void) d1 = AU1100_GPIO3_INT; s0 = AU1100_GPIO1_INT; s1 = AU1100_GPIO4_INT; + + gpio_direction_input(19); /* sd0 cd# */ + gpio_direction_input(20); /* sd1 cd# */ + platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); } else if (board == BCSR_WHOAMI_DB1000) { c0 = AU1000_GPIO2_INT; From 1c043f16a01c144305e952025e883b55706f2450 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:22 +0000 Subject: [PATCH 016/119] MIPS: Alchemy: Add RTC device to all devboards All Devboards can use the 32kHz counter as a RTC device. Also delete the custom CMOS RTC header, which can be used for the DS1693 on the PB1500. But since it doesn't have a buffer battery it is as useful as the on-chip RTC which I prefer. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2874/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/db1200.c | 8 ----- arch/mips/alchemy/devboards/db1300.c | 8 ----- arch/mips/alchemy/devboards/db1550.c | 8 ----- arch/mips/alchemy/devboards/platform.c | 13 +++++-- .../include/asm/mach-pb1x00/mc146818rtc.h | 34 ------------------- 5 files changed, 11 insertions(+), 60 deletions(-) delete mode 100644 arch/mips/include/asm/mach-pb1x00/mc146818rtc.h diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index ec481f33aecc..1181241c5052 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -312,13 +312,6 @@ static struct platform_device db1200_ide_dev = { /**********************************************************************/ -static struct platform_device db1200_rtc_dev = { - .name = "rtc-au1xxx", - .id = -1, -}; - -/**********************************************************************/ - /* SD carddetects: they're supposed to be edge-triggered, but ack * doesn't seem to work (CPLD Rev 2). Instead, the screaming one * is disabled and its counterpart enabled. The 500ms timeout is @@ -755,7 +748,6 @@ static struct platform_device *db1200_devs[] __initdata = { &db1200_mmc0_dev, &au1200_lcd_dev, &db1200_eth_dev, - &db1200_rtc_dev, &db1200_nand_dev, &db1200_audiodma_dev, &db1200_audio_dev, diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index 7f3dacb60ea5..0893f2af0d01 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -386,13 +386,6 @@ static struct platform_device db1300_5waysw_dev = { /**********************************************************************/ -static struct platform_device db1300_rtc_dev = { - .name = "rtc-au1xxx", - .id = -1, -}; - -/**********************************************************************/ - static struct pata_platform_info db1300_ide_info = { .ioport_shift = DB1300_IDE_REG_SHIFT, }; @@ -697,7 +690,6 @@ static struct platform_device *db1300_dev[] __initdata = { &db1300_eth_dev, &db1300_i2c_dev, &db1300_5waysw_dev, - &db1300_rtc_dev, &db1300_nand_dev, &db1300_ide_dev, &db1300_sd0_dev, diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c index a4755b0570a1..6815d0783cd8 100644 --- a/arch/mips/alchemy/devboards/db1550.c +++ b/arch/mips/alchemy/devboards/db1550.c @@ -372,13 +372,6 @@ static struct platform_device db1550_sndi2s_dev = { /**********************************************************************/ -static struct platform_device db1550_rtc_dev = { - .name = "rtc-au1xxx", - .id = -1, -}; - -/**********************************************************************/ - static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) { if ((slot < 11) || (slot > 13) || pin == 0) @@ -427,7 +420,6 @@ static struct platform_device db1550_pci_host_dev = { /**********************************************************************/ static struct platform_device *db1550_devs[] __initdata = { - &db1550_rtc_dev, &db1550_nand_dev, &db1550_i2c_dev, &db1550_ac97_dev, diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c index 49a4b3244d8e..621f70afb63a 100644 --- a/arch/mips/alchemy/devboards/platform.c +++ b/arch/mips/alchemy/devboards/platform.c @@ -13,6 +13,13 @@ #include #include + +static struct platform_device db1x00_rtc_dev = { + .name = "rtc-au1xxx", + .id = -1, +}; + + static void db1x_power_off(void) { bcsr_write(BCSR_RESETS, 0); @@ -25,7 +32,7 @@ static void db1x_reset(char *c) bcsr_write(BCSR_SYSTEM, 0); } -static int __init db1x_poweroff_setup(void) +static int __init db1x_late_setup(void) { if (!pm_power_off) pm_power_off = db1x_power_off; @@ -34,9 +41,11 @@ static int __init db1x_poweroff_setup(void) if (!_machine_restart) _machine_restart = db1x_reset; + platform_device_register(&db1x00_rtc_dev); + return 0; } -late_initcall(db1x_poweroff_setup); +device_initcall(db1x_late_setup); /* register a pcmcia socket */ int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start, diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h deleted file mode 100644 index 622c58710e5b..000000000000 --- a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_AU1XX_MC146818RTC_H -#define __ASM_MACH_AU1XX_MC146818RTC_H - -#include -#include - -#define RTC_PORT(x) (0x0c000000 + (x)) -#define RTC_IRQ 8 -#define PB1500_RTC_ADDR 0x0c000000 - -static inline unsigned char CMOS_READ(unsigned long offset) -{ - offset <<= 2; - return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long offset) -{ - offset <<= 2; - au_writel(data, offset + PB1500_RTC_ADDR); -} - -#define RTC_ALWAYS_BCD 1 - -#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */ From edc9ded191f7075f2d9e7aa3c9e84c48bc4338b2 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 15 Nov 2011 20:23:43 +0100 Subject: [PATCH 017/119] MIPS: AR7: constify some arrays in gpio and prom code Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2980/ Signed-off-by: Ralf Baechle --- arch/mips/ar7/gpio.c | 2 +- arch/mips/ar7/prom.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c index bb571bcdb8f2..d8dbd8f0c1d2 100644 --- a/arch/mips/ar7/gpio.c +++ b/arch/mips/ar7/gpio.c @@ -217,7 +217,7 @@ struct titan_gpio_cfg { u32 func; }; -static struct titan_gpio_cfg titan_gpio_table[] = { +static const struct titan_gpio_cfg titan_gpio_table[] = { /* reg, start bit, mux value */ {4, 24, 1}, {4, 26, 1}, diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c index 8088c6fdb83e..a23adc49d50f 100644 --- a/arch/mips/ar7/prom.c +++ b/arch/mips/ar7/prom.c @@ -69,7 +69,7 @@ struct psbl_rec { u32 ffs_size; }; -static __initdata char psp_env_version[] = "TIENV0.8"; +static const char psp_env_version[] __initconst = "TIENV0.8"; struct psp_env_chunk { u8 num; @@ -84,7 +84,7 @@ struct psp_var_map_entry { char *value; }; -static struct psp_var_map_entry psp_var_map[] = { +static const struct psp_var_map_entry psp_var_map[] = { { 1, "cpufrequency" }, { 2, "memsize" }, { 3, "flashsize" }, From f77138e8d53a7a4a539f8d931107991d91727afd Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 15 Nov 2011 20:23:44 +0100 Subject: [PATCH 018/119] MIPS: AR7: add LEDs layout for the Actiontec GT701 router Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2981/ Signed-off-by: Ralf Baechle --- arch/mips/ar7/platform.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 33ffecf6a6d6..e5f6fca690e1 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -462,6 +462,40 @@ static struct gpio_led fb_fon_leds[] = { }, }; +static struct gpio_led gt701_leds[] = { + { + .name = "inet:green", + .gpio = 13, + .active_low = 1, + }, + { + .name = "usb", + .gpio = 12, + .active_low = 1, + }, + { + .name = "inet:red", + .gpio = 9, + .active_low = 1, + }, + { + .name = "power:red", + .gpio = 7, + .active_low = 1, + }, + { + .name = "power:green", + .gpio = 8, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "ethernet", + .gpio = 10, + .active_low = 1, + }, +}; + static struct gpio_led_platform_data ar7_led_data; static struct platform_device ar7_gpio_leds = { @@ -503,6 +537,9 @@ static void __init detect_leds(void) } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) { ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); ar7_led_data.leds = titan_leds; + } else if (strstr(prid, "GT701")) { + ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds); + ar7_led_data.leds = gt701_leds; } } From 2f8501b9b81b23e99206e31b3eff65e68b56b24b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Sun, 5 Jun 2011 23:38:44 +0200 Subject: [PATCH 019/119] MIPS: ath79: Change number of available IRQs The status register of the miscellaneous interrupt controller is 32 bits wide, but the actual value of NR_IRQS covers only 8 of them. Change NR_IRQS in order to make all of those interrupt lines usable. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2441/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-ath79/irq.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 189bc6eb9c10..cffbeab57a74 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -10,10 +10,10 @@ #define __ASM_MACH_ATH79_IRQ_H #define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 16 +#define NR_IRQS 40 #define ATH79_MISC_IRQ_BASE 8 -#define ATH79_MISC_IRQ_COUNT 8 +#define ATH79_MISC_IRQ_COUNT 32 #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) From d2b4ac1e5d34648cc56785f6bd11bfa020ad4f02 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Sun, 5 Jun 2011 23:38:45 +0200 Subject: [PATCH 020/119] MIPS: ath79: Handle more MISC IRQs The AR724X SoCs have more IRQ sources hooked into the MISC IRQ controller. The patch adds support for them. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2440/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/irq.c | 12 ++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++++ arch/mips/include/asm/mach-ath79/irq.h | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index ac610d5fe3ba..0d98114cbf4d 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) else if (pending & MISC_INT_TIMER) generic_handle_irq(ATH79_MISC_IRQ_TIMER); + else if (pending & MISC_INT_TIMER2) + generic_handle_irq(ATH79_MISC_IRQ_TIMER2); + + else if (pending & MISC_INT_TIMER3) + generic_handle_irq(ATH79_MISC_IRQ_TIMER3); + + else if (pending & MISC_INT_TIMER4) + generic_handle_irq(ATH79_MISC_IRQ_TIMER4); + else if (pending & MISC_INT_OHCI) generic_handle_irq(ATH79_MISC_IRQ_OHCI); @@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) else if (pending & MISC_INT_WDOG) generic_handle_irq(ATH79_MISC_IRQ_WDOG); + else if (pending & MISC_INT_ETHSW) + generic_handle_irq(ATH79_MISC_IRQ_ETHSW); + else spurious_interrupt(); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index cda1c8070b27..da0d89478259 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -130,6 +130,10 @@ #define AR724X_RESET_REG_RESET_MODULE 0x1c +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) #define MISC_INT_DMA BIT(7) #define MISC_INT_OHCI BIT(6) #define MISC_INT_PERFC BIT(5) diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index cffbeab57a74..519958fe4e3c 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -30,6 +30,10 @@ #define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) #define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) #define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) +#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8) +#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9) +#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10) +#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12) #include_next From 7e98aa4639cba9ef5c99b1484bc86ddb04f67b80 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Sun, 5 Jun 2011 23:38:46 +0200 Subject: [PATCH 021/119] MIPS: ath79: add common USB Host Controller device Add common platform_device and helper code to make the registration of the built-in USB controllers easier on the board which are using them. Also register the USB controller on the AP81 and PB44 boards. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2442/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/Kconfig | 5 + arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-usb.c | 178 ++++++++++++++++++ arch/mips/ath79/dev-usb.h | 17 ++ arch/mips/ath79/mach-ap81.c | 2 + arch/mips/ath79/mach-pb44.c | 2 + .../mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++- 7 files changed, 236 insertions(+), 1 deletion(-) create mode 100644 arch/mips/ath79/dev-usb.c create mode 100644 arch/mips/ath79/dev-usb.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 47707410582c..af01669ba665 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -9,6 +9,7 @@ config ATH79_MACH_AP81 select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO select ATH79_DEV_SPI + select ATH79_DEV_USB help Say 'Y' here if you want your kernel to support the Atheros AP81 reference board. @@ -19,6 +20,7 @@ config ATH79_MACH_PB44 select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO select ATH79_DEV_SPI + select ATH79_DEV_USB help Say 'Y' here if you want your kernel to support the Atheros PB44 reference board. @@ -52,4 +54,7 @@ config ATH79_DEV_LEDS_GPIO config ATH79_DEV_SPI def_bool n +config ATH79_DEV_USB + def_bool n + endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index c33d4653007c..57188b61b9ae 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o +obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o # # Machines diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c new file mode 100644 index 000000000000..c3f1999c761b --- /dev/null +++ b/arch/mips/ath79/dev-usb.c @@ -0,0 +1,178 @@ +/* + * Atheros AR7XXX/AR9XXX USB Host Controller device + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include "common.h" +#include "dev-usb.h" + +static struct resource ath79_ohci_resources[] = { + [0] = { + /* .start and .end fields are filled dynamically */ + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_MISC_IRQ_OHCI, + .end = ATH79_MISC_IRQ_OHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); +static struct platform_device ath79_ohci_device = { + .name = "ath79-ohci", + .id = -1, + .resource = ath79_ohci_resources, + .num_resources = ARRAY_SIZE(ath79_ohci_resources), + .dev = { + .dma_mask = &ath79_ohci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource ath79_ehci_resources[] = { + [0] = { + /* .start and .end fields are filled dynamically */ + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_CPU_IRQ_USB, + .end = ATH79_CPU_IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); +static struct platform_device ath79_ehci_device = { + .name = "ath79-ehci", + .id = -1, + .resource = ath79_ehci_resources, + .num_resources = ARRAY_SIZE(ath79_ehci_resources), + .dev = { + .dma_mask = &ath79_ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ + AR71XX_RESET_USB_PHY | \ + AR71XX_RESET_USB_OHCI_DLL) + +static void __init ath79_usb_setup(void) +{ + void __iomem *usb_ctrl_base; + + ath79_device_reset_set(AR71XX_USB_RESET_MASK); + mdelay(1000); + ath79_device_reset_clear(AR71XX_USB_RESET_MASK); + + usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE); + + /* Turning on the Buff and Desc swap bits */ + __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG); + + /* WAR for HW bug. Here it adjusts the duration between two SOFS */ + __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); + + iounmap(usb_ctrl_base); + + mdelay(900); + + ath79_ohci_resources[0].start = AR71XX_OHCI_BASE; + ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1; + platform_device_register(&ath79_ohci_device); + + ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; + ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; + ath79_ehci_device.name = "ar71xx-ehci"; + platform_device_register(&ath79_ehci_device); +} + +static void __init ar7240_usb_setup(void) +{ + void __iomem *usb_ctrl_base; + + ath79_device_reset_clear(AR7240_RESET_OHCI_DLL); + ath79_device_reset_set(AR7240_RESET_USB_HOST); + + mdelay(1000); + + ath79_device_reset_set(AR7240_RESET_OHCI_DLL); + ath79_device_reset_clear(AR7240_RESET_USB_HOST); + + usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE); + + /* WAR for HW bug. Here it adjusts the duration between two SOFS */ + __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); + + iounmap(usb_ctrl_base); + + ath79_ohci_resources[0].start = AR7240_OHCI_BASE; + ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; + platform_device_register(&ath79_ohci_device); +} + +static void __init ar724x_usb_setup(void) +{ + ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE); + mdelay(10); + + ath79_device_reset_clear(AR724X_RESET_USB_HOST); + mdelay(10); + + ath79_device_reset_clear(AR724X_RESET_USB_PHY); + mdelay(10); + + ath79_ehci_resources[0].start = AR724X_EHCI_BASE; + ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; + ath79_ehci_device.name = "ar724x-ehci"; + platform_device_register(&ath79_ehci_device); +} + +static void __init ar913x_usb_setup(void) +{ + ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE); + mdelay(10); + + ath79_device_reset_clear(AR913X_RESET_USB_HOST); + mdelay(10); + + ath79_device_reset_clear(AR913X_RESET_USB_PHY); + mdelay(10); + + ath79_ehci_resources[0].start = AR913X_EHCI_BASE; + ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; + ath79_ehci_device.name = "ar913x-ehci"; + platform_device_register(&ath79_ehci_device); +} + +void __init ath79_register_usb(void) +{ + if (soc_is_ar71xx()) + ath79_usb_setup(); + else if (soc_is_ar7240()) + ar7240_usb_setup(); + else if (soc_is_ar7241() || soc_is_ar7242()) + ar724x_usb_setup(); + else if (soc_is_ar913x()) + ar913x_usb_setup(); + else + BUG(); +} diff --git a/arch/mips/ath79/dev-usb.h b/arch/mips/ath79/dev-usb.h new file mode 100644 index 000000000000..4b86a69ca080 --- /dev/null +++ b/arch/mips/ath79/dev-usb.h @@ -0,0 +1,17 @@ +/* + * Atheros AR71XX/AR724X/AR913X USB Host Controller support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_USB_H +#define _ATH79_DEV_USB_H + +void ath79_register_usb(void); + +#endif /* _ATH79_DEV_USB_H */ diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c index eee4c121deb4..6c0826736012 100644 --- a/arch/mips/ath79/mach-ap81.c +++ b/arch/mips/ath79/mach-ap81.c @@ -14,6 +14,7 @@ #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" +#include "dev-usb.h" #define AP81_GPIO_LED_STATUS 1 #define AP81_GPIO_LED_AOSS 3 @@ -92,6 +93,7 @@ static void __init ap81_setup(void) ath79_register_spi(&ap81_spi_data, ap81_spi_info, ARRAY_SIZE(ap81_spi_info)); ath79_register_ar913x_wmac(cal_data); + ath79_register_usb(); } MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index ec7b7a135d53..fe9701a32291 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -18,6 +18,7 @@ #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" +#include "dev-usb.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 @@ -112,6 +113,7 @@ static void __init pb44_init(void) pb44_gpio_keys); ath79_register_spi(&pb44_spi_data, pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); + ath79_register_usb(); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index da0d89478259..86f0fc8c07c1 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -20,6 +20,10 @@ #include #define AR71XX_APB_BASE 0x18000000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 #define AR71XX_SPI_BASE 0x1f000000 #define AR71XX_SPI_SIZE 0x01000000 @@ -27,6 +31,8 @@ #define AR71XX_DDR_CTRL_SIZE 0x100 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) #define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) @@ -34,6 +40,16 @@ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) #define AR71XX_RESET_SIZE 0x100 +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) #define AR913X_WMAC_SIZE 0x30000 @@ -104,6 +120,12 @@ #define AR913X_AHB_DIV_SHIFT 19 #define AR913X_AHB_DIV_MASK 0x1 +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + /* * RESET block */ @@ -162,14 +184,22 @@ #define AR71XX_RESET_PCI_BUS BIT(1) #define AR71XX_RESET_PCI_CORE BIT(0) +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + #define AR724X_RESET_GE1_MDIO BIT(23) #define AR724X_RESET_GE0_MDIO BIT(22) #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) #define AR724X_RESET_PCIE_PHY BIT(7) #define AR724X_RESET_PCIE BIT(6) -#define AR724X_RESET_OHCI_DLL BIT(3) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) #define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) #define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_AR71XX 0x00a0 From 8bed1288d479fd118d30666de53dfba8044f789f Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:01 +0200 Subject: [PATCH 022/119] MIPS: ath79: Remove superfluous parentheses Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2519/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/setup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 159b42f106b0..dea5af1a3694 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -101,19 +101,19 @@ static void __init ath79_detect_sys_type(void) case REV_ID_MAJOR_AR7240: ath79_soc = ATH79_SOC_AR7240; chip = "7240"; - rev = (id & AR724X_REV_ID_REVISION_MASK); + rev = id & AR724X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR7241: ath79_soc = ATH79_SOC_AR7241; chip = "7241"; - rev = (id & AR724X_REV_ID_REVISION_MASK); + rev = id & AR724X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR7242: ath79_soc = ATH79_SOC_AR7242; chip = "7242"; - rev = (id & AR724X_REV_ID_REVISION_MASK); + rev = id & AR724X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR913X: From 6d1c8fde2daa498fa6ddf8916bcfc5aee1bbe51b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 23 Jun 2011 18:13:14 +0200 Subject: [PATCH 023/119] MIPS: ath79: add revision id for the AR933X SoCs Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2538/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/setup.c | 12 ++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++++ arch/mips/include/asm/mach-ath79/ath79.h | 4 +++- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index dea5af1a3694..4187a1122048 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -116,6 +116,18 @@ static void __init ath79_detect_sys_type(void) rev = id & AR724X_REV_ID_REVISION_MASK; break; + case REV_ID_MAJOR_AR9330: + ath79_soc = ATH79_SOC_AR9330; + chip = "9330"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9331: + ath79_soc = ATH79_SOC_AR9331; + chip = "9331"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + case REV_ID_MAJOR_AR913X: minor = id & AR913X_REV_ID_MINOR_MASK; rev = id >> AR913X_REV_ID_REVISION_SHIFT; diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 86f0fc8c07c1..929be06e1475 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -207,6 +207,8 @@ #define REV_ID_MAJOR_AR7240 0x00c0 #define REV_ID_MAJOR_AR7241 0x0100 #define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 @@ -221,6 +223,8 @@ #define AR913X_REV_ID_REVISION_MASK 0x3 #define AR913X_REV_ID_REVISION_SHIFT 2 +#define AR933X_REV_ID_REVISION_MASK 0x3 + #define AR724X_REV_ID_REVISION_MASK 0x3 /* diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h index 6a9f168506fe..2dfc94c0444b 100644 --- a/arch/mips/include/asm/mach-ath79/ath79.h +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -26,7 +26,9 @@ enum ath79_soc_type { ATH79_SOC_AR7241, ATH79_SOC_AR7242, ATH79_SOC_AR9130, - ATH79_SOC_AR9132 + ATH79_SOC_AR9132, + ATH79_SOC_AR9330, + ATH79_SOC_AR9331, }; extern enum ath79_soc_type ath79_soc; From 0bd3acdf7d559c8289de73c4c711fd2381e6c7ad Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:03 +0200 Subject: [PATCH 024/119] MIPS: ath79: Add early printk support for the AR933X SoCs The AR933X SoCs are using a different UART, thus require different code for early printk support. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2521/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/early_printk.c | 76 ++++++++++++++++--- .../mips/include/asm/mach-ath79/ar71xx_regs.h | 3 + .../mips/include/asm/mach-ath79/ar933x_uart.h | 67 ++++++++++++++++ 3 files changed, 137 insertions(+), 9 deletions(-) create mode 100644 arch/mips/include/asm/mach-ath79/ar933x_uart.h diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c index 7499b0e9df26..6a51ced7a293 100644 --- a/arch/mips/ath79/early_printk.c +++ b/arch/mips/ath79/early_printk.c @@ -1,7 +1,7 @@ /* - * Atheros AR71XX/AR724X/AR913X SoC early printk support + * Atheros AR7XXX/AR9XXX SoC early printk support * - * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * * This program is free software; you can redistribute it and/or modify it @@ -10,27 +10,85 @@ */ #include +#include #include #include +#include #include +#include -static inline void prom_wait_thre(void __iomem *base) +static void (*_prom_putchar) (unsigned char); + +static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) { - u32 lsr; + u32 t; do { - lsr = __raw_readl(base + UART_LSR * 4); - if (lsr & UART_LSR_THRE) + t = __raw_readl(reg); + if ((t & mask) == val) break; } while (1); } -void prom_putchar(unsigned char ch) +static void prom_putchar_ar71xx(unsigned char ch) { void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); - prom_wait_thre(base); + prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); __raw_writel(ch, base + UART_TX * 4); - prom_wait_thre(base); + prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); +} + +static void prom_putchar_ar933x(unsigned char ch) +{ + void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); + + prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, + AR933X_UART_DATA_TX_CSR); + __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG); + prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, + AR933X_UART_DATA_TX_CSR); +} + +static void prom_putchar_dummy(unsigned char ch) +{ + /* nothing to do */ +} + +static void prom_putchar_init(void) +{ + void __iomem *base; + u32 id; + + base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE)); + id = __raw_readl(base + AR71XX_RESET_REG_REV_ID); + id &= REV_ID_MAJOR_MASK; + + switch (id) { + case REV_ID_MAJOR_AR71XX: + case REV_ID_MAJOR_AR7240: + case REV_ID_MAJOR_AR7241: + case REV_ID_MAJOR_AR7242: + case REV_ID_MAJOR_AR913X: + _prom_putchar = prom_putchar_ar71xx; + break; + + case REV_ID_MAJOR_AR9330: + case REV_ID_MAJOR_AR9331: + _prom_putchar = prom_putchar_ar933x; + break; + + default: + _prom_putchar = prom_putchar_dummy; + break; + } +} + +void prom_putchar(unsigned char ch) +{ + if (!_prom_putchar) + prom_putchar_init(); + + _prom_putchar(ch); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 929be06e1475..90223f206610 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -53,6 +53,9 @@ #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) #define AR913X_WMAC_SIZE 0x30000 +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 + /* * DDR_CTRL block */ diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h new file mode 100644 index 000000000000..52730555937f --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h @@ -0,0 +1,67 @@ +/* + * Atheros AR933X UART defines + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __AR933X_UART_H +#define __AR933X_UART_H + +#define AR933X_UART_REGS_SIZE 20 +#define AR933X_UART_FIFO_SIZE 16 + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLOCK_REG 0x08 +#define AR933X_UART_INT_REG 0x0c +#define AR933X_UART_INT_EN_REG 0x10 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) + +#define AR933X_UART_CS_PARITY_S 0 +#define AR933X_UART_CS_PARITY_M 0x3 +#define AR933X_UART_CS_PARITY_NONE 0 +#define AR933X_UART_CS_PARITY_ODD 1 +#define AR933X_UART_CS_PARITY_EVEN 2 +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_NONE 0 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_FLOW_CTRL_S 4 +#define AR933X_UART_CS_FLOW_CTRL_M 0x3 +#define AR933X_UART_CS_DMA_EN BIT(6) +#define AR933X_UART_CS_TX_READY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_READY_ORIDE BIT(8) +#define AR933X_UART_CS_TX_READY BIT(9) +#define AR933X_UART_CS_RX_BREAK BIT(10) +#define AR933X_UART_CS_TX_BREAK BIT(11) +#define AR933X_UART_CS_HOST_INT BIT(12) +#define AR933X_UART_CS_HOST_INT_EN BIT(13) +#define AR933X_UART_CS_TX_BUSY BIT(14) +#define AR933X_UART_CS_RX_BUSY BIT(15) + +#define AR933X_UART_CLOCK_STEP_M 0xffff +#define AR933X_UART_CLOCK_SCALE_M 0xfff +#define AR933X_UART_CLOCK_SCALE_S 16 +#define AR933X_UART_CLOCK_STEP_M 0xffff + +#define AR933X_UART_INT_RX_VALID BIT(0) +#define AR933X_UART_INT_TX_READY BIT(1) +#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) +#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) +#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) +#define AR933X_UART_INT_RX_PARITY_ERR BIT(5) +#define AR933X_UART_INT_RX_BREAK_ON BIT(6) +#define AR933X_UART_INT_RX_BREAK_OFF BIT(7) +#define AR933X_UART_INT_RX_FULL BIT(8) +#define AR933X_UART_INT_TX_EMPTY BIT(9) +#define AR933X_UART_INT_ALLINTS 0x3ff + +#endif /* __AR933X_UART_H */ From 04225e1d227c8e68d685936ecf42ac175fec0e54 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:04 +0200 Subject: [PATCH 025/119] MIPS: ath79: add AR933X specific clock init Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2522/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/clock.c | 55 +++++++++++++++++++ .../mips/include/asm/mach-ath79/ar71xx_regs.h | 22 ++++++++ arch/mips/include/asm/mach-ath79/ath79.h | 6 ++ 3 files changed, 83 insertions(+) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index 680bde99a26c..54d0eb4db987 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(void) ath79_uart_clk.rate = ath79_ahb_clk.rate; } +static void __init ar933x_clocks_init(void) +{ + u32 clock_ctrl; + u32 cpu_config; + u32 freq; + u32 t; + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + if (t & AR933X_BOOTSTRAP_REF_CLK_40) + ath79_ref_clk.rate = (40 * 1000 * 1000); + else + ath79_ref_clk.rate = (25 * 1000 * 1000); + + clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); + if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { + ath79_cpu_clk.rate = ath79_ref_clk.rate; + ath79_ahb_clk.rate = ath79_ref_clk.rate; + ath79_ddr_clk.rate = ath79_ref_clk.rate; + } else { + cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG); + + t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + AR933X_PLL_CPU_CONFIG_REFDIV_MASK; + freq = ath79_ref_clk.rate / t; + + t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & + AR933X_PLL_CPU_CONFIG_NINT_MASK; + freq *= t; + + t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; + if (t == 0) + t = 1; + + freq >>= t; + + t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & + AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; + ath79_cpu_clk.rate = freq / t; + + t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & + AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; + ath79_ddr_clk.rate = freq / t; + + t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & + AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; + ath79_ahb_clk.rate = freq / t; + } + + ath79_wdt_clk.rate = ath79_ref_clk.rate; + ath79_uart_clk.rate = ath79_ref_clk.rate; +} + void __init ath79_clocks_init(void) { if (soc_is_ar71xx()) @@ -118,6 +171,8 @@ void __init ath79_clocks_init(void) ar724x_clocks_init(); else if (soc_is_ar913x()) ar913x_clocks_init(); + else if (soc_is_ar933x()) + ar933x_clocks_init(); else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 90223f206610..418b7392e8c3 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -123,6 +123,24 @@ #define AR913X_AHB_DIV_SHIFT 19 #define AR913X_AHB_DIV_MASK 0x1 +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + /* * USB_CONFIG block */ @@ -155,6 +173,8 @@ #define AR724X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) #define MISC_INT_TIMER3 BIT(9) @@ -204,6 +224,8 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + #define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_AR71XX 0x00a0 #define REV_ID_MAJOR_AR913X 0x00b0 diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h index 2dfc94c0444b..407c9354f747 100644 --- a/arch/mips/include/asm/mach-ath79/ath79.h +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -68,6 +68,12 @@ static inline int soc_is_ar913x(void) ath79_soc == ATH79_SOC_AR9132); } +static inline int soc_is_ar933x(void) +{ + return (ath79_soc == ATH79_SOC_AR9330 || + ath79_soc == ATH79_SOC_AR9331); +} + extern void __iomem *ath79_ddr_base; extern void __iomem *ath79_pll_base; extern void __iomem *ath79_reset_base; From 7ee15d8a2837841d75f56319b94510ed950094b5 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:05 +0200 Subject: [PATCH 026/119] MIPS: ath79: Add AR933X specific glue for ath79_device_reset_{set,clear} Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2523/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/common.c | 4 ++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index 58f60e722a03..38c2ad7bd871 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -64,6 +64,8 @@ void ath79_device_reset_set(u32 mask) reg = AR724X_RESET_REG_RESET_MODULE; else if (soc_is_ar913x()) reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; else BUG(); @@ -86,6 +88,8 @@ void ath79_device_reset_clear(u32 mask) reg = AR724X_RESET_REG_RESET_MODULE; else if (soc_is_ar913x()) reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 418b7392e8c3..c7159e3479c2 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -173,6 +173,7 @@ #define AR724X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_RESET_MODULE 0x1c #define AR933X_RESET_REG_BOOTSTRAP 0xac #define MISC_INT_ETHSW BIT(12) From 54eed4c77ca1d02228f07bee74a1afe081393ab0 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:06 +0200 Subject: [PATCH 027/119] MIPS: ath79: Add AR933X specific IRQ initialization Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2530/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/irq.c | 5 ++++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 5 +++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index 0d98114cbf4d..1b073de44680 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -129,7 +129,7 @@ static void __init ath79_misc_irq_init(void) if (soc_is_ar71xx() || soc_is_ar913x()) ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; - else if (soc_is_ar724x()) + else if (soc_is_ar724x() || soc_is_ar933x()) ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; else BUG(); @@ -186,6 +186,9 @@ void __init arch_init_irq(void) } else if (soc_is_ar913x()) { ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; + } else if (soc_is_ar933x()) { + ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC; + ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB; } else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index c7159e3479c2..9c76185801d0 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -82,6 +82,11 @@ #define AR913X_DDR_REG_FLUSH_USB 0x84 #define AR913X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 + /* * PLL block */ From fdfbcf4705e0b01d90112d6cfa5deec6484ec11b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:07 +0200 Subject: [PATCH 028/119] MIPS: ath79: add AR933X specific GPIO initialization Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2524/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/gpio.c | 2 ++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c index a0c426b82123..a2f8ca630ed6 100644 --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c @@ -153,6 +153,8 @@ void __init ath79_gpio_init(void) ath79_gpio_count = AR724X_GPIO_COUNT; else if (soc_is_ar913x()) ath79_gpio_count = AR913X_GPIO_COUNT; + else if (soc_is_ar933x()) + ath79_gpio_count = AR933X_GPIO_COUNT; else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 9c76185801d0..e65c10dd159b 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -298,5 +298,6 @@ #define AR71XX_GPIO_COUNT 16 #define AR724X_GPIO_COUNT 18 #define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 #endif /* __ASM_MACH_AR71XX_REGS_H */ From 2c048303d6fac960dc2deaeae764a3403aa97f3b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:08 +0200 Subject: [PATCH 029/119] MIPS: ath79: Add config symbol for the AR933X SoCs Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2525/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index af01669ba665..90edf27609e8 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -41,6 +41,9 @@ config SOC_AR913X select USB_ARCH_HAS_EHCI def_bool n +config SOC_AR933X + def_bool n + config ATH79_DEV_AR913X_WMAC depends on SOC_AR913X def_bool n From 9d6b204f93cfeb7ec5e6ec499aca43d2c1d6da3f Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:09 +0200 Subject: [PATCH 030/119] USB: ehci-ath79: Add device_id entry for the AR933X SoCs Also make the USB_EHCI_ATH79 selectable for the AR933X SoCs. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2529/ Signed-off-by: Ralf Baechle --- drivers/usb/host/Kconfig | 2 +- drivers/usb/host/ehci-ath79.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 060e0e2b1ae6..8b094b4f6531 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI config USB_EHCI_ATH79 bool "EHCI support for AR7XXX/AR9XXX SoCs" - depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X) + depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) select USB_EHCI_ROOT_HUB_TT default y ---help--- diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c index afb6743cf094..f1424f9bc363 100644 --- a/drivers/usb/host/ehci-ath79.c +++ b/drivers/usb/host/ehci-ath79.c @@ -32,6 +32,10 @@ static const struct platform_device_id ehci_ath79_id_table[] = { .name = "ar913x-ehci", .driver_data = EHCI_ATH79_IP_V2, }, + { + .name = "ar933x-ehci", + .driver_data = EHCI_ATH79_IP_V2, + }, { /* terminating entry */ }, From c279b7759602d4ef97d45f3eb2cdf36a713eb99a Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:10 +0200 Subject: [PATCH 031/119] MIPS: ath79: add AR933X specific USB platform device registration Also select the USB_ARCH_HAS_EHCI symbol in order to make the EHCI driver available. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2527/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/Kconfig | 1 + arch/mips/ath79/dev-usb.c | 19 +++++++++++++++++++ .../mips/include/asm/mach-ath79/ar71xx_regs.h | 7 +++++++ 3 files changed, 27 insertions(+) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 90edf27609e8..c3680c83a102 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -42,6 +42,7 @@ config SOC_AR913X def_bool n config SOC_AR933X + select USB_ARCH_HAS_EHCI def_bool n config ATH79_DEV_AR913X_WMAC diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index c3f1999c761b..002d6d2afe04 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -163,6 +163,23 @@ static void __init ar913x_usb_setup(void) platform_device_register(&ath79_ehci_device); } +static void __init ar933x_usb_setup(void) +{ + ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE); + mdelay(10); + + ath79_device_reset_clear(AR933X_RESET_USB_HOST); + mdelay(10); + + ath79_device_reset_clear(AR933X_RESET_USB_PHY); + mdelay(10); + + ath79_ehci_resources[0].start = AR933X_EHCI_BASE; + ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; + ath79_ehci_device.name = "ar933x-ehci"; + platform_device_register(&ath79_ehci_device); +} + void __init ath79_register_usb(void) { if (soc_is_ar71xx()) @@ -173,6 +190,8 @@ void __init ath79_register_usb(void) ar724x_usb_setup(); else if (soc_is_ar913x()) ar913x_usb_setup(); + else if (soc_is_ar933x()) + ar933x_usb_setup(); else BUG(); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index e65c10dd159b..733bacace778 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -56,6 +56,9 @@ #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR933X_UART_SIZE 0x14 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 + /* * DDR_CTRL block */ @@ -230,6 +233,10 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define REV_ID_MAJOR_MASK 0xfff0 From d57f341ba08c9f34ccd45a89729e73174d4a3325 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 19:26:11 +0200 Subject: [PATCH 032/119] SERIAL: AR933X: Add driver for the built-in UART of the SoC This patch adds the driver for the built-in UART of the Atheros AR933X SoCs. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Cc: Alan Cox Cc: linux-serial@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2526/ Signed-off-by: Alan Cox Signed-off-by: Ralf Baechle --- .../asm/mach-ath79/ar933x_uart_platform.h | 18 + drivers/tty/serial/Kconfig | 23 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/ar933x_uart.c | 688 ++++++++++++++++++ include/linux/serial_core.h | 4 + 5 files changed, 734 insertions(+) create mode 100644 arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h create mode 100644 drivers/tty/serial/ar933x_uart.c diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h new file mode 100644 index 000000000000..6cb30f2b7198 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h @@ -0,0 +1,18 @@ +/* + * Platform data definition for Atheros AR933X UART + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _AR933X_UART_PLATFORM_H +#define _AR933X_UART_PLATFORM_H + +struct ar933x_uart_platform_data { + unsigned uartclk; +}; + +#endif /* _AR933X_UART_PLATFORM_H */ diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 925a1e547a83..95a0f5fe7d42 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1610,4 +1610,27 @@ config SERIAL_XILINX_PS_UART_CONSOLE help Enable a Xilinx PS UART port to be the system console. +config SERIAL_AR933X + bool "AR933X serial port support" + depends on SOC_AR933X + select SERIAL_CORE + help + If you have an Atheros AR933X SOC based board and want to use the + built-in UART of the SoC, say Y to this option. + +config SERIAL_AR933X_CONSOLE + bool "Console on AR933X serial port" + depends on SERIAL_AR933X=y + select SERIAL_CORE_CONSOLE + help + Enable a built-in UART port of the AR933X to be the system console. + +config SERIAL_AR933X_NR_UARTS + int "Maximum number of AR933X serial ports" + depends on SERIAL_AR933X + default "2" + help + Set this to the number of serial ports you want the driver + to support. + endmenu diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index e10cf5b54b6d..76811cc58591 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o +obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c new file mode 100644 index 000000000000..e4f60e2b87f3 --- /dev/null +++ b/drivers/tty/serial/ar933x_uart.c @@ -0,0 +1,688 @@ +/* + * Atheros AR933X SoC built-in UART driver + * + * Copyright (C) 2011 Gabor Juhos + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "ar933x-uart" + +#define AR933X_DUMMY_STATUS_RD 0x01 + +static struct uart_driver ar933x_uart_driver; + +struct ar933x_uart_port { + struct uart_port port; + unsigned int ier; /* shadow Interrupt Enable Register */ +}; + +static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up, + int offset) +{ + return readl(up->port.membase + offset); +} + +static inline void ar933x_uart_write(struct ar933x_uart_port *up, + int offset, unsigned int value) +{ + writel(value, up->port.membase + offset); +} + +static inline void ar933x_uart_rmw(struct ar933x_uart_port *up, + unsigned int offset, + unsigned int mask, + unsigned int val) +{ + unsigned int t; + + t = ar933x_uart_read(up, offset); + t &= ~mask; + t |= val; + ar933x_uart_write(up, offset, t); +} + +static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up, + unsigned int offset, + unsigned int val) +{ + ar933x_uart_rmw(up, offset, 0, val); +} + +static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up, + unsigned int offset, + unsigned int val) +{ + ar933x_uart_rmw(up, offset, val, 0); +} + +static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up) +{ + up->ier |= AR933X_UART_INT_TX_EMPTY; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); +} + +static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up) +{ + up->ier &= ~AR933X_UART_INT_TX_EMPTY; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); +} + +static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch) +{ + unsigned int rdata; + + rdata = ch & AR933X_UART_DATA_TX_RX_MASK; + rdata |= AR933X_UART_DATA_TX_CSR; + ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata); +} + +static unsigned int ar933x_uart_tx_empty(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned long flags; + unsigned int rdata; + + spin_lock_irqsave(&up->port.lock, flags); + rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); + spin_unlock_irqrestore(&up->port.lock, flags); + + return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT; +} + +static unsigned int ar933x_uart_get_mctrl(struct uart_port *port) +{ + return TIOCM_CAR; +} + +static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static void ar933x_uart_start_tx(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + ar933x_uart_start_tx_interrupt(up); +} + +static void ar933x_uart_stop_tx(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + ar933x_uart_stop_tx_interrupt(up); +} + +static void ar933x_uart_stop_rx(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + up->ier &= ~AR933X_UART_INT_RX_VALID; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); +} + +static void ar933x_uart_break_ctl(struct uart_port *port, int break_state) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned long flags; + + spin_lock_irqsave(&up->port.lock, flags); + if (break_state == -1) + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_TX_BREAK); + else + ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, + AR933X_UART_CS_TX_BREAK); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static void ar933x_uart_enable_ms(struct uart_port *port) +{ +} + +static void ar933x_uart_set_termios(struct uart_port *port, + struct ktermios *new, + struct ktermios *old) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned int cs; + unsigned long flags; + unsigned int baud, scale; + + /* Only CS8 is supported */ + new->c_cflag &= ~CSIZE; + new->c_cflag |= CS8; + + /* Only one stop bit is supported */ + new->c_cflag &= ~CSTOPB; + + cs = 0; + if (new->c_cflag & PARENB) { + if (!(new->c_cflag & PARODD)) + cs |= AR933X_UART_CS_PARITY_EVEN; + else + cs |= AR933X_UART_CS_PARITY_ODD; + } else { + cs |= AR933X_UART_CS_PARITY_NONE; + } + + /* Mark/space parity is not supported */ + new->c_cflag &= ~CMSPAR; + + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); + scale = (port->uartclk / (16 * baud)) - 1; + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + /* Update the per-port timeout. */ + uart_update_timeout(port, new->c_cflag, baud); + + up->port.ignore_status_mask = 0; + + /* ignore all characters if CREAD is not set */ + if ((new->c_cflag & CREAD) == 0) + up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD; + + ar933x_uart_write(up, AR933X_UART_CLOCK_REG, + scale << AR933X_UART_CLOCK_SCALE_S | 8192); + + /* setup configuration register */ + ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs); + + /* enable host interrupt */ + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_HOST_INT_EN); + + spin_unlock_irqrestore(&up->port.lock, flags); + + if (tty_termios_baud_rate(new)) + tty_termios_encode_baud_rate(new, baud, baud); +} + +static void ar933x_uart_rx_chars(struct ar933x_uart_port *up) +{ + struct tty_struct *tty; + int max_count = 256; + + tty = tty_port_tty_get(&up->port.state->port); + do { + unsigned int rdata; + unsigned char ch; + + rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); + if ((rdata & AR933X_UART_DATA_RX_CSR) == 0) + break; + + /* remove the character from the FIFO */ + ar933x_uart_write(up, AR933X_UART_DATA_REG, + AR933X_UART_DATA_RX_CSR); + + if (!tty) { + /* discard the data if no tty available */ + continue; + } + + up->port.icount.rx++; + ch = rdata & AR933X_UART_DATA_TX_RX_MASK; + + if (uart_handle_sysrq_char(&up->port, ch)) + continue; + + if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0) + tty_insert_flip_char(tty, ch, TTY_NORMAL); + } while (max_count-- > 0); + + if (tty) { + tty_flip_buffer_push(tty); + tty_kref_put(tty); + } +} + +static void ar933x_uart_tx_chars(struct ar933x_uart_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int count; + + if (uart_tx_stopped(&up->port)) + return; + + count = up->port.fifosize; + do { + unsigned int rdata; + + rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); + if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) + break; + + if (up->port.x_char) { + ar933x_uart_putc(up, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + continue; + } + + if (uart_circ_empty(xmit)) + break; + + ar933x_uart_putc(up, xmit->buf[xmit->tail]); + + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (!uart_circ_empty(xmit)) + ar933x_uart_start_tx_interrupt(up); +} + +static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id) +{ + struct ar933x_uart_port *up = dev_id; + unsigned int status; + + status = ar933x_uart_read(up, AR933X_UART_CS_REG); + if ((status & AR933X_UART_CS_HOST_INT) == 0) + return IRQ_NONE; + + spin_lock(&up->port.lock); + + status = ar933x_uart_read(up, AR933X_UART_INT_REG); + status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG); + + if (status & AR933X_UART_INT_RX_VALID) { + ar933x_uart_write(up, AR933X_UART_INT_REG, + AR933X_UART_INT_RX_VALID); + ar933x_uart_rx_chars(up); + } + + if (status & AR933X_UART_INT_TX_EMPTY) { + ar933x_uart_write(up, AR933X_UART_INT_REG, + AR933X_UART_INT_TX_EMPTY); + ar933x_uart_stop_tx_interrupt(up); + ar933x_uart_tx_chars(up); + } + + spin_unlock(&up->port.lock); + + return IRQ_HANDLED; +} + +static int ar933x_uart_startup(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned long flags; + int ret; + + ret = request_irq(up->port.irq, ar933x_uart_interrupt, + up->port.irqflags, dev_name(up->port.dev), up); + if (ret) + return ret; + + spin_lock_irqsave(&up->port.lock, flags); + + /* Enable HOST interrupts */ + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_HOST_INT_EN); + + /* Enable RX interrupts */ + up->ier = AR933X_UART_INT_RX_VALID; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); + + spin_unlock_irqrestore(&up->port.lock, flags); + + return 0; +} + +static void ar933x_uart_shutdown(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + /* Disable all interrupts */ + up->ier = 0; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); + + /* Disable break condition */ + ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, + AR933X_UART_CS_TX_BREAK); + + free_irq(up->port.irq, up); +} + +static const char *ar933x_uart_type(struct uart_port *port) +{ + return (port->type == PORT_AR933X) ? "AR933X UART" : NULL; +} + +static void ar933x_uart_release_port(struct uart_port *port) +{ + /* Nothing to release ... */ +} + +static int ar933x_uart_request_port(struct uart_port *port) +{ + /* UARTs always present */ + return 0; +} + +static void ar933x_uart_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) + port->type = PORT_AR933X; +} + +static int ar933x_uart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (ser->type != PORT_UNKNOWN && + ser->type != PORT_AR933X) + return -EINVAL; + + if (ser->irq < 0 || ser->irq >= NR_IRQS) + return -EINVAL; + + if (ser->baud_base < 28800) + return -EINVAL; + + return 0; +} + +static struct uart_ops ar933x_uart_ops = { + .tx_empty = ar933x_uart_tx_empty, + .set_mctrl = ar933x_uart_set_mctrl, + .get_mctrl = ar933x_uart_get_mctrl, + .stop_tx = ar933x_uart_stop_tx, + .start_tx = ar933x_uart_start_tx, + .stop_rx = ar933x_uart_stop_rx, + .enable_ms = ar933x_uart_enable_ms, + .break_ctl = ar933x_uart_break_ctl, + .startup = ar933x_uart_startup, + .shutdown = ar933x_uart_shutdown, + .set_termios = ar933x_uart_set_termios, + .type = ar933x_uart_type, + .release_port = ar933x_uart_release_port, + .request_port = ar933x_uart_request_port, + .config_port = ar933x_uart_config_port, + .verify_port = ar933x_uart_verify_port, +}; + +#ifdef CONFIG_SERIAL_AR933X_CONSOLE + +static struct ar933x_uart_port * +ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS]; + +static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up) +{ + unsigned int status; + unsigned int timeout = 60000; + + /* Wait up to 60ms for the character(s) to be sent. */ + do { + status = ar933x_uart_read(up, AR933X_UART_DATA_REG); + if (--timeout == 0) + break; + udelay(1); + } while ((status & AR933X_UART_DATA_TX_CSR) == 0); +} + +static void ar933x_uart_console_putchar(struct uart_port *port, int ch) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + ar933x_uart_wait_xmitr(up); + ar933x_uart_putc(up, ch); +} + +static void ar933x_uart_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct ar933x_uart_port *up = ar933x_console_ports[co->index]; + unsigned long flags; + unsigned int int_en; + int locked = 1; + + local_irq_save(flags); + + if (up->port.sysrq) + locked = 0; + else if (oops_in_progress) + locked = spin_trylock(&up->port.lock); + else + spin_lock(&up->port.lock); + + /* + * First save the IER then disable the interrupts + */ + int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG); + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0); + + uart_console_write(&up->port, s, count, ar933x_uart_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + ar933x_uart_wait_xmitr(up); + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en); + + ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS); + + if (locked) + spin_unlock(&up->port.lock); + + local_irq_restore(flags); +} + +static int ar933x_uart_console_setup(struct console *co, char *options) +{ + struct ar933x_uart_port *up; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS) + return -EINVAL; + + up = ar933x_console_ports[co->index]; + if (!up) + return -ENODEV; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(&up->port, co, baud, parity, bits, flow); +} + +static struct console ar933x_uart_console = { + .name = "ttyATH", + .write = ar933x_uart_console_write, + .device = uart_console_device, + .setup = ar933x_uart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &ar933x_uart_driver, +}; + +static void ar933x_uart_add_console_port(struct ar933x_uart_port *up) +{ + ar933x_console_ports[up->port.line] = up; +} + +#define AR933X_SERIAL_CONSOLE (&ar933x_uart_console) + +#else + +static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {} + +#define AR933X_SERIAL_CONSOLE NULL + +#endif /* CONFIG_SERIAL_AR933X_CONSOLE */ + +static struct uart_driver ar933x_uart_driver = { + .owner = THIS_MODULE, + .driver_name = DRIVER_NAME, + .dev_name = "ttyATH", + .nr = CONFIG_SERIAL_AR933X_NR_UARTS, + .cons = AR933X_SERIAL_CONSOLE, +}; + +static int __devinit ar933x_uart_probe(struct platform_device *pdev) +{ + struct ar933x_uart_platform_data *pdata; + struct ar933x_uart_port *up; + struct uart_port *port; + struct resource *mem_res; + struct resource *irq_res; + int id; + int ret; + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + id = pdev->id; + if (id == -1) + id = 0; + + if (id > CONFIG_SERIAL_AR933X_NR_UARTS) + return -EINVAL; + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem_res) { + dev_err(&pdev->dev, "no MEM resource\n"); + return -EINVAL; + } + + irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!irq_res) { + dev_err(&pdev->dev, "no IRQ resource\n"); + return -EINVAL; + } + + up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL); + if (!up) + return -ENOMEM; + + port = &up->port; + port->mapbase = mem_res->start; + + port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE); + if (!port->membase) { + ret = -ENOMEM; + goto err_free_up; + } + + port->line = id; + port->irq = irq_res->start; + port->dev = &pdev->dev; + port->type = PORT_AR933X; + port->iotype = UPIO_MEM32; + port->uartclk = pdata->uartclk; + + port->regshift = 2; + port->fifosize = AR933X_UART_FIFO_SIZE; + port->ops = &ar933x_uart_ops; + + ar933x_uart_add_console_port(up); + + ret = uart_add_one_port(&ar933x_uart_driver, &up->port); + if (ret) + goto err_unmap; + + platform_set_drvdata(pdev, up); + return 0; + +err_unmap: + iounmap(up->port.membase); +err_free_up: + kfree(up); + return ret; +} + +static int __devexit ar933x_uart_remove(struct platform_device *pdev) +{ + struct ar933x_uart_port *up; + + up = platform_get_drvdata(pdev); + platform_set_drvdata(pdev, NULL); + + if (up) { + uart_remove_one_port(&ar933x_uart_driver, &up->port); + iounmap(up->port.membase); + kfree(up); + } + + return 0; +} + +static struct platform_driver ar933x_uart_platform_driver = { + .probe = ar933x_uart_probe, + .remove = __devexit_p(ar933x_uart_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ar933x_uart_init(void) +{ + int ret; + + ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS; + ret = uart_register_driver(&ar933x_uart_driver); + if (ret) + goto err_out; + + ret = platform_driver_register(&ar933x_uart_platform_driver); + if (ret) + goto err_unregister_uart_driver; + + return 0; + +err_unregister_uart_driver: + uart_unregister_driver(&ar933x_uart_driver); +err_out: + return ret; +} + +static void __exit ar933x_uart_exit(void) +{ + platform_driver_unregister(&ar933x_uart_platform_driver); + uart_unregister_driver(&ar933x_uart_driver); +} + +module_init(ar933x_uart_init); +module_exit(ar933x_uart_exit); + +MODULE_DESCRIPTION("Atheros AR933X UART driver"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index eadf33d0abba..3c35fb2f688f 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -207,6 +207,10 @@ /* Xilinx PSS UART */ #define PORT_XUARTPS 98 +/* Atheros AR933X SoC */ +#define PORT_AR933X 99 + + #ifdef __KERNEL__ #include From 13051c5cc3dd2600afe980049eb566b9b6a4afda Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 19:26:12 +0200 Subject: [PATCH 033/119] MIPS: ath79: register UART device for the AR933X SoCs The AR933X SoCs does not have a 8250 compatible UART, they are using a different UART core. Register a different platform device for the different UART. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2528/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/dev-common.c | 38 ++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c index 3b82e325bebf..f4956f809072 100644 --- a/arch/mips/ath79/dev-common.c +++ b/arch/mips/ath79/dev-common.c @@ -20,6 +20,7 @@ #include #include +#include #include "common.h" #include "dev-common.h" @@ -54,6 +55,30 @@ static struct platform_device ath79_uart_device = { }, }; +static struct resource ar933x_uart_resources[] = { + { + .start = AR933X_UART_BASE, + .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = ATH79_MISC_IRQ_UART, + .end = ATH79_MISC_IRQ_UART, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct ar933x_uart_platform_data ar933x_uart_data; +static struct platform_device ar933x_uart_device = { + .name = "ar933x-uart", + .id = -1, + .resource = ar933x_uart_resources, + .num_resources = ARRAY_SIZE(ar933x_uart_resources), + .dev = { + .platform_data = &ar933x_uart_data, + }, +}; + void __init ath79_register_uart(void) { struct clk *clk; @@ -62,8 +87,17 @@ void __init ath79_register_uart(void) if (IS_ERR(clk)) panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); - ath79_uart_data[0].uartclk = clk_get_rate(clk); - platform_device_register(&ath79_uart_device); + if (soc_is_ar71xx() || + soc_is_ar724x() || + soc_is_ar913x()) { + ath79_uart_data[0].uartclk = clk_get_rate(clk); + platform_device_register(&ath79_uart_device); + } else if (soc_is_ar933x()) { + ar933x_uart_data.uartclk = clk_get_rate(clk); + platform_device_register(&ar933x_uart_device); + } else { + BUG(); + } } static struct platform_device ath79_wdt_device = { From 7e0dde175e5c06c31624e7fb88975eee683d6894 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 19:26:13 +0200 Subject: [PATCH 034/119] MIPS: ath79: Add initial support for the Atheros AP121 reference board Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Patchwork: https://patchwork.linux-mips.org/patch/2531/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/Kconfig | 11 +++++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/mach-ap121.c | 88 ++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 101 insertions(+) create mode 100644 arch/mips/ath79/mach-ap121.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index c3680c83a102..4a7e0e871e90 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -2,6 +2,17 @@ if ATH79 menu "Atheros AR71XX/AR724X/AR913X machine selection" +config ATH79_MACH_AP121 + bool "Atheros AP121 reference board" + select SOC_AR933X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + select ATH79_DEV_USB + help + Say 'Y' here if you want your kernel to support the + Atheros AP121 reference board. + config ATH79_MACH_AP81 bool "Atheros AP81 reference board" select SOC_AR913X diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 57188b61b9ae..8933d18fd0f0 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -25,5 +25,6 @@ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o # # Machines # +obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c new file mode 100644 index 000000000000..353af55fe94d --- /dev/null +++ b/arch/mips/ath79/mach-ap121.c @@ -0,0 +1,88 @@ +/* + * Atheros AP121 board support + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "machtypes.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" +#include "dev-usb.h" + +#define AP121_GPIO_LED_WLAN 0 +#define AP121_GPIO_LED_USB 1 + +#define AP121_GPIO_BTN_JUMPSTART 11 +#define AP121_GPIO_BTN_RESET 12 + +#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) + +#define AP121_CAL_DATA_ADDR 0x1fff1000 + +static struct gpio_led ap121_leds_gpio[] __initdata = { + { + .name = "ap121:green:usb", + .gpio = AP121_GPIO_LED_USB, + .active_low = 0, + }, + { + .name = "ap121:green:wlan", + .gpio = AP121_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ap121_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP121_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, + { + .desc = "reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP121_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct spi_board_info ap121_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "mx25l1606e", + } +}; + +static struct ath79_spi_platform_data ap121_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +static void __init ap121_setup(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), + ap121_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap121_gpio_keys), + ap121_gpio_keys); + + ath79_register_spi(&ap121_spi_data, ap121_spi_info, + ARRAY_SIZE(ap121_spi_info)); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", + ap121_setup); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index 3940fe470b2d..6e28d51c93d5 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -16,6 +16,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ ATH79_MACH_AP81, /* Atheros AP81 reference board */ ATH79_MACH_PB44, /* Atheros PB44 reference board */ }; From 4ff40d5a7668cfadcfc37c3982caea940ba60d8d Mon Sep 17 00:00:00 2001 From: Rene Bolldorf Date: Thu, 17 Nov 2011 14:25:09 +0000 Subject: [PATCH 035/119] MIPS: Initial PCI support for Atheros 724x SoCs. [ralf@linux-mips.org: Fixed the odd formatting of all break statements.] Signed-off-by: Rene Bolldorf Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/3019/ Signed-off-by: Ralf Baechle --- .../mips/include/asm/mach-ath79/pci-ath724x.h | 21 +++ arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-ath724x.c | 174 ++++++++++++++++++ 3 files changed, 196 insertions(+) create mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h create mode 100644 arch/mips/pci/pci-ath724x.c diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/include/asm/mach-ath79/pci-ath724x.h new file mode 100644 index 000000000000..454885fa30c3 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h @@ -0,0 +1,21 @@ +/* + * Atheros 724x PCI support + * + * Copyright (C) 2011 René Bolldorf + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H +#define __ASM_MACH_ATH79_PCI_ATH724X_H + +struct ath724x_pci_data { + int irq; + void *pdata; +}; + +void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); + +#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index bb82cbdbc62a..19cfe044e7dc 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ ops-bcm63xx.o obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o +obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o # # These are still pretty much in the old state, watch, go blind. diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ath724x.c new file mode 100644 index 000000000000..a4dd24a4130b --- /dev/null +++ b/arch/mips/pci/pci-ath724x.c @@ -0,0 +1,174 @@ +/* + * Atheros 724x PCI support + * + * Copyright (C) 2011 René Bolldorf + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) +#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) + +#define ATH724X_PCI_DEV_BASE 0x14000000 +#define ATH724X_PCI_MEM_BASE 0x10000000 +#define ATH724X_PCI_MEM_SIZE 0x08000000 + +static DEFINE_SPINLOCK(ath724x_pci_lock); +static struct ath724x_pci_data *pci_data; +static int pci_data_size; + +static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) +{ + unsigned long flags, addr, tval, mask; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + spin_lock_irqsave(&ath724x_pci_lock, flags); + + switch (size) { + case 1: + addr = where & ~3; + mask = 0xff000000 >> ((where % 4) * 8); + tval = reg_read(ATH724X_PCI_DEV_BASE + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 2: + addr = where & ~3; + mask = 0xffff0000 >> ((where % 4)*8); + tval = reg_read(ATH724X_PCI_DEV_BASE + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 4: + *value = reg_read(ATH724X_PCI_DEV_BASE + where); + break; + default: + spin_unlock_irqrestore(&ath724x_pci_lock, flags); + + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + spin_unlock_irqrestore(&ath724x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t value) +{ + unsigned long flags, tval, addr, mask; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + spin_lock_irqsave(&ath724x_pci_lock, flags); + + switch (size) { + case 1: + addr = (ATH724X_PCI_DEV_BASE + where) & ~3; + mask = 0xff000000 >> ((where % 4)*8); + tval = reg_read(addr); + tval = tval & ~mask; + tval |= (value << ((4 - (where % 4))*8)) & mask; + reg_write(addr, tval); + break; + case 2: + addr = (ATH724X_PCI_DEV_BASE + where) & ~3; + mask = 0xffff0000 >> ((where % 4)*8); + tval = reg_read(addr); + tval = tval & ~mask; + tval |= (value << ((4 - (where % 4))*8)) & mask; + reg_write(addr, tval); + break; + case 4: + reg_write((ATH724X_PCI_DEV_BASE + where), value); + break; + default: + spin_unlock_irqrestore(&ath724x_pci_lock, flags); + + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + spin_unlock_irqrestore(&ath724x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops ath724x_pci_ops = { + .read = ath724x_pci_read, + .write = ath724x_pci_write, +}; + +static struct resource ath724x_io_resource = { + .name = "PCI IO space", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO, +}; + +static struct resource ath724x_mem_resource = { + .name = "PCI memory space", + .start = ATH724X_PCI_MEM_BASE, + .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct pci_controller ath724x_pci_controller = { + .pci_ops = &ath724x_pci_ops, + .io_resource = &ath724x_io_resource, + .mem_resource = &ath724x_mem_resource, +}; + +void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) +{ + pci_data = data; + pci_data_size = size; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) +{ + unsigned int devfn = dev->devfn; + int irq = -1; + + if (devfn > pci_data_size - 1) + return irq; + + irq = pci_data[devfn].irq; + + return irq; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + unsigned int devfn = dev->devfn; + + if (devfn > pci_data_size - 1) + return PCIBIOS_DEVICE_NOT_FOUND; + + dev->dev.platform_data = pci_data[devfn].pdata; + + return PCIBIOS_SUCCESSFUL; +} + +static int __init ath724x_pcibios_init(void) +{ + register_pci_controller(&ath724x_pci_controller); + + return PCIBIOS_SUCCESSFUL; +} + +arch_initcall(ath724x_pcibios_init); From 2dc7b4a1977e3bd3b7c819c63cab1baf7d260d89 Mon Sep 17 00:00:00 2001 From: Rene Bolldorf Date: Fri, 18 Nov 2011 00:17:42 +0000 Subject: [PATCH 036/119] Initial support for the Ubiquiti Networks XM board (rev 1.0). Signed-off-by: Rene Bolldorf Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/3020/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/Kconfig | 11 +++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/mach-ubnt-xm.c | 119 +++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 132 insertions(+) create mode 100644 arch/mips/ath79/mach-ubnt-xm.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 4a7e0e871e90..195813f56610 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -36,6 +36,16 @@ config ATH79_MACH_PB44 Say 'Y' here if you want your kernel to support the Atheros PB44 reference board. +config ATH79_MACH_UBNT_XM + bool "Ubiquiti Networks XM (rev 1.0) board" + select SOC_AR724X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + help + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. + endmenu config SOC_AR71XX @@ -46,6 +56,7 @@ config SOC_AR71XX config SOC_AR724X select USB_ARCH_HAS_EHCI select USB_ARCH_HAS_OHCI + select HW_HAS_PCI def_bool n config SOC_AR913X diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 8933d18fd0f0..3ecc1463b5da 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o +obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c new file mode 100644 index 000000000000..3c311a539347 --- /dev/null +++ b/arch/mips/ath79/mach-ubnt-xm.c @@ -0,0 +1,119 @@ +/* + * Ubiquiti Networks XM (rev 1.0) board support + * + * Copyright (C) 2011 René Bolldorf + * + * Derived from: mach-pb44.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#ifdef CONFIG_PCI +#include +#include +#endif /* CONFIG_PCI */ + +#include "machtypes.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" + +#define UBNT_XM_GPIO_LED_L1 0 +#define UBNT_XM_GPIO_LED_L2 1 +#define UBNT_XM_GPIO_LED_L3 11 +#define UBNT_XM_GPIO_LED_L4 7 + +#define UBNT_XM_GPIO_BTN_RESET 12 + +#define UBNT_XM_KEYS_POLL_INTERVAL 20 +#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) + +#define UBNT_XM_PCI_IRQ 48 +#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) + +static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { + { + .name = "ubnt-xm:red:link1", + .gpio = UBNT_XM_GPIO_LED_L1, + .active_low = 0, + }, { + .name = "ubnt-xm:orange:link2", + .gpio = UBNT_XM_GPIO_LED_L2, + .active_low = 0, + }, { + .name = "ubnt-xm:green:link3", + .gpio = UBNT_XM_GPIO_LED_L3, + .active_low = 0, + }, { + .name = "ubnt-xm:green:link4", + .gpio = UBNT_XM_GPIO_LED_L4, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, + .gpio = UBNT_XM_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct spi_board_info ubnt_xm_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "mx25l6405d", + } +}; + +static struct ath79_spi_platform_data ubnt_xm_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +#ifdef CONFIG_PCI +static struct ath9k_platform_data ubnt_xm_eeprom_data; + +static struct ath724x_pci_data ubnt_xm_pci_data[] = { + { + .irq = UBNT_XM_PCI_IRQ, + .pdata = &ubnt_xm_eeprom_data, + }, +}; +#endif /* CONFIG_PCI */ + +static void __init ubnt_xm_init(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), + ubnt_xm_leds_gpio); + + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); + + ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, + ARRAY_SIZE(ubnt_xm_spi_info)); + +#ifdef CONFIG_PCI + memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, + sizeof(ubnt_xm_eeprom_data.eeprom_data)); + + ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); +#endif /* CONFIG_PCI */ + +} + +MIPS_MACHINE(ATH79_MACH_UBNT_XM, + "UBNT-XM", + "Ubiquiti Networks XM (rev 1.0) board", + ubnt_xm_init); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index 6e28d51c93d5..9a1f3826626e 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -19,6 +19,7 @@ enum ath79_mach_type { ATH79_MACH_AP121, /* Atheros AP121 reference board */ ATH79_MACH_AP81, /* Atheros AP81 reference board */ ATH79_MACH_PB44, /* Atheros PB44 reference board */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ }; #endif /* _ATH79_MACHTYPE_H */ From be5f3623204e15cb8a95a6d381ae6eb074ba46b5 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 18 Nov 2011 00:17:46 +0000 Subject: [PATCH 037/119] MIPS: ath79: Store the SoC revision in a global variable Knowing the exact revision of the SoC is required to make runtime decisions in various code paths. We have determined the SoC revision already, so we only need to store that in a global variable. Signed-off-by: Gabor Juhos Cc: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3027/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/common.c | 1 + arch/mips/ath79/setup.c | 2 ++ arch/mips/include/asm/mach-ath79/ath79.h | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index 38c2ad7bd871..f0fda982b965 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -30,6 +30,7 @@ u32 ath79_ddr_freq; EXPORT_SYMBOL_GPL(ath79_ddr_freq); enum ath79_soc_type ath79_soc; +unsigned int ath79_soc_rev; void __iomem *ath79_pll_base; void __iomem *ath79_reset_base; diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 4187a1122048..61bf3397251a 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -149,6 +149,8 @@ static void __init ath79_detect_sys_type(void) panic("ath79: unknown SoC, id:0x%08x\n", id); } + ath79_soc_rev = rev; + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); pr_info("SoC: %s\n", ath79_sys_type); } diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h index 407c9354f747..6d0c6c9d5622 100644 --- a/arch/mips/include/asm/mach-ath79/ath79.h +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -32,6 +32,7 @@ enum ath79_soc_type { }; extern enum ath79_soc_type ath79_soc; +extern unsigned int ath79_soc_rev; static inline int soc_is_ar71xx(void) { From 67b0f0f1b355df293f92069a0409452c9e24370b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 18 Nov 2011 00:17:53 +0000 Subject: [PATCH 038/119] MIPS: ath79: Remove 'ar913x' from common variable and function names The wireless MAC specific variables and the registration code can be shared between multiple SoCs. Remove the 'ar913x' part from the function and variable names to avoid confusions. Signed-off-by: Gabor Juhos Cc: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3028/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/dev-ar913x-wmac.c | 20 ++++++++++---------- arch/mips/ath79/dev-ar913x-wmac.h | 8 ++++---- arch/mips/ath79/mach-ap81.c | 2 +- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c index 48f425a5ba28..2c9ba40be96e 100644 --- a/arch/mips/ath79/dev-ar913x-wmac.c +++ b/arch/mips/ath79/dev-ar913x-wmac.c @@ -19,9 +19,9 @@ #include #include "dev-ar913x-wmac.h" -static struct ath9k_platform_data ar913x_wmac_data; +static struct ath9k_platform_data ath79_wmac_data; -static struct resource ar913x_wmac_resources[] = { +static struct resource ath79_wmac_resources[] = { { .start = AR913X_WMAC_BASE, .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1, @@ -33,21 +33,21 @@ static struct resource ar913x_wmac_resources[] = { }, }; -static struct platform_device ar913x_wmac_device = { +static struct platform_device ath79_wmac_device = { .name = "ath9k", .id = -1, - .resource = ar913x_wmac_resources, - .num_resources = ARRAY_SIZE(ar913x_wmac_resources), + .resource = ath79_wmac_resources, + .num_resources = ARRAY_SIZE(ath79_wmac_resources), .dev = { - .platform_data = &ar913x_wmac_data, + .platform_data = &ath79_wmac_data, }, }; -void __init ath79_register_ar913x_wmac(u8 *cal_data) +void __init ath79_register_wmac(u8 *cal_data) { if (cal_data) - memcpy(ar913x_wmac_data.eeprom_data, cal_data, - sizeof(ar913x_wmac_data.eeprom_data)); + memcpy(ath79_wmac_data.eeprom_data, cal_data, + sizeof(ath79_wmac_data.eeprom_data)); /* reset the WMAC */ ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); @@ -56,5 +56,5 @@ void __init ath79_register_ar913x_wmac(u8 *cal_data) ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); mdelay(10); - platform_device_register(&ar913x_wmac_device); + platform_device_register(&ath79_wmac_device); } diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-ar913x-wmac.h index 579d562bbda8..de1d78497fc9 100644 --- a/arch/mips/ath79/dev-ar913x-wmac.h +++ b/arch/mips/ath79/dev-ar913x-wmac.h @@ -9,9 +9,9 @@ * by the Free Software Foundation. */ -#ifndef _ATH79_DEV_AR913X_WMAC_H -#define _ATH79_DEV_AR913X_WMAC_H +#ifndef _ATH79_DEV_WMAC_H +#define _ATH79_DEV_WMAC_H -void ath79_register_ar913x_wmac(u8 *cal_data); +void ath79_register_wmac(u8 *cal_data); -#endif /* _ATH79_DEV_AR913X_WMAC_H */ +#endif /* _ATH79_DEV_WMAC_H */ diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c index 6c0826736012..84442da2d23c 100644 --- a/arch/mips/ath79/mach-ap81.c +++ b/arch/mips/ath79/mach-ap81.c @@ -92,7 +92,7 @@ static void __init ap81_setup(void) ap81_gpio_keys); ath79_register_spi(&ap81_spi_data, ap81_spi_info, ARRAY_SIZE(ap81_spi_info)); - ath79_register_ar913x_wmac(cal_data); + ath79_register_wmac(cal_data); ath79_register_usb(); } From 6903bb49da18e0bf3e2909e6b1342ee9a26b78ff Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 18 Nov 2011 00:17:53 +0000 Subject: [PATCH 039/119] MIPS: ath79: Separate AR913x SoC specific WMAC setup code The device registration code can be shared between the different SoCs, but the required setup code varies Move AR913x specific setup code into a separate function in order to make adding support for another SoCs easier. Signed-off-by: Gabor Juhos Cc: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3029/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/dev-ar913x-wmac.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c index 2c9ba40be96e..21118fb461ab 100644 --- a/arch/mips/ath79/dev-ar913x-wmac.c +++ b/arch/mips/ath79/dev-ar913x-wmac.c @@ -23,8 +23,7 @@ static struct ath9k_platform_data ath79_wmac_data; static struct resource ath79_wmac_resources[] = { { - .start = AR913X_WMAC_BASE, - .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1, + /* .start and .end fields are filled dynamically */ .flags = IORESOURCE_MEM, }, { .start = ATH79_CPU_IRQ_IP2, @@ -43,12 +42,8 @@ static struct platform_device ath79_wmac_device = { }, }; -void __init ath79_register_wmac(u8 *cal_data) +static void __init ar913x_wmac_setup(void) { - if (cal_data) - memcpy(ath79_wmac_data.eeprom_data, cal_data, - sizeof(ath79_wmac_data.eeprom_data)); - /* reset the WMAC */ ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); mdelay(10); @@ -56,5 +51,20 @@ void __init ath79_register_wmac(u8 *cal_data) ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); mdelay(10); + ath79_wmac_resources[0].start = AR913X_WMAC_BASE; + ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; +} + +void __init ath79_register_wmac(u8 *cal_data) +{ + if (soc_is_ar913x()) + ar913x_wmac_setup(); + else + BUG(); + + if (cal_data) + memcpy(ath79_wmac_data.eeprom_data, cal_data, + sizeof(ath79_wmac_data.eeprom_data)); + platform_device_register(&ath79_wmac_device); } From 34cfcd26bd34884e9bcbbfae4f87b36e42931c30 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 18 Nov 2011 00:17:53 +0000 Subject: [PATCH 040/119] MIPS: ath79: Add AR933x specific WMAC setup code The wireless MAC of the AR933x SoCs uses different base address, and requires different setup code. Signed-off-by: Gabor Juhos Cc: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3030/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/dev-ar913x-wmac.c | 43 ++++++++++++++++++- arch/mips/ath79/dev-ar913x-wmac.h | 4 +- .../mips/include/asm/mach-ath79/ar71xx_regs.h | 4 +- 3 files changed, 46 insertions(+), 5 deletions(-) diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c index 21118fb461ab..c424e9a2160d 100644 --- a/arch/mips/ath79/dev-ar913x-wmac.c +++ b/arch/mips/ath79/dev-ar913x-wmac.c @@ -1,7 +1,7 @@ /* - * Atheros AR913X SoC built-in WMAC device support + * Atheros AR913X/AR933X SoC built-in WMAC device support * - * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * * This program is free software; you can redistribute it and/or modify it @@ -55,10 +55,49 @@ static void __init ar913x_wmac_setup(void) ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; } + +static int ar933x_wmac_reset(void) +{ + ath79_device_reset_clear(AR933X_RESET_WMAC); + ath79_device_reset_set(AR933X_RESET_WMAC); + + return 0; +} + +static int ar933x_r1_get_wmac_revision(void) +{ + return ath79_soc_rev; +} + +static void __init ar933x_wmac_setup(void) +{ + u32 t; + + ar933x_wmac_reset(); + + ath79_wmac_device.name = "ar933x_wmac"; + + ath79_wmac_resources[0].start = AR933X_WMAC_BASE; + ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + if (t & AR933X_BOOTSTRAP_REF_CLK_40) + ath79_wmac_data.is_clk_25mhz = false; + else + ath79_wmac_data.is_clk_25mhz = true; + + if (ath79_soc_rev == 1) + ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; + + ath79_wmac_data.external_reset = ar933x_wmac_reset; +} + void __init ath79_register_wmac(u8 *cal_data) { if (soc_is_ar913x()) ar913x_wmac_setup(); + if (soc_is_ar933x()) + ar933x_wmac_setup(); else BUG(); diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-ar913x-wmac.h index de1d78497fc9..c9cd8709f090 100644 --- a/arch/mips/ath79/dev-ar913x-wmac.h +++ b/arch/mips/ath79/dev-ar913x-wmac.h @@ -1,7 +1,7 @@ /* - * Atheros AR913X SoC built-in WMAC device support + * Atheros AR913X/AR933X SoC built-in WMAC device support * - * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * * This program is free software; you can redistribute it and/or modify it diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 733bacace778..2f0becb4ec8f 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -55,7 +55,8 @@ #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR933X_UART_SIZE 0x14 - +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 #define AR933X_EHCI_BASE 0x1b000000 #define AR933X_EHCI_SIZE 0x1000 @@ -233,6 +234,7 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_WMAC BIT(11) #define AR933X_RESET_USB_HOST BIT(5) #define AR933X_RESET_USB_PHY BIT(4) #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) From 3ae400223121ffb7d5b6f8299b6d18059a8fd038 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 18 Nov 2011 00:17:54 +0000 Subject: [PATCH 041/119] MIPS: ath79: Rename ATH79_DEV_AR913X_WMAC option to ATH79_DEV_WMAC The ATH79_DEV_AR913X_WMAC option was used to select the AR913x specific wireless MAC registration code. The registration code now supports the AR933X SoCs as well. Rename the option to reflect the changes. Also make the new option depends on SOC_AR933X. Signed-off-by: Gabor Juhos Cc: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3031/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/Kconfig | 11 ++++++----- arch/mips/ath79/Makefile | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 195813f56610..e0fae8f4442b 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -9,6 +9,7 @@ config ATH79_MACH_AP121 select ATH79_DEV_LEDS_GPIO select ATH79_DEV_SPI select ATH79_DEV_USB + select ATH79_DEV_WMAC help Say 'Y' here if you want your kernel to support the Atheros AP121 reference board. @@ -16,11 +17,11 @@ config ATH79_MACH_AP121 config ATH79_MACH_AP81 bool "Atheros AP81 reference board" select SOC_AR913X - select ATH79_DEV_AR913X_WMAC select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO select ATH79_DEV_SPI select ATH79_DEV_USB + select ATH79_DEV_WMAC help Say 'Y' here if you want your kernel to support the Atheros AP81 reference board. @@ -67,10 +68,6 @@ config SOC_AR933X select USB_ARCH_HAS_EHCI def_bool n -config ATH79_DEV_AR913X_WMAC - depends on SOC_AR913X - def_bool n - config ATH79_DEV_GPIO_BUTTONS def_bool n @@ -83,4 +80,8 @@ config ATH79_DEV_SPI config ATH79_DEV_USB def_bool n +config ATH79_DEV_WMAC + depends on (SOC_AR913X || SOC_AR933X) + def_bool n + endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 3ecc1463b5da..53eca55d5b53 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -16,11 +16,11 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o # Devices # obj-y += dev-common.o -obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o +obj-$(CONFIG_ATH79_DEV_WMAC) += dev-ar913x-wmac.o # # Machines From 0b0db270b8695f0a0ca87f273a8214fd9f6773de Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 18 Nov 2011 00:17:54 +0000 Subject: [PATCH 042/119] MIPS: ath79: Register the wireless MAC device on the AP121 board Signed-off-by: Gabor Juhos Cc: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3032/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/mach-ap121.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c index 353af55fe94d..39ee82802e49 100644 --- a/arch/mips/ath79/mach-ap121.c +++ b/arch/mips/ath79/mach-ap121.c @@ -13,6 +13,7 @@ #include "dev-leds-gpio.h" #include "dev-spi.h" #include "dev-usb.h" +#include "dev-ar913x-wmac.h" #define AP121_GPIO_LED_WLAN 0 #define AP121_GPIO_LED_USB 1 @@ -73,6 +74,8 @@ static struct ath79_spi_platform_data ap121_spi_data = { static void __init ap121_setup(void) { + u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), ap121_leds_gpio); ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, @@ -82,6 +85,7 @@ static void __init ap121_setup(void) ath79_register_spi(&ap121_spi_data, ap121_spi_info, ARRAY_SIZE(ap121_spi_info)); ath79_register_usb(); + ath79_register_wmac(cal_data); } MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", From 009b9d52e5bdd4b79ae214db10afb677998b33b1 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 18 Nov 2011 00:17:54 +0000 Subject: [PATCH 043/119] MIPS: ath79: Rename dev-ar913x-wmac.h to dev-wmac.h The 'ar913x' part was removed from the common variable and function names, so remove that from the relevant header file name as well. Signed-off-by: Gabor Juhos Cc: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3033/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/dev-ar913x-wmac.c | 2 +- arch/mips/ath79/{dev-ar913x-wmac.h => dev-wmac.h} | 0 arch/mips/ath79/mach-ap121.c | 2 +- arch/mips/ath79/mach-ap81.c | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/mips/ath79/{dev-ar913x-wmac.h => dev-wmac.h} (100%) diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c index c424e9a2160d..24f546985b69 100644 --- a/arch/mips/ath79/dev-ar913x-wmac.c +++ b/arch/mips/ath79/dev-ar913x-wmac.c @@ -17,7 +17,7 @@ #include #include -#include "dev-ar913x-wmac.h" +#include "dev-wmac.h" static struct ath9k_platform_data ath79_wmac_data; diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-wmac.h similarity index 100% rename from arch/mips/ath79/dev-ar913x-wmac.h rename to arch/mips/ath79/dev-wmac.h diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c index 39ee82802e49..4c20200d7c72 100644 --- a/arch/mips/ath79/mach-ap121.c +++ b/arch/mips/ath79/mach-ap121.c @@ -13,7 +13,7 @@ #include "dev-leds-gpio.h" #include "dev-spi.h" #include "dev-usb.h" -#include "dev-ar913x-wmac.h" +#include "dev-wmac.h" #define AP121_GPIO_LED_WLAN 0 #define AP121_GPIO_LED_USB 1 diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c index 84442da2d23c..abe19836331c 100644 --- a/arch/mips/ath79/mach-ap81.c +++ b/arch/mips/ath79/mach-ap81.c @@ -10,7 +10,7 @@ */ #include "machtypes.h" -#include "dev-ar913x-wmac.h" +#include "dev-wmac.h" #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" From b606d5ae905f5e560021298307ab7b9ef69a60f1 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 18 Nov 2011 00:17:54 +0000 Subject: [PATCH 044/119] MIPS: ath79: Rename dev-ar913x-wmac.c to dev-wmac.c Rename the file as a last step of the 'ar913x' removal changes. Signed-off-by: Gabor Juhos Cc: Imre Kaloz Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3034/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/Makefile | 2 +- arch/mips/ath79/{dev-ar913x-wmac.c => dev-wmac.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/mips/ath79/{dev-ar913x-wmac.c => dev-wmac.c} (100%) diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 53eca55d5b53..3b911e09dbec 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o -obj-$(CONFIG_ATH79_DEV_WMAC) += dev-ar913x-wmac.o +obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o # # Machines diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-wmac.c similarity index 100% rename from arch/mips/ath79/dev-ar913x-wmac.c rename to arch/mips/ath79/dev-wmac.c From 455a503f4cd4971b26e431904d98fdf5beea1075 Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:26 +0100 Subject: [PATCH 045/119] MIPS: BCM63XX: Hook up plat_ioremap to intercept soc registers remapping. Internal SOC registers can be directly accessed, no need to waste a TLB entry. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2890/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-bcm63xx/ioremap.h | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/mips/include/asm/mach-bcm63xx/ioremap.h diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h new file mode 100644 index 000000000000..e3fe04dc50bd --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h @@ -0,0 +1,38 @@ +#ifndef BCM63XX_IOREMAP_H_ +#define BCM63XX_IOREMAP_H_ + +#include + +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +static inline int is_bcm63xx_internal_registers(phys_t offset) +{ + switch (bcm63xx_get_cpu_id()) { + case BCM6338_CPU_ID: + case BCM6345_CPU_ID: + case BCM6348_CPU_ID: + case BCM6358_CPU_ID: + if (offset >= 0xfff00000) + return 1; + break; + } + return 0; +} + +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ + if (is_bcm63xx_internal_registers(offset)) + return (void __iomem *)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_bcm63xx_internal_registers((unsigned long)addr); +} + +#endif /* BCM63XX_IOREMAP_H_ */ From d64ed7ada2f689d2c62af1892ca55e47d3653e36 Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:27 +0100 Subject: [PATCH 046/119] MIPS: BCM63XX: Call board_register_device from device_initcall() Some device registration (eg leds), expect subsystem initcall to be run first, so move board device registration to device_initcall(). Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2891/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index d0056598fbfc..04a349928643 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -124,4 +124,4 @@ int __init bcm63xx_register_devices(void) return board_register_devices(); } -arch_initcall(bcm63xx_register_devices); +device_initcall(bcm63xx_register_devices); From ec68c5206ab32f67583c1297f7883ceb91b043eb Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:29 +0100 Subject: [PATCH 047/119] MIPS: BCM63XX: Cleanup cpu registers. Use preprocessor when possible to avoid duplicated and error-prone code. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2897/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/cpu.c | 180 ++-------- .../include/asm/mach-bcm63xx/bcm63xx_cpu.h | 311 ++++++------------ 2 files changed, 125 insertions(+), 366 deletions(-) diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 7c7e4d4486ce..8bd5133eafd1 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -29,166 +29,38 @@ static u16 bcm63xx_cpu_rev; static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; -/* - * 6338 register sets and irqs - */ -static const unsigned long bcm96338_regs_base[] = { - [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE, - [RSET_PERF] = BCM_6338_PERF_BASE, - [RSET_TIMER] = BCM_6338_TIMER_BASE, - [RSET_WDT] = BCM_6338_WDT_BASE, - [RSET_UART0] = BCM_6338_UART0_BASE, - [RSET_UART1] = BCM_6338_UART1_BASE, - [RSET_GPIO] = BCM_6338_GPIO_BASE, - [RSET_SPI] = BCM_6338_SPI_BASE, - [RSET_OHCI0] = BCM_6338_OHCI0_BASE, - [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE, - [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE, - [RSET_UDC0] = BCM_6338_UDC0_BASE, - [RSET_MPI] = BCM_6338_MPI_BASE, - [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE, - [RSET_SDRAM] = BCM_6338_SDRAM_BASE, - [RSET_DSL] = BCM_6338_DSL_BASE, - [RSET_ENET0] = BCM_6338_ENET0_BASE, - [RSET_ENET1] = BCM_6338_ENET1_BASE, - [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE, - [RSET_MEMC] = BCM_6338_MEMC_BASE, - [RSET_DDR] = BCM_6338_DDR_BASE, +static const unsigned long bcm6338_regs_base[] = { + __GEN_CPU_REGS_TABLE(6338) }; -static const int bcm96338_irqs[] = { - [IRQ_TIMER] = BCM_6338_TIMER_IRQ, - [IRQ_UART0] = BCM_6338_UART0_IRQ, - [IRQ_DSL] = BCM_6338_DSL_IRQ, - [IRQ_ENET0] = BCM_6338_ENET0_IRQ, - [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ, - [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ, - [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ, +static const int bcm6338_irqs[] = { + __GEN_CPU_IRQ_TABLE(6338) }; -/* - * 6345 register sets and irqs - */ -static const unsigned long bcm96345_regs_base[] = { - [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE, - [RSET_PERF] = BCM_6345_PERF_BASE, - [RSET_TIMER] = BCM_6345_TIMER_BASE, - [RSET_WDT] = BCM_6345_WDT_BASE, - [RSET_UART0] = BCM_6345_UART0_BASE, - [RSET_UART1] = BCM_6345_UART1_BASE, - [RSET_GPIO] = BCM_6345_GPIO_BASE, - [RSET_SPI] = BCM_6345_SPI_BASE, - [RSET_UDC0] = BCM_6345_UDC0_BASE, - [RSET_OHCI0] = BCM_6345_OHCI0_BASE, - [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE, - [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE, - [RSET_MPI] = BCM_6345_MPI_BASE, - [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE, - [RSET_DSL] = BCM_6345_DSL_BASE, - [RSET_ENET0] = BCM_6345_ENET0_BASE, - [RSET_ENET1] = BCM_6345_ENET1_BASE, - [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE, - [RSET_EHCI0] = BCM_6345_EHCI0_BASE, - [RSET_SDRAM] = BCM_6345_SDRAM_BASE, - [RSET_MEMC] = BCM_6345_MEMC_BASE, - [RSET_DDR] = BCM_6345_DDR_BASE, +static const unsigned long bcm6345_regs_base[] = { + __GEN_CPU_REGS_TABLE(6345) }; -static const int bcm96345_irqs[] = { - [IRQ_TIMER] = BCM_6345_TIMER_IRQ, - [IRQ_UART0] = BCM_6345_UART0_IRQ, - [IRQ_DSL] = BCM_6345_DSL_IRQ, - [IRQ_ENET0] = BCM_6345_ENET0_IRQ, - [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ, - [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ, - [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ, +static const int bcm6345_irqs[] = { + __GEN_CPU_IRQ_TABLE(6345) }; -/* - * 6348 register sets and irqs - */ -static const unsigned long bcm96348_regs_base[] = { - [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE, - [RSET_PERF] = BCM_6348_PERF_BASE, - [RSET_TIMER] = BCM_6348_TIMER_BASE, - [RSET_WDT] = BCM_6348_WDT_BASE, - [RSET_UART0] = BCM_6348_UART0_BASE, - [RSET_UART1] = BCM_6348_UART1_BASE, - [RSET_GPIO] = BCM_6348_GPIO_BASE, - [RSET_SPI] = BCM_6348_SPI_BASE, - [RSET_OHCI0] = BCM_6348_OHCI0_BASE, - [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE, - [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE, - [RSET_MPI] = BCM_6348_MPI_BASE, - [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE, - [RSET_SDRAM] = BCM_6348_SDRAM_BASE, - [RSET_DSL] = BCM_6348_DSL_BASE, - [RSET_ENET0] = BCM_6348_ENET0_BASE, - [RSET_ENET1] = BCM_6348_ENET1_BASE, - [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE, - [RSET_MEMC] = BCM_6348_MEMC_BASE, - [RSET_DDR] = BCM_6348_DDR_BASE, +static const unsigned long bcm6348_regs_base[] = { + __GEN_CPU_REGS_TABLE(6348) }; -static const int bcm96348_irqs[] = { - [IRQ_TIMER] = BCM_6348_TIMER_IRQ, - [IRQ_UART0] = BCM_6348_UART0_IRQ, - [IRQ_DSL] = BCM_6348_DSL_IRQ, - [IRQ_ENET0] = BCM_6348_ENET0_IRQ, - [IRQ_ENET1] = BCM_6348_ENET1_IRQ, - [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ, - [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ, - [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ, - [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ, - [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ, - [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ, - [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ, - [IRQ_PCI] = BCM_6348_PCI_IRQ, +static const int bcm6348_irqs[] = { + __GEN_CPU_IRQ_TABLE(6348) + }; -/* - * 6358 register sets and irqs - */ -static const unsigned long bcm96358_regs_base[] = { - [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE, - [RSET_PERF] = BCM_6358_PERF_BASE, - [RSET_TIMER] = BCM_6358_TIMER_BASE, - [RSET_WDT] = BCM_6358_WDT_BASE, - [RSET_UART0] = BCM_6358_UART0_BASE, - [RSET_UART1] = BCM_6358_UART1_BASE, - [RSET_GPIO] = BCM_6358_GPIO_BASE, - [RSET_SPI] = BCM_6358_SPI_BASE, - [RSET_OHCI0] = BCM_6358_OHCI0_BASE, - [RSET_EHCI0] = BCM_6358_EHCI0_BASE, - [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE, - [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE, - [RSET_MPI] = BCM_6358_MPI_BASE, - [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE, - [RSET_SDRAM] = BCM_6358_SDRAM_BASE, - [RSET_DSL] = BCM_6358_DSL_BASE, - [RSET_ENET0] = BCM_6358_ENET0_BASE, - [RSET_ENET1] = BCM_6358_ENET1_BASE, - [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE, - [RSET_MEMC] = BCM_6358_MEMC_BASE, - [RSET_DDR] = BCM_6358_DDR_BASE, +static const unsigned long bcm6358_regs_base[] = { + __GEN_CPU_REGS_TABLE(6358) }; -static const int bcm96358_irqs[] = { - [IRQ_TIMER] = BCM_6358_TIMER_IRQ, - [IRQ_UART0] = BCM_6358_UART0_IRQ, - [IRQ_UART1] = BCM_6358_UART1_IRQ, - [IRQ_DSL] = BCM_6358_DSL_IRQ, - [IRQ_ENET0] = BCM_6358_ENET0_IRQ, - [IRQ_ENET1] = BCM_6358_ENET1_IRQ, - [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ, - [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ, - [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ, - [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ, - [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ, - [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ, - [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ, - [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ, - [IRQ_PCI] = BCM_6358_PCI_IRQ, +static const int bcm6358_irqs[] = { + __GEN_CPU_IRQ_TABLE(6358) + }; u16 __bcm63xx_get_cpu_id(void) @@ -301,24 +173,24 @@ void __init bcm63xx_cpu_init(void) case CPU_BMIPS3300: if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) { expected_cpu_id = BCM6348_CPU_ID; - bcm63xx_regs_base = bcm96348_regs_base; - bcm63xx_irqs = bcm96348_irqs; + bcm63xx_regs_base = bcm6348_regs_base; + bcm63xx_irqs = bcm6348_irqs; } else { __cpu_name[cpu] = "Broadcom BCM6338"; expected_cpu_id = BCM6338_CPU_ID; - bcm63xx_regs_base = bcm96338_regs_base; - bcm63xx_irqs = bcm96338_irqs; + bcm63xx_regs_base = bcm6338_regs_base; + bcm63xx_irqs = bcm6338_irqs; } break; case CPU_BMIPS32: expected_cpu_id = BCM6345_CPU_ID; - bcm63xx_regs_base = bcm96345_regs_base; - bcm63xx_irqs = bcm96345_irqs; + bcm63xx_regs_base = bcm6345_regs_base; + bcm63xx_irqs = bcm6345_irqs; break; case CPU_BMIPS4350: expected_cpu_id = BCM6358_CPU_ID; - bcm63xx_regs_base = bcm96358_regs_base; - bcm63xx_irqs = bcm96358_irqs; + bcm63xx_regs_base = bcm6358_regs_base; + bcm63xx_irqs = bcm6358_irqs; break; } diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 96a2391ad85b..464f948e6504 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -234,202 +234,77 @@ enum bcm63xx_regs_set { extern const unsigned long *bcm63xx_regs_base; +#define __GEN_RSET_BASE(__cpu, __rset) \ + case RSET_## __rset : \ + return BCM_## __cpu ##_## __rset ##_BASE; + +#define __GEN_RSET(__cpu) \ + switch (set) { \ + __GEN_RSET_BASE(__cpu, DSL_LMEM) \ + __GEN_RSET_BASE(__cpu, PERF) \ + __GEN_RSET_BASE(__cpu, TIMER) \ + __GEN_RSET_BASE(__cpu, WDT) \ + __GEN_RSET_BASE(__cpu, UART0) \ + __GEN_RSET_BASE(__cpu, UART1) \ + __GEN_RSET_BASE(__cpu, GPIO) \ + __GEN_RSET_BASE(__cpu, SPI) \ + __GEN_RSET_BASE(__cpu, UDC0) \ + __GEN_RSET_BASE(__cpu, OHCI0) \ + __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ + __GEN_RSET_BASE(__cpu, USBH_PRIV) \ + __GEN_RSET_BASE(__cpu, MPI) \ + __GEN_RSET_BASE(__cpu, PCMCIA) \ + __GEN_RSET_BASE(__cpu, DSL) \ + __GEN_RSET_BASE(__cpu, ENET0) \ + __GEN_RSET_BASE(__cpu, ENET1) \ + __GEN_RSET_BASE(__cpu, ENETDMA) \ + __GEN_RSET_BASE(__cpu, EHCI0) \ + __GEN_RSET_BASE(__cpu, SDRAM) \ + __GEN_RSET_BASE(__cpu, MEMC) \ + __GEN_RSET_BASE(__cpu, DDR) \ + } + +#define __GEN_CPU_REGS_TABLE(__cpu) \ + [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \ + [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \ + [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \ + [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \ + [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \ + [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ + [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ + [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ + [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ + [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ + [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ + [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ + [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ + [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ + [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ + [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ + [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ + [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \ + [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \ + [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \ + [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \ + [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \ + + static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) { #ifdef BCMCPU_RUNTIME_DETECT return bcm63xx_regs_base[set]; #else #ifdef CONFIG_BCM63XX_CPU_6338 - switch (set) { - case RSET_DSL_LMEM: - return BCM_6338_DSL_LMEM_BASE; - case RSET_PERF: - return BCM_6338_PERF_BASE; - case RSET_TIMER: - return BCM_6338_TIMER_BASE; - case RSET_WDT: - return BCM_6338_WDT_BASE; - case RSET_UART0: - return BCM_6338_UART0_BASE; - case RSET_UART1: - return BCM_6338_UART1_BASE; - case RSET_GPIO: - return BCM_6338_GPIO_BASE; - case RSET_SPI: - return BCM_6338_SPI_BASE; - case RSET_UDC0: - return BCM_6338_UDC0_BASE; - case RSET_OHCI0: - return BCM_6338_OHCI0_BASE; - case RSET_OHCI_PRIV: - return BCM_6338_OHCI_PRIV_BASE; - case RSET_USBH_PRIV: - return BCM_6338_USBH_PRIV_BASE; - case RSET_MPI: - return BCM_6338_MPI_BASE; - case RSET_PCMCIA: - return BCM_6338_PCMCIA_BASE; - case RSET_DSL: - return BCM_6338_DSL_BASE; - case RSET_ENET0: - return BCM_6338_ENET0_BASE; - case RSET_ENET1: - return BCM_6338_ENET1_BASE; - case RSET_ENETDMA: - return BCM_6338_ENETDMA_BASE; - case RSET_EHCI0: - return BCM_6338_EHCI0_BASE; - case RSET_SDRAM: - return BCM_6338_SDRAM_BASE; - case RSET_MEMC: - return BCM_6338_MEMC_BASE; - case RSET_DDR: - return BCM_6338_DDR_BASE; - } + __GEN_RSET(6338) #endif #ifdef CONFIG_BCM63XX_CPU_6345 - switch (set) { - case RSET_DSL_LMEM: - return BCM_6345_DSL_LMEM_BASE; - case RSET_PERF: - return BCM_6345_PERF_BASE; - case RSET_TIMER: - return BCM_6345_TIMER_BASE; - case RSET_WDT: - return BCM_6345_WDT_BASE; - case RSET_UART0: - return BCM_6345_UART0_BASE; - case RSET_UART1: - return BCM_6345_UART1_BASE; - case RSET_GPIO: - return BCM_6345_GPIO_BASE; - case RSET_SPI: - return BCM_6345_SPI_BASE; - case RSET_UDC0: - return BCM_6345_UDC0_BASE; - case RSET_OHCI0: - return BCM_6345_OHCI0_BASE; - case RSET_OHCI_PRIV: - return BCM_6345_OHCI_PRIV_BASE; - case RSET_USBH_PRIV: - return BCM_6345_USBH_PRIV_BASE; - case RSET_MPI: - return BCM_6345_MPI_BASE; - case RSET_PCMCIA: - return BCM_6345_PCMCIA_BASE; - case RSET_DSL: - return BCM_6345_DSL_BASE; - case RSET_ENET0: - return BCM_6345_ENET0_BASE; - case RSET_ENET1: - return BCM_6345_ENET1_BASE; - case RSET_ENETDMA: - return BCM_6345_ENETDMA_BASE; - case RSET_EHCI0: - return BCM_6345_EHCI0_BASE; - case RSET_SDRAM: - return BCM_6345_SDRAM_BASE; - case RSET_MEMC: - return BCM_6345_MEMC_BASE; - case RSET_DDR: - return BCM_6345_DDR_BASE; - } + __GEN_RSET(6345) #endif #ifdef CONFIG_BCM63XX_CPU_6348 - switch (set) { - case RSET_DSL_LMEM: - return BCM_6348_DSL_LMEM_BASE; - case RSET_PERF: - return BCM_6348_PERF_BASE; - case RSET_TIMER: - return BCM_6348_TIMER_BASE; - case RSET_WDT: - return BCM_6348_WDT_BASE; - case RSET_UART0: - return BCM_6348_UART0_BASE; - case RSET_UART1: - return BCM_6348_UART1_BASE; - case RSET_GPIO: - return BCM_6348_GPIO_BASE; - case RSET_SPI: - return BCM_6348_SPI_BASE; - case RSET_UDC0: - return BCM_6348_UDC0_BASE; - case RSET_OHCI0: - return BCM_6348_OHCI0_BASE; - case RSET_OHCI_PRIV: - return BCM_6348_OHCI_PRIV_BASE; - case RSET_USBH_PRIV: - return BCM_6348_USBH_PRIV_BASE; - case RSET_MPI: - return BCM_6348_MPI_BASE; - case RSET_PCMCIA: - return BCM_6348_PCMCIA_BASE; - case RSET_DSL: - return BCM_6348_DSL_BASE; - case RSET_ENET0: - return BCM_6348_ENET0_BASE; - case RSET_ENET1: - return BCM_6348_ENET1_BASE; - case RSET_ENETDMA: - return BCM_6348_ENETDMA_BASE; - case RSET_EHCI0: - return BCM_6348_EHCI0_BASE; - case RSET_SDRAM: - return BCM_6348_SDRAM_BASE; - case RSET_MEMC: - return BCM_6348_MEMC_BASE; - case RSET_DDR: - return BCM_6348_DDR_BASE; - } + __GEN_RSET(6348) #endif #ifdef CONFIG_BCM63XX_CPU_6358 - switch (set) { - case RSET_DSL_LMEM: - return BCM_6358_DSL_LMEM_BASE; - case RSET_PERF: - return BCM_6358_PERF_BASE; - case RSET_TIMER: - return BCM_6358_TIMER_BASE; - case RSET_WDT: - return BCM_6358_WDT_BASE; - case RSET_UART0: - return BCM_6358_UART0_BASE; - case RSET_UART1: - return BCM_6358_UART1_BASE; - case RSET_GPIO: - return BCM_6358_GPIO_BASE; - case RSET_SPI: - return BCM_6358_SPI_BASE; - case RSET_UDC0: - return BCM_6358_UDC0_BASE; - case RSET_OHCI0: - return BCM_6358_OHCI0_BASE; - case RSET_OHCI_PRIV: - return BCM_6358_OHCI_PRIV_BASE; - case RSET_USBH_PRIV: - return BCM_6358_USBH_PRIV_BASE; - case RSET_MPI: - return BCM_6358_MPI_BASE; - case RSET_PCMCIA: - return BCM_6358_PCMCIA_BASE; - case RSET_ENET0: - return BCM_6358_ENET0_BASE; - case RSET_ENET1: - return BCM_6358_ENET1_BASE; - case RSET_ENETDMA: - return BCM_6358_ENETDMA_BASE; - case RSET_DSL: - return BCM_6358_DSL_BASE; - case RSET_EHCI0: - return BCM_6358_EHCI0_BASE; - case RSET_SDRAM: - return BCM_6358_SDRAM_BASE; - case RSET_MEMC: - return BCM_6358_MEMC_BASE; - case RSET_DDR: - return BCM_6358_DDR_BASE; - } + __GEN_RSET(6358) #endif #endif /* unreached */ @@ -449,7 +324,6 @@ enum bcm63xx_irq { IRQ_ENET_PHY, IRQ_OHCI0, IRQ_EHCI0, - IRQ_PCMCIA0, IRQ_ENET0_RXDMA, IRQ_ENET0_TXDMA, IRQ_ENET1_RXDMA, @@ -462,62 +336,58 @@ enum bcm63xx_irq { * 6338 irqs */ #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) -#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6338_UART1_IRQ 0 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) -#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6) -#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7) #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6338_ENET1_IRQ 0 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) -#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) -#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) -#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12) -#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13) -#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14) +#define BCM_6338_OHCI0_IRQ 0 +#define BCM_6338_EHCI0_IRQ 0 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) -#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) +#define BCM_6338_ENET1_RXDMA_IRQ 0 +#define BCM_6338_ENET1_TXDMA_IRQ 0 +#define BCM_6338_PCI_IRQ 0 +#define BCM_6338_PCMCIA_IRQ 0 /* * 6345 irqs */ #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6345_UART1_IRQ 0 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) -#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) -#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6345_ENET1_IRQ 0 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6345_OHCI0_IRQ 0 +#define BCM_6345_EHCI0_IRQ 0 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) -#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) -#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) -#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) -#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) -#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) -#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) -#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) -#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) -#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) -#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) +#define BCM_6345_ENET1_RXDMA_IRQ 0 +#define BCM_6345_ENET1_TXDMA_IRQ 0 +#define BCM_6345_PCI_IRQ 0 +#define BCM_6345_PCMCIA_IRQ 0 /* * 6348 irqs */ #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6348_UART1_IRQ 0 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) -#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6348_EHCI0_IRQ 0 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) -#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) +#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) /* * 6358 irqs @@ -525,21 +395,38 @@ enum bcm63xx_irq { #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) -#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) -#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) -#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) extern const int *bcm63xx_irqs; +#define __GEN_CPU_IRQ_TABLE(__cpu) \ + [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ + [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ + [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ + [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ + [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ + [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ + [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ + [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ + [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ + [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ + [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ + [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ + [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \ + [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \ + [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \ + static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) { return bcm63xx_irqs[irq]; From d430b6c5e7b3a16ad3b4cd921b3a22b553f53ca2 Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:30 +0100 Subject: [PATCH 048/119] MIPS: BCM63XX: Add more register sets & missing register definitions. Needed for upcoming 6368 CPU support. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2893/ Signed-off-by: Ralf Baechle --- .../include/asm/mach-bcm63xx/bcm63xx_cpu.h | 185 +++++++++++++++++- .../include/asm/mach-bcm63xx/bcm63xx_regs.h | 78 ++++++++ 2 files changed, 261 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 464f948e6504..46f03322e2ca 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -88,6 +88,7 @@ enum bcm63xx_regs_set { RSET_UART1, RSET_GPIO, RSET_SPI, + RSET_SPI2, RSET_UDC0, RSET_OHCI0, RSET_OHCI_PRIV, @@ -98,10 +99,23 @@ enum bcm63xx_regs_set { RSET_ENET0, RSET_ENET1, RSET_ENETDMA, + RSET_ENETDMAC, + RSET_ENETDMAS, + RSET_ENETSW, RSET_EHCI0, RSET_SDRAM, RSET_MEMC, RSET_DDR, + RSET_M2M, + RSET_ATM, + RSET_XTM, + RSET_XTMDMA, + RSET_XTMDMAC, + RSET_XTMDMAS, + RSET_PCM, + RSET_PCMDMA, + RSET_PCMDMAC, + RSET_PCMDMAS, }; #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) @@ -109,11 +123,18 @@ enum bcm63xx_regs_set { #define RSET_WDT_SIZE 12 #define RSET_ENET_SIZE 2048 #define RSET_ENETDMA_SIZE 2048 +#define RSET_ENETSW_SIZE 65536 #define RSET_UART_SIZE 24 #define RSET_UDC_SIZE 256 #define RSET_OHCI_SIZE 256 #define RSET_EHCI_SIZE 256 #define RSET_PCMCIA_SIZE 12 +#define RSET_M2M_SIZE 256 +#define RSET_ATM_SIZE 4096 +#define RSET_XTM_SIZE 10240 +#define RSET_XTMDMA_SIZE 256 +#define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) +#define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) /* * 6338 register sets base address @@ -127,6 +148,7 @@ enum bcm63xx_regs_set { #define BCM_6338_UART1_BASE (0xdeadbeef) #define BCM_6338_GPIO_BASE (0xfffe0400) #define BCM_6338_SPI_BASE (0xfffe0c00) +#define BCM_6338_SPI2_BASE (0xdeadbeef) #define BCM_6338_UDC0_BASE (0xdeadbeef) #define BCM_6338_USBDMA_BASE (0xfffe2400) #define BCM_6338_OHCI0_BASE (0xdeadbeef) @@ -136,15 +158,27 @@ enum bcm63xx_regs_set { #define BCM_6338_PCMCIA_BASE (0xdeadbeef) #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) #define BCM_6338_DSL_BASE (0xfffe1000) -#define BCM_6338_SAR_BASE (0xfffe2000) #define BCM_6338_UBUS_BASE (0xdeadbeef) #define BCM_6338_ENET0_BASE (0xfffe2800) #define BCM_6338_ENET1_BASE (0xdeadbeef) #define BCM_6338_ENETDMA_BASE (0xfffe2400) +#define BCM_6338_ENETDMAC_BASE (0xfffe2500) +#define BCM_6338_ENETDMAS_BASE (0xfffe2600) +#define BCM_6338_ENETSW_BASE (0xdeadbeef) #define BCM_6338_EHCI0_BASE (0xdeadbeef) #define BCM_6338_SDRAM_BASE (0xfffe3100) #define BCM_6338_MEMC_BASE (0xdeadbeef) #define BCM_6338_DDR_BASE (0xdeadbeef) +#define BCM_6338_M2M_BASE (0xdeadbeef) +#define BCM_6338_ATM_BASE (0xfffe2000) +#define BCM_6338_XTM_BASE (0xdeadbeef) +#define BCM_6338_XTMDMA_BASE (0xdeadbeef) +#define BCM_6338_XTMDMAC_BASE (0xdeadbeef) +#define BCM_6338_XTMDMAS_BASE (0xdeadbeef) +#define BCM_6338_PCM_BASE (0xdeadbeef) +#define BCM_6338_PCMDMA_BASE (0xdeadbeef) +#define BCM_6338_PCMDMAC_BASE (0xdeadbeef) +#define BCM_6338_PCMDMAS_BASE (0xdeadbeef) /* * 6345 register sets base address @@ -158,10 +192,14 @@ enum bcm63xx_regs_set { #define BCM_6345_UART1_BASE (0xdeadbeef) #define BCM_6345_GPIO_BASE (0xfffe0400) #define BCM_6345_SPI_BASE (0xdeadbeef) +#define BCM_6345_SPI2_BASE (0xdeadbeef) #define BCM_6345_UDC0_BASE (0xdeadbeef) #define BCM_6345_USBDMA_BASE (0xfffe2800) #define BCM_6345_ENET0_BASE (0xfffe1800) #define BCM_6345_ENETDMA_BASE (0xfffe2800) +#define BCM_6345_ENETDMAC_BASE (0xfffe2900) +#define BCM_6345_ENETDMAS_BASE (0xfffe2a00) +#define BCM_6345_ENETSW_BASE (0xdeadbeef) #define BCM_6345_PCMCIA_BASE (0xfffe2028) #define BCM_6345_MPI_BASE (0xdeadbeef) #define BCM_6345_OHCI0_BASE (0xfffe2100) @@ -169,13 +207,22 @@ enum bcm63xx_regs_set { #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6345_DSL_BASE (0xdeadbeef) -#define BCM_6345_SAR_BASE (0xdeadbeef) #define BCM_6345_UBUS_BASE (0xdeadbeef) #define BCM_6345_ENET1_BASE (0xdeadbeef) #define BCM_6345_EHCI0_BASE (0xdeadbeef) #define BCM_6345_SDRAM_BASE (0xfffe2300) #define BCM_6345_MEMC_BASE (0xdeadbeef) #define BCM_6345_DDR_BASE (0xdeadbeef) +#define BCM_6345_M2M_BASE (0xdeadbeef) +#define BCM_6345_ATM_BASE (0xfffe4000) +#define BCM_6345_XTM_BASE (0xdeadbeef) +#define BCM_6345_XTMDMA_BASE (0xdeadbeef) +#define BCM_6345_XTMDMAC_BASE (0xdeadbeef) +#define BCM_6345_XTMDMAS_BASE (0xdeadbeef) +#define BCM_6345_PCM_BASE (0xdeadbeef) +#define BCM_6345_PCMDMA_BASE (0xdeadbeef) +#define BCM_6345_PCMDMAC_BASE (0xdeadbeef) +#define BCM_6345_PCMDMAS_BASE (0xdeadbeef) /* * 6348 register sets base address @@ -188,6 +235,7 @@ enum bcm63xx_regs_set { #define BCM_6348_UART1_BASE (0xdeadbeef) #define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_SPI_BASE (0xfffe0c00) +#define BCM_6348_SPI2_BASE (0xdeadbeef) #define BCM_6348_UDC0_BASE (0xfffe1000) #define BCM_6348_OHCI0_BASE (0xfffe1b00) #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) @@ -195,14 +243,27 @@ enum bcm63xx_regs_set { #define BCM_6348_MPI_BASE (0xfffe2000) #define BCM_6348_PCMCIA_BASE (0xfffe2054) #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) +#define BCM_6348_M2M_BASE (0xfffe2800) #define BCM_6348_DSL_BASE (0xfffe3000) #define BCM_6348_ENET0_BASE (0xfffe6000) #define BCM_6348_ENET1_BASE (0xfffe6800) #define BCM_6348_ENETDMA_BASE (0xfffe7000) +#define BCM_6348_ENETDMAC_BASE (0xfffe7100) +#define BCM_6348_ENETDMAS_BASE (0xfffe7200) +#define BCM_6348_ENETSW_BASE (0xdeadbeef) #define BCM_6348_EHCI0_BASE (0xdeadbeef) #define BCM_6348_SDRAM_BASE (0xfffe2300) #define BCM_6348_MEMC_BASE (0xdeadbeef) #define BCM_6348_DDR_BASE (0xdeadbeef) +#define BCM_6348_ATM_BASE (0xfffe4000) +#define BCM_6348_XTM_BASE (0xdeadbeef) +#define BCM_6348_XTMDMA_BASE (0xdeadbeef) +#define BCM_6348_XTMDMAC_BASE (0xdeadbeef) +#define BCM_6348_XTMDMAS_BASE (0xdeadbeef) +#define BCM_6348_PCM_BASE (0xdeadbeef) +#define BCM_6348_PCMDMA_BASE (0xdeadbeef) +#define BCM_6348_PCMDMAC_BASE (0xdeadbeef) +#define BCM_6348_PCMDMAS_BASE (0xdeadbeef) /* * 6358 register sets base address @@ -215,6 +276,7 @@ enum bcm63xx_regs_set { #define BCM_6358_UART1_BASE (0xfffe0120) #define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_SPI_BASE (0xdeadbeef) +#define BCM_6358_SPI2_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800) #define BCM_6358_OHCI0_BASE (0xfffe1400) #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) @@ -222,14 +284,28 @@ enum bcm63xx_regs_set { #define BCM_6358_MPI_BASE (0xfffe1000) #define BCM_6358_PCMCIA_BASE (0xfffe1054) #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) +#define BCM_6358_M2M_BASE (0xdeadbeef) #define BCM_6358_DSL_BASE (0xfffe3000) #define BCM_6358_ENET0_BASE (0xfffe4000) #define BCM_6358_ENET1_BASE (0xfffe4800) #define BCM_6358_ENETDMA_BASE (0xfffe5000) +#define BCM_6358_ENETDMAC_BASE (0xfffe5100) +#define BCM_6358_ENETDMAS_BASE (0xfffe5200) +#define BCM_6358_ENETSW_BASE (0xdeadbeef) #define BCM_6358_EHCI0_BASE (0xfffe1300) #define BCM_6358_SDRAM_BASE (0xdeadbeef) #define BCM_6358_MEMC_BASE (0xfffe1200) #define BCM_6358_DDR_BASE (0xfffe12a0) +#define BCM_6358_ATM_BASE (0xfffe2000) +#define BCM_6358_XTM_BASE (0xdeadbeef) +#define BCM_6358_XTMDMA_BASE (0xdeadbeef) +#define BCM_6358_XTMDMAC_BASE (0xdeadbeef) +#define BCM_6358_XTMDMAS_BASE (0xdeadbeef) +#define BCM_6358_PCM_BASE (0xfffe1600) +#define BCM_6358_PCMDMA_BASE (0xfffe1800) +#define BCM_6358_PCMDMAC_BASE (0xfffe1900) +#define BCM_6358_PCMDMAS_BASE (0xfffe1a00) + extern const unsigned long *bcm63xx_regs_base; @@ -248,6 +324,7 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, UART1) \ __GEN_RSET_BASE(__cpu, GPIO) \ __GEN_RSET_BASE(__cpu, SPI) \ + __GEN_RSET_BASE(__cpu, SPI2) \ __GEN_RSET_BASE(__cpu, UDC0) \ __GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ @@ -258,10 +335,23 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, ENET0) \ __GEN_RSET_BASE(__cpu, ENET1) \ __GEN_RSET_BASE(__cpu, ENETDMA) \ + __GEN_RSET_BASE(__cpu, ENETDMAC) \ + __GEN_RSET_BASE(__cpu, ENETDMAS) \ + __GEN_RSET_BASE(__cpu, ENETSW) \ __GEN_RSET_BASE(__cpu, EHCI0) \ __GEN_RSET_BASE(__cpu, SDRAM) \ __GEN_RSET_BASE(__cpu, MEMC) \ __GEN_RSET_BASE(__cpu, DDR) \ + __GEN_RSET_BASE(__cpu, M2M) \ + __GEN_RSET_BASE(__cpu, ATM) \ + __GEN_RSET_BASE(__cpu, XTM) \ + __GEN_RSET_BASE(__cpu, XTMDMA) \ + __GEN_RSET_BASE(__cpu, XTMDMAC) \ + __GEN_RSET_BASE(__cpu, XTMDMAS) \ + __GEN_RSET_BASE(__cpu, PCM) \ + __GEN_RSET_BASE(__cpu, PCMDMA) \ + __GEN_RSET_BASE(__cpu, PCMDMAC) \ + __GEN_RSET_BASE(__cpu, PCMDMAS) \ } #define __GEN_CPU_REGS_TABLE(__cpu) \ @@ -273,6 +363,7 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ + [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \ [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ @@ -283,10 +374,23 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \ + [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \ + [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \ + [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \ [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \ [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \ [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \ [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \ + [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \ + [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \ + [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \ + [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \ + [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \ + [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \ + [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \ + [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ + [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ + [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) @@ -330,6 +434,17 @@ enum bcm63xx_irq { IRQ_ENET1_TXDMA, IRQ_PCI, IRQ_PCMCIA, + IRQ_ATM, + IRQ_ENETSW_RXDMA0, + IRQ_ENETSW_RXDMA1, + IRQ_ENETSW_RXDMA2, + IRQ_ENETSW_RXDMA3, + IRQ_ENETSW_TXDMA0, + IRQ_ENETSW_TXDMA1, + IRQ_ENETSW_TXDMA2, + IRQ_ENETSW_TXDMA3, + IRQ_XTM, + IRQ_XTM_DMA0, }; /* @@ -350,6 +465,17 @@ enum bcm63xx_irq { #define BCM_6338_ENET1_TXDMA_IRQ 0 #define BCM_6338_PCI_IRQ 0 #define BCM_6338_PCMCIA_IRQ 0 +#define BCM_6338_ATM_IRQ 0 +#define BCM_6338_ENETSW_RXDMA0_IRQ 0 +#define BCM_6338_ENETSW_RXDMA1_IRQ 0 +#define BCM_6338_ENETSW_RXDMA2_IRQ 0 +#define BCM_6338_ENETSW_RXDMA3_IRQ 0 +#define BCM_6338_ENETSW_TXDMA0_IRQ 0 +#define BCM_6338_ENETSW_TXDMA1_IRQ 0 +#define BCM_6338_ENETSW_TXDMA2_IRQ 0 +#define BCM_6338_ENETSW_TXDMA3_IRQ 0 +#define BCM_6338_XTM_IRQ 0 +#define BCM_6338_XTM_DMA0_IRQ 0 /* * 6345 irqs @@ -369,6 +495,17 @@ enum bcm63xx_irq { #define BCM_6345_ENET1_TXDMA_IRQ 0 #define BCM_6345_PCI_IRQ 0 #define BCM_6345_PCMCIA_IRQ 0 +#define BCM_6345_ATM_IRQ 0 +#define BCM_6345_ENETSW_RXDMA0_IRQ 0 +#define BCM_6345_ENETSW_RXDMA1_IRQ 0 +#define BCM_6345_ENETSW_RXDMA2_IRQ 0 +#define BCM_6345_ENETSW_RXDMA3_IRQ 0 +#define BCM_6345_ENETSW_TXDMA0_IRQ 0 +#define BCM_6345_ENETSW_TXDMA1_IRQ 0 +#define BCM_6345_ENETSW_TXDMA2_IRQ 0 +#define BCM_6345_ENETSW_TXDMA3_IRQ 0 +#define BCM_6345_XTM_IRQ 0 +#define BCM_6345_XTM_DMA0_IRQ 0 /* * 6348 irqs @@ -388,6 +525,17 @@ enum bcm63xx_irq { #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) +#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6348_ENETSW_RXDMA0_IRQ 0 +#define BCM_6348_ENETSW_RXDMA1_IRQ 0 +#define BCM_6348_ENETSW_RXDMA2_IRQ 0 +#define BCM_6348_ENETSW_RXDMA3_IRQ 0 +#define BCM_6348_ENETSW_TXDMA0_IRQ 0 +#define BCM_6348_ENETSW_TXDMA1_IRQ 0 +#define BCM_6348_ENETSW_TXDMA2_IRQ 0 +#define BCM_6348_ENETSW_TXDMA3_IRQ 0 +#define BCM_6348_XTM_IRQ 0 +#define BCM_6348_XTM_DMA0_IRQ 0 /* * 6358 irqs @@ -407,6 +555,24 @@ enum bcm63xx_irq { #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) +#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19) +#define BCM_6358_ENETSW_RXDMA0_IRQ 0 +#define BCM_6358_ENETSW_RXDMA1_IRQ 0 +#define BCM_6358_ENETSW_RXDMA2_IRQ 0 +#define BCM_6358_ENETSW_RXDMA3_IRQ 0 +#define BCM_6358_ENETSW_TXDMA0_IRQ 0 +#define BCM_6358_ENETSW_TXDMA1_IRQ 0 +#define BCM_6358_ENETSW_TXDMA2_IRQ 0 +#define BCM_6358_ENETSW_TXDMA3_IRQ 0 +#define BCM_6358_XTM_IRQ 0 +#define BCM_6358_XTM_DMA0_IRQ 0 + +#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23) +#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24) +#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) +#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) +#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) +#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) extern const int *bcm63xx_irqs; @@ -426,6 +592,17 @@ extern const int *bcm63xx_irqs; [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \ [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \ [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \ + [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \ + [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \ + [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \ + [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \ + [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \ + [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \ + [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \ + [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \ + [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \ + [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \ + [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) { @@ -437,4 +614,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) */ unsigned int bcm63xx_get_memory_size(void); +void bcm63xx_machine_halt(void); + +void bcm63xx_machine_reboot(void); + #endif /* !BCM63XX_CPU_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 0ed5230243c9..3ea2681c162d 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -547,6 +547,56 @@ #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) +/************************************************************************* + * _REG relative to RSET_ENETDMAC + *************************************************************************/ + +/* Channel Configuration register */ +#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) +#define ENETDMAC_CHANCFG_EN_SHIFT 0 +#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) +#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 +#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) + +/* Interrupt Control/Status register */ +#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) +#define ENETDMAC_IR_BUFDONE_MASK (1 << 0) +#define ENETDMAC_IR_PKTDONE_MASK (1 << 1) +#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) + +/* Interrupt Mask register */ +#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10) + +/* Maximum Burst Length */ +#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10) + + +/************************************************************************* + * _REG relative to RSET_ENETDMAS + *************************************************************************/ + +/* Ring Start Address register */ +#define ENETDMAS_RSTART_REG(x) ((x) * 0x10) + +/* State Ram Word 2 */ +#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10) + +/* State Ram Word 3 */ +#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10) + +/* State Ram Word 4 */ +#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10) + + +/************************************************************************* + * _REG relative to RSET_ENETSW + *************************************************************************/ + +/* MIB register */ +#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) +#define ENETSW_MIB_REG_COUNT 47 + + /************************************************************************* * _REG relative to RSET_OHCI_PRIV *************************************************************************/ @@ -768,4 +818,32 @@ #define DMIPSPLLCFG_N2_SHIFT 29 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) +/************************************************************************* + * _REG relative to RSET_M2M + *************************************************************************/ + +#define M2M_RX 0 +#define M2M_TX 1 + +#define M2M_SRC_REG(x) ((x) * 0x40 + 0x00) +#define M2M_DST_REG(x) ((x) * 0x40 + 0x04) +#define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08) + +#define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c) +#define M2M_CTRL_ENABLE_MASK (1 << 0) +#define M2M_CTRL_IRQEN_MASK (1 << 1) +#define M2M_CTRL_ERROR_CLR_MASK (1 << 6) +#define M2M_CTRL_DONE_CLR_MASK (1 << 7) +#define M2M_CTRL_NOINC_MASK (1 << 8) +#define M2M_CTRL_PCMCIASWAP_MASK (1 << 9) +#define M2M_CTRL_SWAPBYTE_MASK (1 << 10) +#define M2M_CTRL_ENDIAN_MASK (1 << 11) + +#define M2M_STAT_REG(x) ((x) * 0x40 + 0x10) +#define M2M_STAT_DONE (1 << 0) +#define M2M_STAT_ERROR (1 << 1) + +#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) +#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) + #endif /* BCM63XX_REGS_H_ */ From f61cced99347783c1f3a7464e88b855a5ca6c227 Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:31 +0100 Subject: [PATCH 049/119] MIPS: BCM63XX: Change irq code to prepare for per-cpu peculiarity. No functionnal change is introduced by this patch. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2894/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 86 +++++++++++++++++-- .../include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 ++- 2 files changed, 85 insertions(+), 11 deletions(-) diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 162e11b4ed75..a81cd828c769 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -19,19 +19,86 @@ #include #include +static void __dispatch_internal(void) __maybe_unused; + +#ifndef BCMCPU_RUNTIME_DETECT +#ifdef CONFIG_BCM63XX_CPU_6338 +#define irq_stat_reg PERF_IRQSTAT_6338_REG +#define irq_mask_reg PERF_IRQMASK_6338_REG +#endif +#ifdef CONFIG_BCM63XX_CPU_6345 +#define irq_stat_reg PERF_IRQSTAT_6345_REG +#define irq_mask_reg PERF_IRQMASK_6345_REG +#endif +#ifdef CONFIG_BCM63XX_CPU_6348 +#define irq_stat_reg PERF_IRQSTAT_6348_REG +#define irq_mask_reg PERF_IRQMASK_6348_REG +#endif +#ifdef CONFIG_BCM63XX_CPU_6358 +#define irq_stat_reg PERF_IRQSTAT_6358_REG +#define irq_mask_reg PERF_IRQMASK_6358_REG +#endif + +#define dispatch_internal __dispatch_internal + +#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg) +#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg) + +static inline void bcm63xx_init_irq(void) +{ +} +#else /* ! BCMCPU_RUNTIME_DETECT */ + +static u32 irq_stat_addr, irq_mask_addr; +static void (*dispatch_internal)(void); + +static void bcm63xx_init_irq(void) +{ + irq_stat_addr = bcm63xx_regset_address(RSET_PERF); + irq_mask_addr = bcm63xx_regset_address(RSET_PERF); + + switch (bcm63xx_get_cpu_id()) { + case BCM6338_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6338_REG; + irq_mask_addr += PERF_IRQMASK_6338_REG; + break; + case BCM6345_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6345_REG; + irq_mask_addr += PERF_IRQMASK_6345_REG; + break; + case BCM6348_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6348_REG; + irq_mask_addr += PERF_IRQMASK_6348_REG; + break; + case BCM6358_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6358_REG; + irq_mask_addr += PERF_IRQMASK_6358_REG; + break; + default: + BUG(); + } + + dispatch_internal = __dispatch_internal; +} +#endif /* ! BCMCPU_RUNTIME_DETECT */ + +static inline void handle_internal(int intbit) +{ + do_IRQ(intbit + IRQ_INTERNAL_BASE); +} + /* * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not * prioritize any interrupt relatively to another. the static counter * will resume the loop where it ended the last time we left this * function. */ -static void bcm63xx_irq_dispatch_internal(void) +static void __dispatch_internal(void) { u32 pending; static int i; - pending = bcm_perf_readl(PERF_IRQMASK_REG) & - bcm_perf_readl(PERF_IRQSTAT_REG); + pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr); if (!pending) return ; @@ -41,7 +108,7 @@ static void bcm63xx_irq_dispatch_internal(void) i = (i + 1) & 0x1f; if (pending & (1 << to_call)) { - do_IRQ(to_call + IRQ_INTERNAL_BASE); + handle_internal(to_call); break; } } @@ -60,7 +127,7 @@ asmlinkage void plat_irq_dispatch(void) if (cause & CAUSEF_IP7) do_IRQ(7); if (cause & CAUSEF_IP2) - bcm63xx_irq_dispatch_internal(); + dispatch_internal(); if (cause & CAUSEF_IP3) do_IRQ(IRQ_EXT_0); if (cause & CAUSEF_IP4) @@ -81,9 +148,9 @@ static inline void bcm63xx_internal_irq_mask(struct irq_data *d) unsigned int irq = d->irq - IRQ_INTERNAL_BASE; u32 mask; - mask = bcm_perf_readl(PERF_IRQMASK_REG); + mask = bcm_readl(irq_mask_addr); mask &= ~(1 << irq); - bcm_perf_writel(mask, PERF_IRQMASK_REG); + bcm_writel(mask, irq_mask_addr); } static void bcm63xx_internal_irq_unmask(struct irq_data *d) @@ -91,9 +158,9 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d) unsigned int irq = d->irq - IRQ_INTERNAL_BASE; u32 mask; - mask = bcm_perf_readl(PERF_IRQMASK_REG); + mask = bcm_readl(irq_mask_addr); mask |= (1 << irq); - bcm_perf_writel(mask, PERF_IRQMASK_REG); + bcm_writel(mask, irq_mask_addr); } /* @@ -229,6 +296,7 @@ void __init arch_init_irq(void) { int i; + bcm63xx_init_irq(); mips_cpu_irq_init(); for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 3ea2681c162d..25676cdeb30f 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -88,10 +88,16 @@ #define SYS_PLL_SOFT_RESET 0x1 /* Interrupt Mask register */ -#define PERF_IRQMASK_REG 0xc +#define PERF_IRQMASK_6338_REG 0xc +#define PERF_IRQMASK_6345_REG 0xc +#define PERF_IRQMASK_6348_REG 0xc +#define PERF_IRQMASK_6358_REG 0xc /* Interrupt Status register */ -#define PERF_IRQSTAT_REG 0x10 +#define PERF_IRQSTAT_6338_REG 0x10 +#define PERF_IRQSTAT_6345_REG 0x10 +#define PERF_IRQSTAT_6348_REG 0x10 +#define PERF_IRQSTAT_6358_REG 0x10 /* External Interrupt Configuration register */ #define PERF_EXTIRQ_CFG_REG 0x14 From 37c42a741f6c2c76dc5e61650e5d66dd20540aaf Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:32 +0100 Subject: [PATCH 050/119] MIPS: BCM63XX: Prepare irq code to handle different external irq hardware implementation. External irq only works for 6348, change code to prepare support of other CPUs. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2895/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 104 +++++++++++------- .../include/asm/mach-bcm63xx/bcm63xx_irq.h | 12 +- arch/mips/include/asm/mach-bcm63xx/irq.h | 7 ++ 3 files changed, 79 insertions(+), 44 deletions(-) create mode 100644 arch/mips/include/asm/mach-bcm63xx/irq.h diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index a81cd828c769..cdf352b040a9 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -25,18 +25,32 @@ static void __dispatch_internal(void) __maybe_unused; #ifdef CONFIG_BCM63XX_CPU_6338 #define irq_stat_reg PERF_IRQSTAT_6338_REG #define irq_mask_reg PERF_IRQMASK_6338_REG +#define is_ext_irq_cascaded 0 +#define ext_irq_start 0 +#define ext_irq_end 0 #endif #ifdef CONFIG_BCM63XX_CPU_6345 #define irq_stat_reg PERF_IRQSTAT_6345_REG #define irq_mask_reg PERF_IRQMASK_6345_REG +#define is_ext_irq_cascaded 0 +#define ext_irq_start 0 +#define ext_irq_end 0 #endif #ifdef CONFIG_BCM63XX_CPU_6348 #define irq_stat_reg PERF_IRQSTAT_6348_REG #define irq_mask_reg PERF_IRQMASK_6348_REG +#define dispatch_internal __dispatch_internal +#define is_ext_irq_cascaded 0 +#define ext_irq_start 0 +#define ext_irq_end 0 #endif #ifdef CONFIG_BCM63XX_CPU_6358 #define irq_stat_reg PERF_IRQSTAT_6358_REG #define irq_mask_reg PERF_IRQMASK_6358_REG +#define dispatch_internal __dispatch_internal +#define is_ext_irq_cascaded 1 +#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE) +#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE) #endif #define dispatch_internal __dispatch_internal @@ -51,6 +65,8 @@ static inline void bcm63xx_init_irq(void) static u32 irq_stat_addr, irq_mask_addr; static void (*dispatch_internal)(void); +static int is_ext_irq_cascaded; +static unsigned int ext_irq_start, ext_irq_end; static void bcm63xx_init_irq(void) { @@ -73,6 +89,9 @@ static void bcm63xx_init_irq(void) case BCM6358_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6358_REG; irq_mask_addr += PERF_IRQMASK_6358_REG; + is_ext_irq_cascaded = 1; + ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; + ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; break; default: BUG(); @@ -84,7 +103,11 @@ static void bcm63xx_init_irq(void) static inline void handle_internal(int intbit) { - do_IRQ(intbit + IRQ_INTERNAL_BASE); + if (is_ext_irq_cascaded && + intbit >= ext_irq_start && intbit <= ext_irq_end) + do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE); + else + do_IRQ(intbit + IRQ_INTERNAL_BASE); } /* @@ -128,14 +151,16 @@ asmlinkage void plat_irq_dispatch(void) do_IRQ(7); if (cause & CAUSEF_IP2) dispatch_internal(); - if (cause & CAUSEF_IP3) - do_IRQ(IRQ_EXT_0); - if (cause & CAUSEF_IP4) - do_IRQ(IRQ_EXT_1); - if (cause & CAUSEF_IP5) - do_IRQ(IRQ_EXT_2); - if (cause & CAUSEF_IP6) - do_IRQ(IRQ_EXT_3); + if (!is_ext_irq_cascaded) { + if (cause & CAUSEF_IP3) + do_IRQ(IRQ_EXT_0); + if (cause & CAUSEF_IP4) + do_IRQ(IRQ_EXT_1); + if (cause & CAUSEF_IP5) + do_IRQ(IRQ_EXT_2); + if (cause & CAUSEF_IP6) + do_IRQ(IRQ_EXT_3); + } } while (1); } @@ -143,9 +168,8 @@ asmlinkage void plat_irq_dispatch(void) * internal IRQs operations: only mask/unmask on PERF irq mask * register. */ -static inline void bcm63xx_internal_irq_mask(struct irq_data *d) +static void internal_irq_mask(unsigned int irq) { - unsigned int irq = d->irq - IRQ_INTERNAL_BASE; u32 mask; mask = bcm_readl(irq_mask_addr); @@ -153,9 +177,8 @@ static inline void bcm63xx_internal_irq_mask(struct irq_data *d) bcm_writel(mask, irq_mask_addr); } -static void bcm63xx_internal_irq_unmask(struct irq_data *d) +static void internal_irq_unmask(unsigned int irq) { - unsigned int irq = d->irq - IRQ_INTERNAL_BASE; u32 mask; mask = bcm_readl(irq_mask_addr); @@ -163,33 +186,47 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d) bcm_writel(mask, irq_mask_addr); } +static void bcm63xx_internal_irq_mask(struct irq_data *d) +{ + internal_irq_mask(d->irq - IRQ_INTERNAL_BASE); +} + +static void bcm63xx_internal_irq_unmask(struct irq_data *d) +{ + internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE); +} + /* * external IRQs operations: mask/unmask and clear on PERF external * irq control register. */ static void bcm63xx_external_irq_mask(struct irq_data *d) { - unsigned int irq = d->irq - IRQ_EXT_BASE; + unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg &= ~EXTIRQ_CFG_MASK(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); + if (is_ext_irq_cascaded) + internal_irq_mask(irq + ext_irq_start); } static void bcm63xx_external_irq_unmask(struct irq_data *d) { - unsigned int irq = d->irq - IRQ_EXT_BASE; + unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg |= EXTIRQ_CFG_MASK(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); + if (is_ext_irq_cascaded) + internal_irq_unmask(irq + ext_irq_start); } static void bcm63xx_external_irq_clear(struct irq_data *d) { - unsigned int irq = d->irq - IRQ_EXT_BASE; + unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); @@ -197,25 +234,10 @@ static void bcm63xx_external_irq_clear(struct irq_data *d) bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); } -static unsigned int bcm63xx_external_irq_startup(struct irq_data *d) -{ - set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); - irq_enable_hazard(); - bcm63xx_external_irq_unmask(d); - return 0; -} - -static void bcm63xx_external_irq_shutdown(struct irq_data *d) -{ - bcm63xx_external_irq_mask(d); - clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); - irq_disable_hazard(); -} - static int bcm63xx_external_irq_set_type(struct irq_data *d, unsigned int flow_type) { - unsigned int irq = d->irq - IRQ_EXT_BASE; + unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg; flow_type &= IRQ_TYPE_SENSE_MASK; @@ -275,9 +297,6 @@ static struct irq_chip bcm63xx_internal_irq_chip = { static struct irq_chip bcm63xx_external_irq_chip = { .name = "bcm63xx_epic", - .irq_startup = bcm63xx_external_irq_startup, - .irq_shutdown = bcm63xx_external_irq_shutdown, - .irq_ack = bcm63xx_external_irq_clear, .irq_mask = bcm63xx_external_irq_mask, @@ -292,6 +311,12 @@ static struct irqaction cpu_ip2_cascade_action = { .flags = IRQF_NO_THREAD, }; +static struct irqaction cpu_ext_cascade_action = { + .handler = no_action, + .name = "cascade_extirq", + .flags = IRQF_NO_THREAD, +}; + void __init arch_init_irq(void) { int i; @@ -302,9 +327,14 @@ void __init arch_init_irq(void) irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, handle_level_irq); - for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) + for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + 4; ++i) irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, handle_edge_irq); - setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); + if (!is_ext_irq_cascaded) { + for (i = 3; i < 7; ++i) + setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); + } + + setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); } diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h index 5f95577c8213..0c3074b871b8 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h @@ -3,13 +3,11 @@ #include -#define IRQ_MIPS_BASE 0 #define IRQ_INTERNAL_BASE 8 - -#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3) -#define IRQ_EXT_0 (IRQ_EXT_BASE + 0) -#define IRQ_EXT_1 (IRQ_EXT_BASE + 1) -#define IRQ_EXT_2 (IRQ_EXT_BASE + 2) -#define IRQ_EXT_3 (IRQ_EXT_BASE + 3) +#define IRQ_EXTERNAL_BASE 100 +#define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0) +#define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1) +#define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2) +#define IRQ_EXT_3 (IRQ_EXTERNAL_BASE + 3) #endif /* ! BCM63XX_IRQ_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h new file mode 100644 index 000000000000..9332e788a5c9 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/irq.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_BCM63XX_IRQ_H +#define __ASM_MACH_BCM63XX_IRQ_H + +#define NR_IRQS 128 +#define MIPS_CPU_IRQ_BASE 0 + +#endif From 015ce7d3526be8a969390fe625cb18f958e85a51 Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:28 +0100 Subject: [PATCH 051/119] MIPS: BCM63XX: Introduce bcm_readq & bcm_writeq. Needed for upcoming 6368 CPU support. [ralf@linux-mips.org: Changed function names as per Sergei's comments.] Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2896/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h index 91180fac6ed9..72477a6441dd 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h @@ -49,9 +49,11 @@ #define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a)) #define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a)) #define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a)) +#define bcm_readq(a) (*(volatile u64 *) BCM_REGS_VA(a)) #define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) #define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) #define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) +#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v)) /* * IO helpers to access register set for current CPU From 71a43927b3bfe1a42cbf7bb174b170f06fa00a1a Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:33 +0100 Subject: [PATCH 052/119] MIPS: BCM63XX: Handle 64 bits irq stat register in irq code. bcm6368 has larger irq registers, prepare for this. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2898/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 82 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 76 insertions(+), 6 deletions(-) diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index cdf352b040a9..11f8942b82dc 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -20,11 +20,17 @@ #include static void __dispatch_internal(void) __maybe_unused; +static void __dispatch_internal_64(void) __maybe_unused; +static void __internal_irq_mask_32(unsigned int irq) __maybe_unused; +static void __internal_irq_mask_64(unsigned int irq) __maybe_unused; +static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; +static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #ifndef BCMCPU_RUNTIME_DETECT #ifdef CONFIG_BCM63XX_CPU_6338 #define irq_stat_reg PERF_IRQSTAT_6338_REG #define irq_mask_reg PERF_IRQMASK_6338_REG +#define irq_bits 32 #define is_ext_irq_cascaded 0 #define ext_irq_start 0 #define ext_irq_end 0 @@ -32,6 +38,7 @@ static void __dispatch_internal(void) __maybe_unused; #ifdef CONFIG_BCM63XX_CPU_6345 #define irq_stat_reg PERF_IRQSTAT_6345_REG #define irq_mask_reg PERF_IRQMASK_6345_REG +#define irq_bits 32 #define is_ext_irq_cascaded 0 #define ext_irq_start 0 #define ext_irq_end 0 @@ -39,7 +46,7 @@ static void __dispatch_internal(void) __maybe_unused; #ifdef CONFIG_BCM63XX_CPU_6348 #define irq_stat_reg PERF_IRQSTAT_6348_REG #define irq_mask_reg PERF_IRQMASK_6348_REG -#define dispatch_internal __dispatch_internal +#define irq_bits 32 #define is_ext_irq_cascaded 0 #define ext_irq_start 0 #define ext_irq_end 0 @@ -47,13 +54,21 @@ static void __dispatch_internal(void) __maybe_unused; #ifdef CONFIG_BCM63XX_CPU_6358 #define irq_stat_reg PERF_IRQSTAT_6358_REG #define irq_mask_reg PERF_IRQMASK_6358_REG -#define dispatch_internal __dispatch_internal +#define irq_bits 32 #define is_ext_irq_cascaded 1 #define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE) #define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE) #endif -#define dispatch_internal __dispatch_internal +#if irq_bits == 32 +#define dispatch_internal __dispatch_internal +#define internal_irq_mask __internal_irq_mask_32 +#define internal_irq_unmask __internal_irq_unmask_32 +#else +#define dispatch_internal __dispatch_internal_64 +#define internal_irq_mask __internal_irq_mask_64 +#define internal_irq_unmask __internal_irq_unmask_64 +#endif #define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg) #define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg) @@ -67,9 +82,13 @@ static u32 irq_stat_addr, irq_mask_addr; static void (*dispatch_internal)(void); static int is_ext_irq_cascaded; static unsigned int ext_irq_start, ext_irq_end; +static void (*internal_irq_mask)(unsigned int irq); +static void (*internal_irq_unmask)(unsigned int irq); static void bcm63xx_init_irq(void) { + int irq_bits; + irq_stat_addr = bcm63xx_regset_address(RSET_PERF); irq_mask_addr = bcm63xx_regset_address(RSET_PERF); @@ -77,18 +96,22 @@ static void bcm63xx_init_irq(void) case BCM6338_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6338_REG; irq_mask_addr += PERF_IRQMASK_6338_REG; + irq_bits = 32; break; case BCM6345_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6345_REG; irq_mask_addr += PERF_IRQMASK_6345_REG; + irq_bits = 32; break; case BCM6348_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6348_REG; irq_mask_addr += PERF_IRQMASK_6348_REG; + irq_bits = 32; break; case BCM6358_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6358_REG; irq_mask_addr += PERF_IRQMASK_6358_REG; + irq_bits = 32; is_ext_irq_cascaded = 1; ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; @@ -97,7 +120,15 @@ static void bcm63xx_init_irq(void) BUG(); } - dispatch_internal = __dispatch_internal; + if (irq_bits == 32) { + dispatch_internal = __dispatch_internal; + internal_irq_mask = __internal_irq_mask_32; + internal_irq_unmask = __internal_irq_unmask_32; + } else { + dispatch_internal = __dispatch_internal_64; + internal_irq_mask = __internal_irq_mask_64; + internal_irq_unmask = __internal_irq_unmask_64; + } } #endif /* ! BCMCPU_RUNTIME_DETECT */ @@ -137,6 +168,27 @@ static void __dispatch_internal(void) } } +static void __dispatch_internal_64(void) +{ + u64 pending; + static int i; + + pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr); + + if (!pending) + return ; + + while (1) { + int to_call = i; + + i = (i + 1) & 0x3f; + if (pending & (1ull << to_call)) { + handle_internal(to_call); + break; + } + } +} + asmlinkage void plat_irq_dispatch(void) { u32 cause; @@ -168,7 +220,7 @@ asmlinkage void plat_irq_dispatch(void) * internal IRQs operations: only mask/unmask on PERF irq mask * register. */ -static void internal_irq_mask(unsigned int irq) +static void __internal_irq_mask_32(unsigned int irq) { u32 mask; @@ -177,7 +229,16 @@ static void internal_irq_mask(unsigned int irq) bcm_writel(mask, irq_mask_addr); } -static void internal_irq_unmask(unsigned int irq) +static void __internal_irq_mask_64(unsigned int irq) +{ + u64 mask; + + mask = bcm_readq(irq_mask_addr); + mask &= ~(1ull << irq); + bcm_writeq(mask, irq_mask_addr); +} + +static void __internal_irq_unmask_32(unsigned int irq) { u32 mask; @@ -186,6 +247,15 @@ static void internal_irq_unmask(unsigned int irq) bcm_writel(mask, irq_mask_addr); } +static void __internal_irq_unmask_64(unsigned int irq) +{ + u64 mask; + + mask = bcm_readq(irq_mask_addr); + mask |= (1ull << irq); + bcm_writeq(mask, irq_mask_addr); +} + static void bcm63xx_internal_irq_mask(struct irq_data *d) { internal_irq_mask(d->irq - IRQ_INTERNAL_BASE); From 6224892c819e96898534c107c72b80a1a8e75abf Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:34 +0100 Subject: [PATCH 053/119] MIPS: BCM63XX: Add external irq support for non 6348 CPUs. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2899/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 131 ++++++++++++++---- arch/mips/bcm63xx/setup.c | 30 +++- .../include/asm/mach-bcm63xx/bcm63xx_regs.h | 31 +++-- 3 files changed, 149 insertions(+), 43 deletions(-) diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 11f8942b82dc..9f538846b3f7 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -34,6 +34,9 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #define is_ext_irq_cascaded 0 #define ext_irq_start 0 #define ext_irq_end 0 +#define ext_irq_count 4 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338 +#define ext_irq_cfg_reg2 0 #endif #ifdef CONFIG_BCM63XX_CPU_6345 #define irq_stat_reg PERF_IRQSTAT_6345_REG @@ -42,6 +45,9 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #define is_ext_irq_cascaded 0 #define ext_irq_start 0 #define ext_irq_end 0 +#define ext_irq_count 0 +#define ext_irq_cfg_reg1 0 +#define ext_irq_cfg_reg2 0 #endif #ifdef CONFIG_BCM63XX_CPU_6348 #define irq_stat_reg PERF_IRQSTAT_6348_REG @@ -50,6 +56,9 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #define is_ext_irq_cascaded 0 #define ext_irq_start 0 #define ext_irq_end 0 +#define ext_irq_count 4 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348 +#define ext_irq_cfg_reg2 0 #endif #ifdef CONFIG_BCM63XX_CPU_6358 #define irq_stat_reg PERF_IRQSTAT_6358_REG @@ -58,6 +67,9 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #define is_ext_irq_cascaded 1 #define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE) #define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE) +#define ext_irq_count 4 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358 +#define ext_irq_cfg_reg2 0 #endif #if irq_bits == 32 @@ -81,7 +93,9 @@ static inline void bcm63xx_init_irq(void) static u32 irq_stat_addr, irq_mask_addr; static void (*dispatch_internal)(void); static int is_ext_irq_cascaded; +static unsigned int ext_irq_count; static unsigned int ext_irq_start, ext_irq_end; +static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; static void (*internal_irq_mask)(unsigned int irq); static void (*internal_irq_unmask)(unsigned int irq); @@ -107,14 +121,18 @@ static void bcm63xx_init_irq(void) irq_stat_addr += PERF_IRQSTAT_6348_REG; irq_mask_addr += PERF_IRQMASK_6348_REG; irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; break; case BCM6358_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6358_REG; irq_mask_addr += PERF_IRQMASK_6358_REG; irq_bits = 32; + ext_irq_count = 4; is_ext_irq_cascaded = 1; ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; break; default: BUG(); @@ -132,6 +150,13 @@ static void bcm63xx_init_irq(void) } #endif /* ! BCMCPU_RUNTIME_DETECT */ +static inline u32 get_ext_irq_perf_reg(int irq) +{ + if (irq < 4) + return ext_irq_cfg_reg1; + return ext_irq_cfg_reg2; +} + static inline void handle_internal(int intbit) { if (is_ext_irq_cascaded && @@ -273,11 +298,17 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d) static void bcm63xx_external_irq_mask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; - u32 reg; + u32 reg, regaddr; - reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); - reg &= ~EXTIRQ_CFG_MASK(irq); - bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); + regaddr = get_ext_irq_perf_reg(irq); + reg = bcm_perf_readl(regaddr); + + if (BCMCPU_IS_6348()) + reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); + else + reg &= ~EXTIRQ_CFG_MASK(irq % 4); + + bcm_perf_writel(reg, regaddr); if (is_ext_irq_cascaded) internal_irq_mask(irq + ext_irq_start); } @@ -285,11 +316,18 @@ static void bcm63xx_external_irq_mask(struct irq_data *d) static void bcm63xx_external_irq_unmask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; - u32 reg; + u32 reg, regaddr; + + regaddr = get_ext_irq_perf_reg(irq); + reg = bcm_perf_readl(regaddr); + + if (BCMCPU_IS_6348()) + reg |= EXTIRQ_CFG_MASK_6348(irq % 4); + else + reg |= EXTIRQ_CFG_MASK(irq % 4); + + bcm_perf_writel(reg, regaddr); - reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); - reg |= EXTIRQ_CFG_MASK(irq); - bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); if (is_ext_irq_cascaded) internal_irq_unmask(irq + ext_irq_start); } @@ -297,58 +335,93 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d) static void bcm63xx_external_irq_clear(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; - u32 reg; + u32 reg, regaddr; - reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); - reg |= EXTIRQ_CFG_CLEAR(irq); - bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); + regaddr = get_ext_irq_perf_reg(irq); + reg = bcm_perf_readl(regaddr); + + if (BCMCPU_IS_6348()) + reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); + else + reg |= EXTIRQ_CFG_CLEAR(irq % 4); + + bcm_perf_writel(reg, regaddr); } static int bcm63xx_external_irq_set_type(struct irq_data *d, unsigned int flow_type) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; - u32 reg; + u32 reg, regaddr; + int levelsense, sense, bothedge; flow_type &= IRQ_TYPE_SENSE_MASK; if (flow_type == IRQ_TYPE_NONE) flow_type = IRQ_TYPE_LEVEL_LOW; - reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); + levelsense = sense = bothedge = 0; switch (flow_type) { case IRQ_TYPE_EDGE_BOTH: - reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); - reg |= EXTIRQ_CFG_BOTHEDGE(irq); + bothedge = 1; break; case IRQ_TYPE_EDGE_RISING: - reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); - reg |= EXTIRQ_CFG_SENSE(irq); - reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); + sense = 1; break; case IRQ_TYPE_EDGE_FALLING: - reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); - reg &= ~EXTIRQ_CFG_SENSE(irq); - reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); break; case IRQ_TYPE_LEVEL_HIGH: - reg |= EXTIRQ_CFG_LEVELSENSE(irq); - reg |= EXTIRQ_CFG_SENSE(irq); + levelsense = 1; + sense = 1; break; case IRQ_TYPE_LEVEL_LOW: - reg |= EXTIRQ_CFG_LEVELSENSE(irq); - reg &= ~EXTIRQ_CFG_SENSE(irq); + levelsense = 1; break; default: printk(KERN_ERR "bogus flow type combination given !\n"); return -EINVAL; } - bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); + + regaddr = get_ext_irq_perf_reg(irq); + reg = bcm_perf_readl(regaddr); + irq %= 4; + + if (BCMCPU_IS_6348()) { + if (levelsense) + reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); + else + reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq); + if (sense) + reg |= EXTIRQ_CFG_SENSE_6348(irq); + else + reg &= ~EXTIRQ_CFG_SENSE_6348(irq); + if (bothedge) + reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); + else + reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); + } + + if (BCMCPU_IS_6338() || BCMCPU_IS_6358()) { + if (levelsense) + reg |= EXTIRQ_CFG_LEVELSENSE(irq); + else + reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); + if (sense) + reg |= EXTIRQ_CFG_SENSE(irq); + else + reg &= ~EXTIRQ_CFG_SENSE(irq); + if (bothedge) + reg |= EXTIRQ_CFG_BOTHEDGE(irq); + else + reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); + } + + bcm_perf_writel(reg, regaddr); irqd_set_trigger_type(d, flow_type); if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) @@ -397,12 +470,12 @@ void __init arch_init_irq(void) irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, handle_level_irq); - for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + 4; ++i) + for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i) irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, handle_edge_irq); if (!is_ext_irq_cascaded) { - for (i = 3; i < 7; ++i) + for (i = 3; i < 3 + ext_irq_count; ++i) setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); } diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index 04a349928643..d209f85d87bb 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -63,13 +63,33 @@ static void bcm6348_a1_reboot(void) void bcm63xx_machine_reboot(void) { - u32 reg; + u32 reg, perf_regs[2] = { 0, 0 }; + unsigned int i; /* mask and clear all external irq */ - reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); - reg &= ~EXTIRQ_CFG_MASK_ALL; - reg |= EXTIRQ_CFG_CLEAR_ALL; - bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); + switch (bcm63xx_get_cpu_id()) { + case BCM6338_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; + break; + case BCM6348_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348; + break; + case BCM6358_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358; + break; + } + + for (i = 0; i < 2; i++) { + reg = bcm_perf_readl(perf_regs[i]); + if (BCMCPU_IS_6348()) { + reg &= ~EXTIRQ_CFG_MASK_ALL_6348; + reg |= EXTIRQ_CFG_CLEAR_ALL_6348; + } else { + reg &= ~EXTIRQ_CFG_MASK_ALL; + reg |= EXTIRQ_CFG_CLEAR_ALL; + } + bcm_perf_writel(reg, perf_regs[i]); + } if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1)) bcm6348_a1_reboot(); diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 25676cdeb30f..2b3a2d6bdb03 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -100,16 +100,29 @@ #define PERF_IRQSTAT_6358_REG 0x10 /* External Interrupt Configuration register */ -#define PERF_EXTIRQ_CFG_REG 0x14 -#define EXTIRQ_CFG_SENSE(x) (1 << (x)) -#define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) -#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) -#define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) -#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) -#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) +#define PERF_EXTIRQ_CFG_REG_6338 0x14 +#define PERF_EXTIRQ_CFG_REG_6348 0x14 +#define PERF_EXTIRQ_CFG_REG_6358 0x14 -#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) -#define EXTIRQ_CFG_MASK_ALL (0xf << 15) +/* for 6348 only */ +#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x)) +#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5)) +#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10)) +#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15)) +#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20)) +#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25)) +#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10) +#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15) + +/* for all others */ +#define EXTIRQ_CFG_SENSE(x) (1 << (x)) +#define EXTIRQ_CFG_STAT(x) (1 << (x + 4)) +#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8)) +#define EXTIRQ_CFG_MASK(x) (1 << (x + 12)) +#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16)) +#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20)) +#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8) +#define EXTIRQ_CFG_MASK_ALL (0xf << 12) /* Soft Reset register */ #define PERF_SOFTRESET_REG 0x28 From 04712f3ff6e3a42ef658b55b0f99478f4f0682e3 Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 4 Nov 2011 19:09:35 +0100 Subject: [PATCH 054/119] MIPS: BCM63XX: Add support for bcm6368 CPU. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2892/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/Kconfig | 4 + arch/mips/bcm63xx/clk.c | 70 ++++++++++- arch/mips/bcm63xx/cpu.c | 79 ++++++++++--- arch/mips/bcm63xx/dev-uart.c | 2 +- arch/mips/bcm63xx/irq.c | 24 +++- arch/mips/bcm63xx/prom.c | 7 +- .../include/asm/mach-bcm63xx/bcm63xx_cpu.h | 99 ++++++++++++++++ .../include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 + .../include/asm/mach-bcm63xx/bcm63xx_regs.h | 109 +++++++++++++++++- arch/mips/include/asm/mach-bcm63xx/ioremap.h | 4 + arch/mips/pci/pci-bcm63xx.c | 4 +- 11 files changed, 377 insertions(+), 27 deletions(-) diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig index fb177d6df066..6b1b9ad8d857 100644 --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -20,6 +20,10 @@ config BCM63XX_CPU_6348 config BCM63XX_CPU_6358 bool "support 6358 CPU" select HW_HAS_PCI + +config BCM63XX_CPU_6368 + bool "support 6368 CPU" + select HW_HAS_PCI endmenu source "arch/mips/bcm63xx/boards/Kconfig" diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index 2c68ee9ccee2..9d57c71b7b58 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -112,6 +113,34 @@ static struct clk clk_ephy = { .set = ephy_set, }; +/* + * Ethernet switch clock + */ +static void enetsw_set(struct clk *clk, int enable) +{ + if (!BCMCPU_IS_6368()) + return; + bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN | + CKCTL_6368_SWPKT_USB_EN | + CKCTL_6368_SWPKT_SAR_EN, enable); + if (enable) { + u32 val; + + /* reset switch core afer clock change */ + val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); + val &= ~SOFTRESET_6368_ENETSW_MASK; + bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); + msleep(10); + val |= SOFTRESET_6368_ENETSW_MASK; + bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); + msleep(10); + } +} + +static struct clk clk_enetsw = { + .set = enetsw_set, +}; + /* * PCM clock */ @@ -131,9 +160,10 @@ static struct clk clk_pcm = { */ static void usbh_set(struct clk *clk, int enable) { - if (!BCMCPU_IS_6348()) - return; - bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); + if (BCMCPU_IS_6348()) + bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable); } static struct clk clk_usbh = { @@ -161,6 +191,36 @@ static struct clk clk_spi = { .set = spi_set, }; +/* + * XTM clock + */ +static void xtm_set(struct clk *clk, int enable) +{ + if (!BCMCPU_IS_6368()) + return; + + bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN | + CKCTL_6368_SWPKT_SAR_EN, enable); + + if (enable) { + u32 val; + + /* reset sar core afer clock change */ + val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); + val &= ~SOFTRESET_6368_SAR_MASK; + bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); + mdelay(1); + val |= SOFTRESET_6368_SAR_MASK; + bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); + mdelay(1); + } +} + + +static struct clk clk_xtm = { + .set = xtm_set, +}; + /* * Internal peripheral clock */ @@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id) return &clk_enet0; if (!strcmp(id, "enet1")) return &clk_enet1; + if (!strcmp(id, "enetsw")) + return &clk_enetsw; if (!strcmp(id, "ephy")) return &clk_ephy; if (!strcmp(id, "usbh")) return &clk_usbh; if (!strcmp(id, "spi")) return &clk_spi; + if (!strcmp(id, "xtm")) + return &clk_xtm; if (!strcmp(id, "periph")) return &clk_periph; if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 8bd5133eafd1..80941687b9dd 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -63,6 +63,15 @@ static const int bcm6358_irqs[] = { }; +static const unsigned long bcm6368_regs_base[] = { + __GEN_CPU_REGS_TABLE(6368) +}; + +static const int bcm6368_irqs[] = { + __GEN_CPU_IRQ_TABLE(6368) + +}; + u16 __bcm63xx_get_cpu_id(void) { return bcm63xx_cpu_id; @@ -89,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void) static unsigned int detect_cpu_clock(void) { - unsigned int tmp, n1 = 0, n2 = 0, m1 = 0; - - /* BCM6338 has a fixed 240 Mhz frequency */ - if (BCMCPU_IS_6338()) + switch (bcm63xx_get_cpu_id()) { + case BCM6338_CPU_ID: + /* BCM6338 has a fixed 240 Mhz frequency */ return 240000000; - /* BCM6345 has a fixed 140Mhz frequency */ - if (BCMCPU_IS_6345()) + case BCM6345_CPU_ID: + /* BCM6345 has a fixed 140Mhz frequency */ return 140000000; - /* - * frequency depends on PLL configuration: - */ - if (BCMCPU_IS_6348()) { + case BCM6348_CPU_ID: + { + unsigned int tmp, n1, n2, m1; + /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; @@ -111,17 +119,47 @@ static unsigned int detect_cpu_clock(void) n1 += 1; n2 += 2; m1 += 1; + return (16 * 1000000 * n1 * n2) / m1; } - if (BCMCPU_IS_6358()) { + case BCM6358_CPU_ID: + { + unsigned int tmp, n1, n2, m1; + /* 16MHz * N1 * N2 / M1_CPU */ tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; + return (16 * 1000000 * n1 * n2) / m1; } - return (16 * 1000000 * n1 * n2) / m1; + case BCM6368_CPU_ID: + { + unsigned int tmp, p1, p2, ndiv, m1; + + /* (64MHz / P1) * P2 * NDIV / M1_CPU */ + tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG); + + p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> + DMIPSPLLCFG_6368_P1_SHIFT; + + p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> + DMIPSPLLCFG_6368_P2_SHIFT; + + ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >> + DMIPSPLLCFG_6368_NDIV_SHIFT; + + tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG); + m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> + DMIPSPLLDIV_6368_MDIV_SHIFT; + + return (((64 * 1000000) / p1) * p2 * ndiv) / m1; + } + + default: + BUG(); + } } /* @@ -143,7 +181,7 @@ static unsigned int detect_memory_size(void) banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; } - if (BCMCPU_IS_6358()) { + if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { val = bcm_memc_readl(MEMC_CFG_REG); rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; @@ -188,9 +226,18 @@ void __init bcm63xx_cpu_init(void) bcm63xx_irqs = bcm6345_irqs; break; case CPU_BMIPS4350: - expected_cpu_id = BCM6358_CPU_ID; - bcm63xx_regs_base = bcm6358_regs_base; - bcm63xx_irqs = bcm6358_irqs; + switch (read_c0_prid() & 0xf0) { + case 0x10: + expected_cpu_id = BCM6358_CPU_ID; + bcm63xx_regs_base = bcm6358_regs_base; + bcm63xx_irqs = bcm6358_irqs; + break; + case 0x30: + expected_cpu_id = BCM6368_CPU_ID; + bcm63xx_regs_base = bcm6368_regs_base; + bcm63xx_irqs = bcm6368_irqs; + break; + } break; } diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c index c2963da0253e..d6e42c608325 100644 --- a/arch/mips/bcm63xx/dev-uart.c +++ b/arch/mips/bcm63xx/dev-uart.c @@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id) if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) return -ENODEV; - if (id == 1 && !BCMCPU_IS_6358()) + if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368())) return -ENODEV; if (id == 0) { diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 9f538846b3f7..9a216a451d92 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -71,6 +71,17 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358 #define ext_irq_cfg_reg2 0 #endif +#ifdef CONFIG_BCM63XX_CPU_6368 +#define irq_stat_reg PERF_IRQSTAT_6368_REG +#define irq_mask_reg PERF_IRQMASK_6368_REG +#define irq_bits 64 +#define is_ext_irq_cascaded 1 +#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE) +#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE) +#define ext_irq_count 6 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368 +#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368 +#endif #if irq_bits == 32 #define dispatch_internal __dispatch_internal @@ -134,6 +145,17 @@ static void bcm63xx_init_irq(void) ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; break; + case BCM6368_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6368_REG; + irq_mask_addr += PERF_IRQMASK_6368_REG; + irq_bits = 64; + ext_irq_count = 6; + is_ext_irq_cascaded = 1; + ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; + ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; + ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; + break; default: BUG(); } @@ -406,7 +428,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); } - if (BCMCPU_IS_6338() || BCMCPU_IS_6358()) { + if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { if (levelsense) reg |= EXTIRQ_CFG_LEVELSENSE(irq); else diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index be252efa0757..99d7f405cbeb 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -32,9 +32,12 @@ void __init prom_init(void) mask = CKCTL_6345_ALL_SAFE_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_ALL_SAFE_EN; - else - /* BCMCPU_IS_6358() */ + else if (BCMCPU_IS_6358()) mask = CKCTL_6358_ALL_SAFE_EN; + else if (BCMCPU_IS_6368()) + mask = CKCTL_6368_ALL_SAFE_EN; + else + mask = 0; reg = bcm_perf_readl(PERF_CKCTL_REG); reg &= ~mask; diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 46f03322e2ca..23403a32c158 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -13,6 +13,7 @@ #define BCM6345_CPU_ID 0x6345 #define BCM6348_CPU_ID 0x6348 #define BCM6358_CPU_ID 0x6358 +#define BCM6368_CPU_ID 0x6368 void __init bcm63xx_cpu_init(void); u16 __bcm63xx_get_cpu_id(void); @@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void); # define BCMCPU_IS_6358() (0) #endif +#ifdef CONFIG_BCM63XX_CPU_6368 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM6368_CPU_ID +# endif +# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) +#else +# define BCMCPU_IS_6368() (0) +#endif + #ifndef bcm63xx_get_cpu_id #error "No CPU support configured" #endif @@ -307,6 +321,47 @@ enum bcm63xx_regs_set { #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) +/* + * 6368 register sets base address + */ +#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) +#define BCM_6368_PERF_BASE (0xb0000000) +#define BCM_6368_TIMER_BASE (0xb0000040) +#define BCM_6368_WDT_BASE (0xb000005c) +#define BCM_6368_UART0_BASE (0xb0000100) +#define BCM_6368_UART1_BASE (0xb0000120) +#define BCM_6368_GPIO_BASE (0xb0000080) +#define BCM_6368_SPI_BASE (0xdeadbeef) +#define BCM_6368_SPI2_BASE (0xb0000800) +#define BCM_6368_UDC0_BASE (0xdeadbeef) +#define BCM_6368_OHCI0_BASE (0xb0001600) +#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) +#define BCM_6368_USBH_PRIV_BASE (0xb0001700) +#define BCM_6368_MPI_BASE (0xb0001000) +#define BCM_6368_PCMCIA_BASE (0xb0001054) +#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) +#define BCM_6368_M2M_BASE (0xdeadbeef) +#define BCM_6368_DSL_BASE (0xdeadbeef) +#define BCM_6368_ENET0_BASE (0xdeadbeef) +#define BCM_6368_ENET1_BASE (0xdeadbeef) +#define BCM_6368_ENETDMA_BASE (0xb0006800) +#define BCM_6368_ENETDMAC_BASE (0xb0006a00) +#define BCM_6368_ENETDMAS_BASE (0xb0006c00) +#define BCM_6368_ENETSW_BASE (0xb0f00000) +#define BCM_6368_EHCI0_BASE (0xb0001500) +#define BCM_6368_SDRAM_BASE (0xdeadbeef) +#define BCM_6368_MEMC_BASE (0xb0001200) +#define BCM_6368_DDR_BASE (0xb0001280) +#define BCM_6368_ATM_BASE (0xdeadbeef) +#define BCM_6368_XTM_BASE (0xb0001800) +#define BCM_6368_XTMDMA_BASE (0xb0005000) +#define BCM_6368_XTMDMAC_BASE (0xb0005200) +#define BCM_6368_XTMDMAS_BASE (0xb0005400) +#define BCM_6368_PCM_BASE (0xb0004000) +#define BCM_6368_PCMDMA_BASE (0xb0005800) +#define BCM_6368_PCMDMAC_BASE (0xb0005a00) +#define BCM_6368_PCMDMAS_BASE (0xb0005c00) + extern const unsigned long *bcm63xx_regs_base; @@ -410,6 +465,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) #ifdef CONFIG_BCM63XX_CPU_6358 __GEN_RSET(6358) #endif +#ifdef CONFIG_BCM63XX_CPU_6368 + __GEN_RSET(6368) +#endif #endif /* unreached */ return 0; @@ -574,6 +632,47 @@ enum bcm63xx_irq { #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) +/* + * 6368 irqs + */ +#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) + +#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) +#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6368_ENET0_IRQ 0 +#define BCM_6368_ENET1_IRQ 0 +#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) +#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_6368_PCMCIA_IRQ 0 +#define BCM_6368_ENET0_RXDMA_IRQ 0 +#define BCM_6368_ENET0_TXDMA_IRQ 0 +#define BCM_6368_ENET1_RXDMA_IRQ 0 +#define BCM_6368_ENET1_TXDMA_IRQ 0 +#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13) +#define BCM_6368_ATM_IRQ 0 +#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0) +#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1) +#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2) +#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3) +#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4) +#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5) +#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6) +#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7) +#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11) +#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8) + +#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30) +#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31) +#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20) +#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21) +#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22) +#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23) +#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) +#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) + extern const int *bcm63xx_irqs; #define __GEN_CPU_IRQ_TABLE(__cpu) \ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 3999ec0aa7f5..3d5de96d4036 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void) return 8; case BCM6345_CPU_ID: return 16; + case BCM6368_CPU_ID: + return 38; case BCM6348_CPU_ID: default: return 37; diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 2b3a2d6bdb03..50057507c4e7 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -83,6 +83,37 @@ CKCTL_6358_USBSU_EN | \ CKCTL_6358_EPHY_EN) +#define CKCTL_6368_VDSL_QPROC_EN (1 << 2) +#define CKCTL_6368_VDSL_AFE_EN (1 << 3) +#define CKCTL_6368_VDSL_BONDING_EN (1 << 4) +#define CKCTL_6368_VDSL_EN (1 << 5) +#define CKCTL_6368_PHYMIPS_EN (1 << 6) +#define CKCTL_6368_SWPKT_USB_EN (1 << 7) +#define CKCTL_6368_SWPKT_SAR_EN (1 << 8) +#define CKCTL_6368_SPI_CLK_EN (1 << 9) +#define CKCTL_6368_USBD_CLK_EN (1 << 10) +#define CKCTL_6368_SAR_CLK_EN (1 << 11) +#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12) +#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13) +#define CKCTL_6368_PCM_CLK_EN (1 << 14) +#define CKCTL_6368_USBH_CLK_EN (1 << 15) +#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) +#define CKCTL_6368_NAND_CLK_EN (1 << 17) +#define CKCTL_6368_IPSEC_CLK_EN (1 << 17) + +#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ + CKCTL_6368_SWPKT_SAR_EN | \ + CKCTL_6368_SPI_CLK_EN | \ + CKCTL_6368_USBD_CLK_EN | \ + CKCTL_6368_SAR_CLK_EN | \ + CKCTL_6368_ROBOSW_CLK_EN | \ + CKCTL_6368_UTOPIA_CLK_EN | \ + CKCTL_6368_PCM_CLK_EN | \ + CKCTL_6368_USBH_CLK_EN | \ + CKCTL_6368_DISABLE_GLESS_EN | \ + CKCTL_6368_NAND_CLK_EN | \ + CKCTL_6368_IPSEC_CLK_EN) + /* System PLL Control register */ #define PERF_SYS_PLL_CTL_REG 0x8 #define SYS_PLL_SOFT_RESET 0x1 @@ -92,17 +123,22 @@ #define PERF_IRQMASK_6345_REG 0xc #define PERF_IRQMASK_6348_REG 0xc #define PERF_IRQMASK_6358_REG 0xc +#define PERF_IRQMASK_6368_REG 0x20 /* Interrupt Status register */ #define PERF_IRQSTAT_6338_REG 0x10 #define PERF_IRQSTAT_6345_REG 0x10 #define PERF_IRQSTAT_6348_REG 0x10 #define PERF_IRQSTAT_6358_REG 0x10 +#define PERF_IRQSTAT_6368_REG 0x28 /* External Interrupt Configuration register */ #define PERF_EXTIRQ_CFG_REG_6338 0x14 #define PERF_EXTIRQ_CFG_REG_6348 0x14 #define PERF_EXTIRQ_CFG_REG_6358 0x14 +#define PERF_EXTIRQ_CFG_REG_6368 0x18 + +#define PERF_EXTIRQ_CFG_REG2_6368 0x1c /* for 6348 only */ #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x)) @@ -126,6 +162,7 @@ /* Soft Reset register */ #define PERF_SOFTRESET_REG 0x28 +#define PERF_SOFTRESET_6368_REG 0x10 #define SOFTRESET_6338_SPI_MASK (1 << 0) #define SOFTRESET_6338_ENET_MASK (1 << 2) @@ -166,6 +203,15 @@ SOFTRESET_6348_ACLC_MASK | \ SOFTRESET_6348_ADSLMIPSPLL_MASK) +#define SOFTRESET_6368_SPI_MASK (1 << 0) +#define SOFTRESET_6368_MPI_MASK (1 << 3) +#define SOFTRESET_6368_EPHY_MASK (1 << 6) +#define SOFTRESET_6368_SAR_MASK (1 << 7) +#define SOFTRESET_6368_ENETSW_MASK (1 << 10) +#define SOFTRESET_6368_USBS_MASK (1 << 11) +#define SOFTRESET_6368_USBH_MASK (1 << 12) +#define SOFTRESET_6368_PCM_MASK (1 << 13) + /* MIPS PLL control register */ #define PERF_MIPSPLLCTL_REG 0x34 #define MIPSPLLCTL_N1_SHIFT 20 @@ -421,6 +467,44 @@ #define GPIO_MODE_6358_SERIAL_LED (1 << 10) #define GPIO_MODE_6358_UTOPIA (1 << 12) +#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) +#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) +#define GPIO_MODE_6368_SYS_IRQ (1 << 2) +#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3) +#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4) +#define GPIO_MODE_6368_INET_LED (1 << 5) +#define GPIO_MODE_6368_EPHY0_LED (1 << 6) +#define GPIO_MODE_6368_EPHY1_LED (1 << 7) +#define GPIO_MODE_6368_EPHY2_LED (1 << 8) +#define GPIO_MODE_6368_EPHY3_LED (1 << 9) +#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10) +#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11) +#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12) +#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13) +#define GPIO_MODE_6368_USBD_LED (1 << 14) +#define GPIO_MODE_6368_NTR_PULSE (1 << 15) +#define GPIO_MODE_6368_PCI_REQ1 (1 << 16) +#define GPIO_MODE_6368_PCI_GNT1 (1 << 17) +#define GPIO_MODE_6368_PCI_INTB (1 << 18) +#define GPIO_MODE_6368_PCI_REQ0 (1 << 19) +#define GPIO_MODE_6368_PCI_GNT0 (1 << 20) +#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22) +#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23) +#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24) +#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25) +#define GPIO_MODE_6368_EBI_CS2 (1 << 26) +#define GPIO_MODE_6368_EBI_CS3 (1 << 27) +#define GPIO_MODE_6368_SPI_SSN2 (1 << 28) +#define GPIO_MODE_6368_SPI_SSN3 (1 << 29) +#define GPIO_MODE_6368_SPI_SSN4 (1 << 30) +#define GPIO_MODE_6368_SPI_SSN5 (1 << 31) + + +#define GPIO_BASEMODE_6368_REG 0x38 +#define GPIO_BASEMODE_6368_UART2 0x1 +#define GPIO_BASEMODE_6368_GPIO 0x0 +#define GPIO_BASEMODE_6368_MASK 0x7 +/* those bits must be kept as read in gpio basemode register*/ /************************************************************************* * _REG relative to RSET_ENET @@ -631,7 +715,9 @@ * _REG relative to RSET_USBH_PRIV *************************************************************************/ -#define USBH_PRIV_SWAP_REG 0x0 +#define USBH_PRIV_SWAP_6358_REG 0x0 +#define USBH_PRIV_SWAP_6368_REG 0x1c + #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 @@ -641,7 +727,13 @@ #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) -#define USBH_PRIV_TEST_REG 0x24 +#define USBH_PRIV_TEST_6358_REG 0x24 +#define USBH_PRIV_TEST_6368_REG 0x14 + +#define USBH_PRIV_SETUP_6368_REG 0x28 +#define USBH_PRIV_SETUP_IOC_SHIFT 4 +#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) + /************************************************************************* @@ -837,6 +929,19 @@ #define DMIPSPLLCFG_N2_SHIFT 29 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) +#define DDR_DMIPSPLLCFG_6368_REG 0x20 +#define DMIPSPLLCFG_6368_P1_SHIFT 0 +#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) +#define DMIPSPLLCFG_6368_P2_SHIFT 4 +#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT) +#define DMIPSPLLCFG_6368_NDIV_SHIFT 16 +#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT) + +#define DDR_DMIPSPLLDIV_6368_REG 0x24 +#define DMIPSPLLDIV_6368_MDIV_SHIFT 0 +#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT) + + /************************************************************************* * _REG relative to RSET_M2M *************************************************************************/ diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h index e3fe04dc50bd..ef94ba73646e 100644 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h @@ -18,6 +18,10 @@ static inline int is_bcm63xx_internal_registers(phys_t offset) if (offset >= 0xfff00000) return 1; break; + case BCM6368_CPU_ID: + if (offset >= 0xb0000000 && offset < 0xb1000000) + return 1; + break; } return 0; } diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c index 82e0fde1dba0..39eb7c417e2f 100644 --- a/arch/mips/pci/pci-bcm63xx.c +++ b/arch/mips/pci/pci-bcm63xx.c @@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void) unsigned int mem_size; u32 val; - if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358()) + if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368()) return -ENODEV; if (!bcm63xx_pci_enabled) @@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void) /* setup PCI to local bus access, used by PCI device to target * local RAM while bus mastering */ bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); - if (BCMCPU_IS_6358()) + if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) val = MPI_SP0_REMAP_ENABLE_MASK; else val = 0; From d61fcfe2bbb27d4da18c609cf279627ae1b74151 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 16 Nov 2011 20:10:36 +0100 Subject: [PATCH 055/119] MIPS: BCM63xx: Fix SDRAM size computation for BCM6345 Instead of hardcoding the amount of available RAM, read the number of effective multiples of 8MB from SDRAM_MBASE_REG. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3008/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/cpu.c | 6 ++++-- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 80941687b9dd..8f0d6c7725ea 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -170,8 +170,10 @@ static unsigned int detect_memory_size(void) unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; u32 val; - if (BCMCPU_IS_6345()) - return (8 * 1024 * 1024); + if (BCMCPU_IS_6345()) { + val = bcm_sdram_readl(SDRAM_MBASE_REG); + return (val * 8 * 1024 * 1024); + } if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { val = bcm_sdram_readl(SDRAM_CFG_REG); diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 50057507c4e7..6c9940fb7b71 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -895,6 +895,8 @@ #define SDRAM_CFG_BANK_SHIFT 13 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) +#define SDRAM_MBASE_REG 0xc + #define SDRAM_PRIO_REG 0x2C #define SDRAM_PRIO_MIPS_SHIFT 29 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) From e1c96c8620539f056291fe42f742f331f5d291b1 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 16 Nov 2011 19:11:12 +0100 Subject: [PATCH 056/119] MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address Though BCM6345 does not technically have the same MPI register layout than the other SoCs, reading the chip-select registers is done the same way, and particularly for chip-select 0, which is the boot flash. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3009/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/boards/board_bcm963xx.c | 21 ++++++------------- .../include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 +- 2 files changed, 7 insertions(+), 16 deletions(-) diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 40b223b603be..ac948c25c9f0 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -709,15 +709,9 @@ void __init board_prom_init(void) char cfe_version[32]; u32 val; - /* read base address of boot chip select (0) - * 6345 does not have MPI but boots from standard - * MIPS Flash address */ - if (BCMCPU_IS_6345()) - val = 0x1fc00000; - else { - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; - } + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; boot_addr = (u8 *)KSEG1ADDR(val); /* dump cfe version */ @@ -893,12 +887,9 @@ int __init board_register_devices(void) bcm63xx_dsp_register(&board.dsp); /* read base address of boot chip select (0) */ - if (BCMCPU_IS_6345()) - val = 0x1fc00000; - else { - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; - } + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + mtd_resources[0].start = val; mtd_resources[0].end = 0x1FFFFFFF; diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 23403a32c158..5b8d15bb5fe8 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -215,7 +215,7 @@ enum bcm63xx_regs_set { #define BCM_6345_ENETDMAS_BASE (0xfffe2a00) #define BCM_6345_ENETSW_BASE (0xdeadbeef) #define BCM_6345_PCMCIA_BASE (0xfffe2028) -#define BCM_6345_MPI_BASE (0xdeadbeef) +#define BCM_6345_MPI_BASE (0xfffe2000) #define BCM_6345_OHCI0_BASE (0xfffe2100) #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) From 92d9ae20269461deeefc46fbcdb8d428c4aa8d18 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 16 Nov 2011 19:11:21 +0100 Subject: [PATCH 057/119] MIPS: BCM63xx: Fix GPIO set/get for BCM6345 On BCM6345, the register offsets for the set/get GPIO registers is wrong. Use the same logic as the one present in arch/mips/bcm63xx/irq.c to define the correct gpio_out_low_reg value when support for BCM6345 is compiled in. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3010/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/gpio.c | 41 ++++++++++++++++--- .../include/asm/mach-bcm63xx/bcm63xx_regs.h | 1 + 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index f560fe7d38dd..a6c2135dbf38 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 2008 Maxime Bizon - * Copyright (C) 2008 Florian Fainelli + * Copyright (C) 2008-2011 Florian Fainelli */ #include @@ -18,6 +18,34 @@ #include #include +#ifndef BCMCPU_RUNTIME_DETECT +#define gpio_out_low_reg GPIO_DATA_LO_REG +#ifdef CONFIG_BCM63XX_CPU_6345 +#ifdef gpio_out_low_reg +#undef gpio_out_low_reg +#define gpio_out_low_reg GPIO_DATA_LO_REG_6345 +#endif /* gpio_out_low_reg */ +#endif /* CONFIG_BCM63XX_CPU_6345 */ + +static inline void bcm63xx_gpio_out_low_reg_init(void) +{ +} +#else /* ! BCMCPU_RUNTIME_DETECT */ +static u32 gpio_out_low_reg; + +static void bcm63xx_gpio_out_low_reg_init(void) +{ + switch (bcm63xx_get_cpu_id()) { + case BCM6345_CPU_ID: + gpio_out_low_reg = GPIO_DATA_LO_REG_6345; + break; + default: + gpio_out_low_reg = GPIO_DATA_LO_REG; + break; + } +} +#endif /* ! BCMCPU_RUNTIME_DETECT */ + static DEFINE_SPINLOCK(bcm63xx_gpio_lock); static u32 gpio_out_low, gpio_out_high; @@ -33,7 +61,7 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip, BUG(); if (gpio < 32) { - reg = GPIO_DATA_LO_REG; + reg = gpio_out_low_reg; mask = 1 << gpio; v = &gpio_out_low; } else { @@ -60,7 +88,7 @@ static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio) BUG(); if (gpio < 32) { - reg = GPIO_DATA_LO_REG; + reg = gpio_out_low_reg; mask = 1 << gpio; } else { reg = GPIO_DATA_HI_REG; @@ -125,8 +153,11 @@ static struct gpio_chip bcm63xx_gpio_chip = { int __init bcm63xx_gpio_init(void) { - gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG); - gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG); + bcm63xx_gpio_out_low_reg_init(); + + gpio_out_low = bcm_gpio_readl(gpio_out_low_reg); + if (!BCMCPU_IS_6345()) + gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG); bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count(); pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio); diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 6c9940fb7b71..94d4faad29a1 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -437,6 +437,7 @@ #define GPIO_CTL_LO_REG 0x4 #define GPIO_DATA_HI_REG 0x8 #define GPIO_DATA_LO_REG 0xC +#define GPIO_DATA_LO_REG_6345 0x8 /* GPIO mux registers and constants */ #define GPIO_MODE_REG 0x18 From b15a6d62b5482966d0605e24c728bea8f7f876eb Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 16 Nov 2011 19:49:58 +0100 Subject: [PATCH 058/119] MIPS: BCM63XX: generate WLAN MAC address after registering ethernet devices. In case the MAC address pool is not big enough to also register a WLAN device prefer registering the Ethernet devices. [ralf@linux-mips.org: Fixed formatting as per Sergei's complaint.] Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3013/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/boards/board_bcm963xx.c | 25 ++++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index ac948c25c9f0..e62461f817d7 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -791,18 +791,6 @@ void __init board_prom_init(void) } bcm_gpio_writel(val, GPIO_MODE_REG); - - /* Generate MAC address for WLAN and - * register our SPROM */ -#ifdef CONFIG_SSB_PCIHOST - if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { - memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); - memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); - if (ssb_arch_register_fallback_sprom( - &bcm63xx_get_fallback_sprom) < 0) - printk(KERN_ERR PFX "failed to register fallback SPROM\n"); - } -#endif } /* @@ -886,6 +874,19 @@ int __init board_register_devices(void) if (board.has_dsp) bcm63xx_dsp_register(&board.dsp); + /* Generate MAC address for WLAN and register our SPROM, + * do this after registering enet devices + */ +#ifdef CONFIG_SSB_PCIHOST + if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { + memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); + if (ssb_arch_register_fallback_sprom( + &bcm63xx_get_fallback_sprom) < 0) + pr_err(PFX "failed to register fallback SPROM\n"); + } +#endif + /* read base address of boot chip select (0) */ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); val &= MPI_CSBASE_BASE_MASK; From 1bbb6c1b7b6c4dffd0d5ff8787691e0ea4c6a796 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 10 Nov 2011 22:30:24 -0800 Subject: [PATCH 059/119] MIPS: BMIPS: Fix up Kconfig settings Factor out common BMIPS options into "CPU_BMIPS". Add L2 cache for BMIPS5000. Add CPU_MIPS32 to satisfy checks in page.h, r4k_switch.S, tlb-r4k.c, etc. Signed-off-by: Kevin Cernekee Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2953/ Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d46f1da18a3c..e7587ac3265a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1413,51 +1413,36 @@ config CPU_CAVIUM_OCTEON config CPU_BMIPS3300 bool "BMIPS3300" depends on SYS_HAS_CPU_BMIPS3300 - select DMA_NONCOHERENT - select IRQ_CPU - select SWAP_IO_SPACE - select SYS_SUPPORTS_32BIT_KERNEL - select WEAK_ORDERING + select CPU_BMIPS help Broadcom BMIPS3300 processors. config CPU_BMIPS4350 bool "BMIPS4350" depends on SYS_HAS_CPU_BMIPS4350 - select CPU_SUPPORTS_32BIT_KERNEL - select DMA_NONCOHERENT - select IRQ_CPU - select SWAP_IO_SPACE + select CPU_BMIPS select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU - select WEAK_ORDERING help Broadcom BMIPS4350 ("VIPER") processors. config CPU_BMIPS4380 bool "BMIPS4380" depends on SYS_HAS_CPU_BMIPS4380 - select CPU_SUPPORTS_32BIT_KERNEL - select DMA_NONCOHERENT - select IRQ_CPU - select SWAP_IO_SPACE + select CPU_BMIPS select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU - select WEAK_ORDERING help Broadcom BMIPS4380 processors. config CPU_BMIPS5000 bool "BMIPS5000" depends on SYS_HAS_CPU_BMIPS5000 - select CPU_SUPPORTS_32BIT_KERNEL + select CPU_BMIPS select CPU_SUPPORTS_HIGHMEM - select DMA_NONCOHERENT - select IRQ_CPU - select SWAP_IO_SPACE + select MIPS_CPU_SCACHE select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU - select WEAK_ORDERING help Broadcom BMIPS5000 processors. @@ -1518,6 +1503,15 @@ config CPU_LOONGSON2 select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM +config CPU_BMIPS + bool + select CPU_MIPS32 + select CPU_SUPPORTS_32BIT_KERNEL + select DMA_NONCOHERENT + select IRQ_CPU + select SWAP_IO_SPACE + select WEAK_ORDERING + config SYS_HAS_CPU_LOONGSON2E bool From 15fb0a150938ad68561bab6aa895685665bef08c Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 10 Nov 2011 22:30:25 -0800 Subject: [PATCH 060/119] MIPS: Clean up whitespace warning in hazards.h Use a tab on second and subsequent lines of multiline #if's, for consistency with the next commit. Signed-off-by: Kevin Cernekee Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2954/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/hazards.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 4e332165d7b7..8f630e495532 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -139,8 +139,8 @@ do { \ } while (0) #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ - defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ - defined(CONFIG_CPU_R5500) + defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ + defined(CONFIG_CPU_R5500) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. From 1c7c44519a12d79af1f599a8cc4997e1230025ed Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Wed, 16 Nov 2011 01:25:40 +0000 Subject: [PATCH 061/119] MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS Add CONFIG_CPU_BMIPS* in all of the right places, so that BMIPS kernel images will compile and run. Signed-off-by: Kevin Cernekee Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2955/ Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 1 + arch/mips/include/asm/hazards.h | 3 ++- arch/mips/include/asm/module.h | 4 +++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0be318609fc6..4fedf5a51d96 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -157,6 +157,7 @@ ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON)))) cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon endif cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 +cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 8f630e495532..b4c20e4f87cd 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -87,7 +87,8 @@ do { \ : "=r" (tmp)); \ } while (0) -#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY) +#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \ + defined(CONFIG_CPU_BMIPS) /* * These are slightly complicated by the fact that we guarantee R1 kernels to diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index bc01a02cacd8..a73bc19ead4e 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -74,7 +74,9 @@ search_module_dbetables(unsigned long addr) } #endif -#ifdef CONFIG_CPU_MIPS32_R1 +#ifdef CONFIG_CPU_BMIPS +#define MODULE_PROC_FAMILY "BMIPS " +#elif defined CONFIG_CPU_MIPS32_R1 #define MODULE_PROC_FAMILY "MIPS32_R1 " #elif defined CONFIG_CPU_MIPS32_R2 #define MODULE_PROC_FAMILY "MIPS32_R2 " From 020232f1ca216a5edd702539f60a8d312d5c3108 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Wed, 16 Nov 2011 01:25:44 +0000 Subject: [PATCH 062/119] MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operations Several BMIPS-specific CP0 registers are used for SMP boot and other operations. Signed-off-by: Kevin Cernekee Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2956/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mipsregs.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 2ea7b817feb8..7f87d824eeb0 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1106,7 +1106,7 @@ do { \ #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) -/* BMIPS4380 */ +/* BMIPS43xx */ #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) @@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config) __BUILD_SET_C0(intcontrol) __BUILD_SET_C0(intctl) __BUILD_SET_C0(srsmap) +__BUILD_SET_C0(brcm_config_0) +__BUILD_SET_C0(brcm_bus_pll) +__BUILD_SET_C0(brcm_reset) +__BUILD_SET_C0(brcm_cmt_intr) +__BUILD_SET_C0(brcm_cmt_ctrl) +__BUILD_SET_C0(brcm_config) +__BUILD_SET_C0(brcm_mode) #endif /* !__ASSEMBLY__ */ From 18a1eef92dcd6b8ec30fcbe6e074e5d33ef31c02 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Wed, 16 Nov 2011 01:25:44 +0000 Subject: [PATCH 063/119] MIPS: BMIPS: Introduce bmips.h bmips.h contains BMIPS definitions that are useful for SMP, vector relocation, performance counters, etc. Signed-off-by: Kevin Cernekee Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2973/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/bmips.h | 110 ++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 arch/mips/include/asm/bmips.h diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h new file mode 100644 index 000000000000..552a65a0cf2b --- /dev/null +++ b/arch/mips/include/asm/bmips.h @@ -0,0 +1,110 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) + * + * Definitions for BMIPS processors + */ +#ifndef _ASM_BMIPS_H +#define _ASM_BMIPS_H + +#include +#include +#include +#include +#include + +/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */ +#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \ + (unsigned long) \ + ((read_c0_brcm_cbr() >> 18) << 18))) + +#define BMIPS_RAC_CONFIG 0x00000000 +#define BMIPS_RAC_ADDRESS_RANGE 0x00000004 +#define BMIPS_RAC_CONFIG_1 0x00000008 +#define BMIPS_L2_CONFIG 0x0000000c +#define BMIPS_LMB_CONTROL 0x0000001c +#define BMIPS_SYSTEM_BASE 0x00000020 +#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000 +#define BMIPS_PERF_CONTROL_0 0x00020004 +#define BMIPS_PERF_CONTROL_1 0x00020008 +#define BMIPS_PERF_COUNTER_0 0x00020010 +#define BMIPS_PERF_COUNTER_1 0x00020014 +#define BMIPS_PERF_COUNTER_2 0x00020018 +#define BMIPS_PERF_COUNTER_3 0x0002001c +#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000 +#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000 + +#define BMIPS_NMI_RESET_VEC 0x80000000 +#define BMIPS_WARM_RESTART_VEC 0x80000380 + +#define ZSCM_REG_BASE 0x97000000 + +#if !defined(__ASSEMBLY__) + +#include +#include + +extern struct plat_smp_ops bmips_smp_ops; +extern char bmips_reset_nmi_vec; +extern char bmips_reset_nmi_vec_end; +extern char bmips_smp_movevec; +extern char bmips_smp_int_vec; +extern char bmips_smp_int_vec_end; + +extern int bmips_smp_enabled; +extern int bmips_cpu_offset; +extern cpumask_t bmips_booted_mask; + +extern void bmips_ebase_setup(void); +extern asmlinkage void plat_wired_tlb_setup(void); + +static inline unsigned long bmips_read_zscm_reg(unsigned int offset) +{ + unsigned long ret; + + __asm__ __volatile__( + ".set push\n" + ".set noreorder\n" + "cache %1, 0(%2)\n" + "sync\n" + "_ssnop\n" + "_ssnop\n" + "_ssnop\n" + "_ssnop\n" + "_ssnop\n" + "_ssnop\n" + "_ssnop\n" + "mfc0 %0, $28, 3\n" + "_ssnop\n" + ".set pop\n" + : "=&r" (ret) + : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset) + : "memory"); + return ret; +} + +static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data) +{ + __asm__ __volatile__( + ".set push\n" + ".set noreorder\n" + "mtc0 %0, $28, 3\n" + "_ssnop\n" + "_ssnop\n" + "_ssnop\n" + "cache %1, 0(%2)\n" + "_ssnop\n" + "_ssnop\n" + "_ssnop\n" + : /* no outputs */ + : "r" (data), + "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset) + : "memory"); +} + +#endif /* !defined(__ASSEMBLY__) */ + +#endif /* _ASM_BMIPS_H */ From 34bd92e27becdc2c8b50d200a329da5e9b8174d9 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Wed, 16 Nov 2011 01:25:44 +0000 Subject: [PATCH 064/119] MIPS: Add NMI notifier Allow the board support code to register a raw notifier callback for NMI, similar to what is done for CU2 exceptions. Signed-off-by: Kevin Cernekee Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2958/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/traps.h | 12 ++++++++++++ arch/mips/kernel/traps.c | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h index 90ff2f497c50..4edab87eebd2 100644 --- a/arch/mips/include/asm/traps.h +++ b/arch/mips/include/asm/traps.h @@ -25,4 +25,16 @@ extern void (*board_nmi_handler_setup)(void); extern void (*board_ejtag_handler_setup)(void); extern void (*board_bind_eic_interrupt)(int irq, int regset); +extern int register_nmi_notifier(struct notifier_block *nb); + +#define nmi_notifier(fn, pri) \ +({ \ + static struct notifier_block fn##_nb = { \ + .notifier_call = fn, \ + .priority = pri \ + }; \ + \ + register_nmi_notifier(&fn##_nb); \ +}) + #endif /* _ASM_TRAPS_H */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 5c8a49d55054..33945aaa9b1b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1339,9 +1339,18 @@ void ejtag_exception_handler(struct pt_regs *regs) /* * NMI exception handler. + * No lock; only written during early bootup by CPU 0. */ +static RAW_NOTIFIER_HEAD(nmi_chain); + +int register_nmi_notifier(struct notifier_block *nb) +{ + return raw_notifier_chain_register(&nmi_chain, nb); +} + NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) { + raw_notifier_call_chain(&nmi_chain, 0, regs); bust_spinlocks(1); printk("NMI taken!!!!\n"); die("NMI", regs); From 6fb97effee5374ac5b2a0e8666d380e83b5ca1e3 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Wed, 16 Nov 2011 01:25:45 +0000 Subject: [PATCH 065/119] MIPS: Add board_ebase_setup() Some systems need to relocate the MIPS exception vector base during trap initialization. Add a hook to make this possible. Signed-off-by: Kevin Cernekee Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2959/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/traps.h | 1 + arch/mips/kernel/traps.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h index 4edab87eebd2..ff74aec3561a 100644 --- a/arch/mips/include/asm/traps.h +++ b/arch/mips/include/asm/traps.h @@ -24,6 +24,7 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); extern void (*board_nmi_handler_setup)(void); extern void (*board_ejtag_handler_setup)(void); extern void (*board_bind_eic_interrupt)(int irq, int regset); +extern void (*board_ebase_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 33945aaa9b1b..c18dfd4428fe 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -91,6 +91,7 @@ int (*board_be_handler)(struct pt_regs *regs, int is_fixup); void (*board_nmi_handler_setup)(void); void (*board_ejtag_handler_setup)(void); void (*board_bind_eic_interrupt)(int irq, int regset); +void (*board_ebase_setup)(void); static void show_raw_backtrace(unsigned long reg29) @@ -1691,6 +1692,8 @@ void __init trap_init(void) ebase += (read_c0_ebase() & 0x3ffff000); } + if (board_ebase_setup) + board_ebase_setup(); per_cpu_trap_init(); /* From df0ac8a406718360aa08e632a73a805a6cc4cb27 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Wed, 16 Nov 2011 01:25:45 +0000 Subject: [PATCH 066/119] MIPS: BMIPS: Add SMP support code for BMIPS43xx/BMIPS5000 Initial commit of BMIPS SMP support code. Smoke-tested on a variety of BMIPS4350, BMIPS4380, and BMIPS5000 platforms. Signed-off-by: Kevin Cernekee Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2977/ Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 + arch/mips/kernel/Makefile | 1 + arch/mips/kernel/bmips_vec.S | 255 +++++++++++++++++++ arch/mips/kernel/smp-bmips.c | 458 +++++++++++++++++++++++++++++++++++ 4 files changed, 717 insertions(+) create mode 100644 arch/mips/kernel/bmips_vec.S create mode 100644 arch/mips/kernel/smp-bmips.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e7587ac3265a..9c4a61074d48 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1986,6 +1986,9 @@ config CPU_HAS_SMARTMIPS config CPU_HAS_WB bool +config XKS01 + bool + # # Vectored interrupt mode is an R2 feature # diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 1a966183e353..01983215977d 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o +obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o obj-$(CONFIG_MIPS_MT) += mips-mt.o obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S new file mode 100644 index 000000000000..e908e81330b1 --- /dev/null +++ b/arch/mips/kernel/bmips_vec.S @@ -0,0 +1,255 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) + * + * Reset/NMI/re-entry vectors for BMIPS processors + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + .macro BARRIER + .set mips32 + _ssnop + _ssnop + _ssnop + .set mips0 + .endm + + __CPUINIT + +/*********************************************************************** + * Alternate CPU1 startup vector for BMIPS4350 + * + * On some systems the bootloader has already started CPU1 and configured + * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is + * triggered by the SW1 interrupt. If that is the case we try to move + * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380. + ***********************************************************************/ + +LEAF(bmips_smp_movevec) + la k0, 1f + li k1, CKSEG1 + or k0, k1 + jr k0 + +1: + /* clear IV, pending IPIs */ + mtc0 zero, CP0_CAUSE + + /* re-enable IRQs to wait for SW1 */ + li k0, ST0_IE | ST0_BEV | STATUSF_IP1 + mtc0 k0, CP0_STATUS + + /* set up CPU1 CBR; move BASE to 0xa000_0000 */ + li k0, 0xff400000 + mtc0 k0, $22, 6 + li k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1 + or k0, k1 + li k1, 0xa0080000 + sw k1, 0(k0) + + /* wait here for SW1 interrupt from bmips_boot_secondary() */ + wait + + la k0, bmips_reset_nmi_vec + li k1, CKSEG1 + or k0, k1 + jr k0 +END(bmips_smp_movevec) + +/*********************************************************************** + * Reset/NMI vector + * For BMIPS processors that can relocate their exception vectors, this + * entire function gets copied to 0x8000_0000. + ***********************************************************************/ + +NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) + .set push + .set noat + .align 4 + +#ifdef CONFIG_SMP + /* if the NMI bit is clear, assume this is a CPU1 reset instead */ + li k1, (1 << 19) + mfc0 k0, CP0_STATUS + and k0, k1 + beqz k0, bmips_smp_entry + +#if defined(CONFIG_CPU_BMIPS5000) + /* if we're not on core 0, this must be the SMP boot signal */ + li k1, (3 << 25) + mfc0 k0, $22 + and k0, k1 + bnez k0, bmips_smp_entry +#endif +#endif /* CONFIG_SMP */ + + /* nope, it's just a regular NMI */ + SAVE_ALL + move a0, sp + + /* clear EXL, ERL, BEV so that TLB refills still work */ + mfc0 k0, CP0_STATUS + li k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE + or k0, k1 + xor k0, k1 + mtc0 k0, CP0_STATUS + BARRIER + + /* jump to the NMI handler function */ + la k0, nmi_handler + jr k0 + + RESTORE_ALL + .set mips3 + eret + +/*********************************************************************** + * CPU1 reset vector (used for the initial boot only) + * This is still part of bmips_reset_nmi_vec(). + ***********************************************************************/ + +#ifdef CONFIG_SMP + +bmips_smp_entry: + + /* set up CP0 STATUS; enable FPU */ + li k0, 0x30000000 + mtc0 k0, CP0_STATUS + BARRIER + + /* set local CP0 CONFIG to make kseg0 cacheable, write-back */ + mfc0 k0, CP0_CONFIG + ori k0, 0x07 + xori k0, 0x04 + mtc0 k0, CP0_CONFIG + +#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) + /* initialize CPU1's local I-cache */ + li k0, 0x80000000 + li k1, 0x80010000 + mtc0 zero, $28 + mtc0 zero, $28, 1 + BARRIER + +1: cache Index_Store_Tag_I, 0(k0) + addiu k0, 16 + bne k0, k1, 1b +#elif defined(CONFIG_CPU_BMIPS5000) + /* set exception vector base */ + la k0, ebase + lw k0, 0(k0) + mtc0 k0, $15, 1 + BARRIER +#endif + + /* jump back to kseg0 in case we need to remap the kseg1 area */ + la k0, 1f + jr k0 +1: + la k0, bmips_enable_xks01 + jalr k0 + + /* use temporary stack to set up upper memory TLB */ + li sp, BMIPS_WARM_RESTART_VEC + la k0, plat_wired_tlb_setup + jalr k0 + + /* switch to permanent stack and continue booting */ + + .global bmips_secondary_reentry +bmips_secondary_reentry: + la k0, bmips_smp_boot_sp + lw sp, 0(k0) + la k0, bmips_smp_boot_gp + lw gp, 0(k0) + la k0, start_secondary + jr k0 + +#endif /* CONFIG_SMP */ + + .align 4 + .global bmips_reset_nmi_vec_end +bmips_reset_nmi_vec_end: + +END(bmips_reset_nmi_vec) + + .set pop + .previous + +/*********************************************************************** + * CPU1 warm restart vector (used for second and subsequent boots). + * Also used for S2 standby recovery (PM). + * This entire function gets copied to (BMIPS_WARM_RESTART_VEC) + ***********************************************************************/ + +LEAF(bmips_smp_int_vec) + + .align 4 + mfc0 k0, CP0_STATUS + ori k0, 0x01 + xori k0, 0x01 + mtc0 k0, CP0_STATUS + eret + + .align 4 + .global bmips_smp_int_vec_end +bmips_smp_int_vec_end: + +END(bmips_smp_int_vec) + +/*********************************************************************** + * XKS01 support + * Certain CPUs support extending kseg0 to 1024MB. + ***********************************************************************/ + + __CPUINIT + +LEAF(bmips_enable_xks01) + +#if defined(CONFIG_XKS01) + +#if defined(CONFIG_CPU_BMIPS4380) + mfc0 t0, $22, 3 + li t1, 0x1ff0 + li t2, (1 << 12) | (1 << 9) + or t0, t1 + xor t0, t1 + or t0, t2 + mtc0 t0, $22, 3 + BARRIER +#elif defined(CONFIG_CPU_BMIPS5000) + mfc0 t0, $22, 5 + li t1, 0x01ff + li t2, (1 << 8) | (1 << 5) + or t0, t1 + xor t0, t1 + or t0, t2 + mtc0 t0, $22, 5 + BARRIER +#else + +#error Missing XKS01 setup + +#endif + +#endif /* defined(CONFIG_XKS01) */ + + jr ra + +END(bmips_enable_xks01) + + .previous diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c new file mode 100644 index 000000000000..58fe71afd879 --- /dev/null +++ b/arch/mips/kernel/smp-bmips.c @@ -0,0 +1,458 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) + * + * SMP support for BMIPS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int __maybe_unused max_cpus = 1; + +/* these may be configured by the platform code */ +int bmips_smp_enabled = 1; +int bmips_cpu_offset; +cpumask_t bmips_booted_mask; + +#ifdef CONFIG_SMP + +/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ +unsigned long bmips_smp_boot_sp; +unsigned long bmips_smp_boot_gp; + +static void bmips_send_ipi_single(int cpu, unsigned int action); +static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id); + +/* SW interrupts 0,1 are used for interprocessor signaling */ +#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) +#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) + +#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) +#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) +#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) +#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) + +static void __init bmips_smp_setup(void) +{ + int i; + +#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) + /* arbitration priority */ + clear_c0_brcm_cmt_ctrl(0x30); + + /* NBK and weak order flags */ + set_c0_brcm_config_0(0x30000); + + /* + * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread + * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output + * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output + */ + change_c0_brcm_cmt_intr(0xf8018000, + (0x02 << 27) | (0x03 << 15)); + + /* single core, 2 threads (2 pipelines) */ + max_cpus = 2; +#elif defined(CONFIG_CPU_BMIPS5000) + /* enable raceless SW interrupts */ + set_c0_brcm_config(0x03 << 22); + + /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ + change_c0_brcm_mode(0x1f << 27, 0x02 << 27); + + /* N cores, 2 threads per core */ + max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; + + /* clear any pending SW interrupts */ + for (i = 0; i < max_cpus; i++) { + write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); + write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); + } +#endif + + if (!bmips_smp_enabled) + max_cpus = 1; + + /* this can be overridden by the BSP */ + if (!board_ebase_setup) + board_ebase_setup = &bmips_ebase_setup; + + for (i = 0; i < max_cpus; i++) { + __cpu_number_map[i] = 1; + __cpu_logical_map[i] = 1; + set_cpu_possible(i, 1); + set_cpu_present(i, 1); + } +} + +/* + * IPI IRQ setup - runs on CPU0 + */ +static void bmips_prepare_cpus(unsigned int max_cpus) +{ + if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, + "smp_ipi0", NULL)) + panic("Can't request IPI0 interrupt\n"); + if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, + "smp_ipi1", NULL)) + panic("Can't request IPI1 interrupt\n"); +} + +/* + * Tell the hardware to boot CPUx - runs on CPU0 + */ +static void bmips_boot_secondary(int cpu, struct task_struct *idle) +{ + bmips_smp_boot_sp = __KSTK_TOS(idle); + bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); + mb(); + + /* + * Initial boot sequence for secondary CPU: + * bmips_reset_nmi_vec @ a000_0000 -> + * bmips_smp_entry -> + * plat_wired_tlb_setup (cached function call; optional) -> + * start_secondary (cached jump) + * + * Warm restart sequence: + * play_dead WAIT loop -> + * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> + * eret to play_dead -> + * bmips_secondary_reentry -> + * start_secondary + */ + + pr_info("SMP: Booting CPU%d...\n", cpu); + + if (cpumask_test_cpu(cpu, &bmips_booted_mask)) + bmips_send_ipi_single(cpu, 0); + else { +#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) + set_c0_brcm_cmt_ctrl(0x01); +#elif defined(CONFIG_CPU_BMIPS5000) + if (cpu & 0x01) + write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); + else { + /* + * core N thread 0 was already booted; just + * pulse the NMI line + */ + bmips_write_zscm_reg(0x210, 0xc0000000); + udelay(10); + bmips_write_zscm_reg(0x210, 0x00); + } +#endif + cpumask_set_cpu(cpu, &bmips_booted_mask); + } +} + +/* + * Early setup - runs on secondary CPU after cache probe + */ +static void bmips_init_secondary(void) +{ + /* move NMI vector to kseg0, in case XKS01 is enabled */ + +#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) + void __iomem *cbr = BMIPS_GET_CBR(); + unsigned long old_vec; + + old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1); + __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1); + + clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); +#elif defined(CONFIG_CPU_BMIPS5000) + write_c0_brcm_bootvec(read_c0_brcm_bootvec() & + (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000)); + + write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); +#endif + + /* make sure there won't be a timer interrupt for a little while */ + write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); + + irq_enable_hazard(); + set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE); + irq_enable_hazard(); +} + +/* + * Late setup - runs on secondary CPU before entering the idle loop + */ +static void bmips_smp_finish(void) +{ + pr_info("SMP: CPU%d is running\n", smp_processor_id()); +} + +/* + * Runs on CPU0 after all CPUs have been booted + */ +static void bmips_cpus_done(void) +{ +} + +#if defined(CONFIG_CPU_BMIPS5000) + +/* + * BMIPS5000 raceless IPIs + * + * Each CPU has two inbound SW IRQs which are independent of all other CPUs. + * IPI0 is used for SMP_RESCHEDULE_YOURSELF + * IPI1 is used for SMP_CALL_FUNCTION + */ + +static void bmips_send_ipi_single(int cpu, unsigned int action) +{ + write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); +} + +static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id) +{ + int action = irq - IPI0_IRQ; + + write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); + + if (action == 0) + scheduler_ipi(); + else + smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +#else + +/* + * BMIPS43xx racey IPIs + * + * We use one inbound SW IRQ for each CPU. + * + * A spinlock must be held in order to keep CPUx from accidentally clearing + * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The + * same spinlock is used to protect the action masks. + */ + +static DEFINE_SPINLOCK(ipi_lock); +static DEFINE_PER_CPU(int, ipi_action_mask); + +static void bmips_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + + spin_lock_irqsave(&ipi_lock, flags); + set_c0_cause(cpu ? C_SW1 : C_SW0); + per_cpu(ipi_action_mask, cpu) |= action; + irq_enable_hazard(); + spin_unlock_irqrestore(&ipi_lock, flags); +} + +static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id) +{ + unsigned long flags; + int action, cpu = irq - IPI0_IRQ; + + spin_lock_irqsave(&ipi_lock, flags); + action = __get_cpu_var(ipi_action_mask); + per_cpu(ipi_action_mask, cpu) = 0; + clear_c0_cause(cpu ? C_SW1 : C_SW0); + spin_unlock_irqrestore(&ipi_lock, flags); + + if (action & SMP_RESCHEDULE_YOURSELF) + scheduler_ipi(); + if (action & SMP_CALL_FUNCTION) + smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +#endif /* BMIPS type */ + +static void bmips_send_ipi_mask(const struct cpumask *mask, + unsigned int action) +{ + unsigned int i; + + for_each_cpu(i, mask) + bmips_send_ipi_single(i, action); +} + +#ifdef CONFIG_HOTPLUG_CPU + +static int bmips_cpu_disable(void) +{ + unsigned int cpu = smp_processor_id(); + + if (cpu == 0) + return -EBUSY; + + pr_info("SMP: CPU%d is offline\n", cpu); + + cpu_clear(cpu, cpu_online_map); + cpu_clear(cpu, cpu_callin_map); + + local_flush_tlb_all(); + local_flush_icache_range(0, ~0); + + return 0; +} + +static void bmips_cpu_die(unsigned int cpu) +{ +} + +void __ref play_dead(void) +{ + idle_task_exit(); + + /* flush data cache */ + _dma_cache_wback_inv(0, ~0); + + /* + * Wakeup is on SW0 or SW1; disable everything else + * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux + * IRQ handlers; this clears ST0_IE and returns immediately. + */ + clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); + change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, + IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); + irq_disable_hazard(); + + /* + * wait for SW interrupt from bmips_boot_secondary(), then jump + * back to start_secondary() + */ + __asm__ __volatile__( + " wait\n" + " j bmips_secondary_reentry\n" + : : : "memory"); +} + +#endif /* CONFIG_HOTPLUG_CPU */ + +struct plat_smp_ops bmips_smp_ops = { + .smp_setup = bmips_smp_setup, + .prepare_cpus = bmips_prepare_cpus, + .boot_secondary = bmips_boot_secondary, + .smp_finish = bmips_smp_finish, + .init_secondary = bmips_init_secondary, + .cpus_done = bmips_cpus_done, + .send_ipi_single = bmips_send_ipi_single, + .send_ipi_mask = bmips_send_ipi_mask, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_disable = bmips_cpu_disable, + .cpu_die = bmips_cpu_die, +#endif +}; + +#endif /* CONFIG_SMP */ + +/*********************************************************************** + * BMIPS vector relocation + * This is primarily used for SMP boot, but it is applicable to some + * UP BMIPS systems as well. + ***********************************************************************/ + +static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end) +{ + memcpy((void *)dst, start, end - start); + dma_cache_wback((unsigned long)start, end - start); + local_flush_icache_range(dst, dst + (end - start)); + instruction_hazard(); +} + +static inline void __cpuinit bmips_nmi_handler_setup(void) +{ + bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec, + &bmips_reset_nmi_vec_end); + bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec, + &bmips_smp_int_vec_end); +} + +void __cpuinit bmips_ebase_setup(void) +{ + unsigned long new_ebase = ebase; + void __iomem __maybe_unused *cbr; + + BUG_ON(ebase != CKSEG0); + +#if defined(CONFIG_CPU_BMIPS4350) + /* + * BMIPS4350 cannot relocate the normal vectors, but it + * can relocate the BEV=1 vectors. So CPU1 starts up at + * the relocated BEV=1, IV=0 general exception vector @ + * 0xa000_0380. + * + * set_uncached_handler() is used here because: + * - CPU1 will run this from uncached space + * - None of the cacheflush functions are set up yet + */ + set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, + &bmips_smp_int_vec, 0x80); + __sync(); + return; +#elif defined(CONFIG_CPU_BMIPS4380) + /* + * 0x8000_0000: reset/NMI (initially in kseg1) + * 0x8000_0400: normal vectors + */ + new_ebase = 0x80000400; + cbr = BMIPS_GET_CBR(); + __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0); + __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1); +#elif defined(CONFIG_CPU_BMIPS5000) + /* + * 0x8000_0000: reset/NMI (initially in kseg1) + * 0x8000_1000: normal vectors + */ + new_ebase = 0x80001000; + write_c0_brcm_bootvec(0xa0088008); + write_c0_ebase(new_ebase); + if (max_cpus > 2) + bmips_write_zscm_reg(0xa0, 0xa008a008); +#else + return; +#endif + board_nmi_handler_setup = &bmips_nmi_handler_setup; + ebase = new_ebase; +} + +asmlinkage void __weak plat_wired_tlb_setup(void) +{ + /* + * Called when starting/restarting a secondary CPU. + * Kernel stacks and other important data might only be accessible + * once the wired entries are present. + */ +} From 506d24be55d510c7ff79a0cdcabd00649b979bc9 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:46:14 +0000 Subject: [PATCH 067/119] MIPS: Octeon: Update struct cvmx_bootinfo to v3. Bootloaders can pass version 3 of this structure. Add the new fields so we can support the Device Tree. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2938/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/octeon/cvmx-bootinfo.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h index 4e4c3a8282d6..d9d1668ac779 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h @@ -39,7 +39,7 @@ * versions. */ #define CVMX_BOOTINFO_MAJ_VER 1 -#define CVMX_BOOTINFO_MIN_VER 2 +#define CVMX_BOOTINFO_MIN_VER 3 #if (CVMX_BOOTINFO_MAJ_VER == 1) #define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20 @@ -116,7 +116,13 @@ struct cvmx_bootinfo { */ uint32_t config_flags; #endif - +#if (CVMX_BOOTINFO_MIN_VER >= 3) + /* + * Address of the OF Flattened Device Tree structure + * describing the board. + */ + uint64_t fdt_addr; +#endif }; #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) From 751c9f684963d2a066a79d8022c0e79e1159291b Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:46:49 +0000 Subject: [PATCH 068/119] MIPS: Oceton: Update model detection code for new chips. Several newer chips were not covered, update the code to detect them. This necessitates updating cvmx-mio-defs.h as well, because it has new and required definitions. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2939/ Signed-off-by: Ralf Baechle --- .../cavium-octeon/executive/octeon-model.c | 119 +- arch/mips/include/asm/octeon/cvmx-mio-defs.h | 1037 ++++++++++++++++- arch/mips/include/asm/octeon/octeon-model.h | 215 ++-- 3 files changed, 1181 insertions(+), 190 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c index c8d35684504e..f4c1b36fdf65 100644 --- a/arch/mips/cavium-octeon/executive/octeon-model.c +++ b/arch/mips/cavium-octeon/executive/octeon-model.c @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -25,10 +25,6 @@ * Contact Cavium Networks for more information ***********************license end**************************************/ -/* - * File defining functions for working with different Octeon - * models. - */ #include /** @@ -69,11 +65,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) char fuse_model[10]; uint32_t fuse_data = 0; - fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); + fus3.u64 = 0; + if (!OCTEON_IS_MODEL(OCTEON_CN6XXX)) + fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); - - num_cores = cvmx_octeon_num_cores(); + num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE)); /* Make sure the non existent devices look disabled */ switch ((chip_id >> 8) & 0xff) { @@ -108,7 +105,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) * Assume pass number is encoded using <5:3><2:0>. Exceptions * will be fixed later. */ - sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7); + sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7); /* * Use the number of cores to determine the last 2 digits of @@ -116,6 +113,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) * later. */ switch (num_cores) { + case 32: + core_model = "80"; + break; + case 24: + core_model = "70"; + break; case 16: core_model = "60"; break; @@ -246,8 +249,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) break; case 3: /* CN58XX */ family = "58"; - /* Special case. 4 core, no crypto */ - if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto) + /* Special case. 4 core, half cache (CP with half cache) */ + if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2)) core_model = "29"; /* Pass 1 uses different encodings for pass numbers */ @@ -285,6 +288,9 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) suffix = "NSP"; if (fus_dat3.s.nozip) suffix = "SCP"; + + if (fus_dat3.s.bar2_en) + suffix = "NSPB2"; } if (fus3.cn56xx.crip_1024k) family = "54"; @@ -301,6 +307,60 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) else family = "52"; break; + case 0x93: /* CN61XX */ + family = "61"; + if (fus_dat2.cn61xx.nocrypto && fus_dat2.cn61xx.dorm_crypto) + suffix = "AP"; + if (fus_dat2.cn61xx.nocrypto) + suffix = "CP"; + else if (fus_dat2.cn61xx.dorm_crypto) + suffix = "DAP"; + else if (fus_dat3.cn61xx.nozip) + suffix = "SCP"; + break; + case 0x90: /* CN63XX */ + family = "63"; + if (fus_dat3.s.l2c_crip == 2) + family = "62"; + if (num_cores == 6) /* Other core counts match generic */ + core_model = "35"; + if (fus_dat2.cn63xx.nocrypto) + suffix = "CP"; + else if (fus_dat2.cn63xx.dorm_crypto) + suffix = "DAP"; + else if (fus_dat3.cn63xx.nozip) + suffix = "SCP"; + else + suffix = "AAP"; + break; + case 0x92: /* CN66XX */ + family = "66"; + if (num_cores == 6) /* Other core counts match generic */ + core_model = "35"; + if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto) + suffix = "AP"; + if (fus_dat2.cn66xx.nocrypto) + suffix = "CP"; + else if (fus_dat2.cn66xx.dorm_crypto) + suffix = "DAP"; + else if (fus_dat3.cn66xx.nozip) + suffix = "SCP"; + else + suffix = "AAP"; + break; + case 0x91: /* CN68XX */ + family = "68"; + if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip) + suffix = "CP"; + else if (fus_dat2.cn68xx.dorm_crypto) + suffix = "DAP"; + else if (fus_dat3.cn68xx.nozip) + suffix = "SCP"; + else if (fus_dat2.cn68xx.nocrypto) + suffix = "SP"; + else + suffix = "AAP"; + break; default: family = "XX"; core_model = "XX"; @@ -310,49 +370,40 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) } clock_mhz = octeon_get_clock_rate() / 1000000; - if (family[0] != '3') { + int fuse_base = 384 / 8; + if (family[0] == '6') + fuse_base = 832 / 8; + /* Check for model in fuses, overrides normal decode */ /* This is _not_ valid for Octeon CN3XXX models */ - fuse_data |= cvmx_fuse_read_byte(51); + fuse_data |= cvmx_fuse_read_byte(fuse_base + 3); fuse_data = fuse_data << 8; - fuse_data |= cvmx_fuse_read_byte(50); + fuse_data |= cvmx_fuse_read_byte(fuse_base + 2); fuse_data = fuse_data << 8; - fuse_data |= cvmx_fuse_read_byte(49); + fuse_data |= cvmx_fuse_read_byte(fuse_base + 1); fuse_data = fuse_data << 8; - fuse_data |= cvmx_fuse_read_byte(48); + fuse_data |= cvmx_fuse_read_byte(fuse_base); if (fuse_data & 0x7ffff) { int model = fuse_data & 0x3fff; int suffix = (fuse_data >> 14) & 0x1f; if (suffix && model) { - /* - * Have both number and suffix in - * fuses, so both - */ - sprintf(fuse_model, "%d%c", - model, 'A' + suffix - 1); + /* Have both number and suffix in fuses, so both */ + sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1); core_model = ""; family = fuse_model; } else if (suffix && !model) { - /* - * Only have suffix, so add suffix to - * 'normal' model number. - */ - sprintf(fuse_model, "%s%c", core_model, - 'A' + suffix - 1); + /* Only have suffix, so add suffix to 'normal' model number */ + sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1); core_model = fuse_model; } else { - /* - * Don't have suffix, so just use - * model from fuses. - */ + /* Don't have suffix, so just use model from fuses */ sprintf(fuse_model, "%d", model); core_model = ""; family = fuse_model; } } } - sprintf(buffer, "CN%s%sp%s-%d-%s", - family, core_model, pass, clock_mhz, suffix); + sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix); return buffer; } diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h index 52b14a333ad4..b1774126736d 100644 --- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h @@ -43,6 +43,22 @@ #define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8) #define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8) #define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull)) +#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull)) +#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull)) +#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull)) +#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull)) +#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull)) +#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull)) +#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull)) +#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8) +#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull)) +#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull)) +#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull)) +#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull)) +#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull)) +#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull)) +#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull)) +#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull)) #define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8) #define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull)) #define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull)) @@ -60,6 +76,7 @@ #define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull)) #define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull)) #define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull)) +#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull)) #define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull)) #define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull)) #define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull)) @@ -68,14 +85,25 @@ #define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull)) #define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull)) #define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull)) +#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull)) +#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull)) +#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull)) +#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull)) #define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull)) #define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull)) #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) +#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull)) +#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull)) +#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull)) +#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull)) #define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull)) +#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8) #define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull)) #define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull)) +#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull)) +#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8) #define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8) #define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull)) #define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull)) @@ -183,11 +211,21 @@ union cvmx_mio_boot_bist_stat { struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; + struct cvmx_mio_boot_bist_stat_cn61xx { + uint64_t reserved_12_63:52; + uint64_t stat:12; + } cn61xx; struct cvmx_mio_boot_bist_stat_cn63xx { uint64_t reserved_9_63:55; uint64_t stat:9; } cn63xx; struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; + struct cvmx_mio_boot_bist_stat_cn66xx { + uint64_t reserved_10_63:54; + uint64_t stat:10; + } cn66xx; + struct cvmx_mio_boot_bist_stat_cn66xx cn68xx; + struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1; }; union cvmx_mio_boot_comp { @@ -204,12 +242,16 @@ union cvmx_mio_boot_comp { struct cvmx_mio_boot_comp_cn50xx cn52xxp1; struct cvmx_mio_boot_comp_cn50xx cn56xx; struct cvmx_mio_boot_comp_cn50xx cn56xxp1; - struct cvmx_mio_boot_comp_cn63xx { + struct cvmx_mio_boot_comp_cn61xx { uint64_t reserved_12_63:52; uint64_t pctl:6; uint64_t nctl:6; - } cn63xx; - struct cvmx_mio_boot_comp_cn63xx cn63xxp1; + } cn61xx; + struct cvmx_mio_boot_comp_cn61xx cn63xx; + struct cvmx_mio_boot_comp_cn61xx cn63xxp1; + struct cvmx_mio_boot_comp_cn61xx cn66xx; + struct cvmx_mio_boot_comp_cn61xx cn68xx; + struct cvmx_mio_boot_comp_cn61xx cn68xxp1; }; union cvmx_mio_boot_dma_cfgx { @@ -230,8 +272,12 @@ union cvmx_mio_boot_dma_cfgx { struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; struct cvmx_mio_boot_dma_cfgx_s cn56xx; struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; + struct cvmx_mio_boot_dma_cfgx_s cn61xx; struct cvmx_mio_boot_dma_cfgx_s cn63xx; struct cvmx_mio_boot_dma_cfgx_s cn63xxp1; + struct cvmx_mio_boot_dma_cfgx_s cn66xx; + struct cvmx_mio_boot_dma_cfgx_s cn68xx; + struct cvmx_mio_boot_dma_cfgx_s cn68xxp1; }; union cvmx_mio_boot_dma_intx { @@ -245,8 +291,12 @@ union cvmx_mio_boot_dma_intx { struct cvmx_mio_boot_dma_intx_s cn52xxp1; struct cvmx_mio_boot_dma_intx_s cn56xx; struct cvmx_mio_boot_dma_intx_s cn56xxp1; + struct cvmx_mio_boot_dma_intx_s cn61xx; struct cvmx_mio_boot_dma_intx_s cn63xx; struct cvmx_mio_boot_dma_intx_s cn63xxp1; + struct cvmx_mio_boot_dma_intx_s cn66xx; + struct cvmx_mio_boot_dma_intx_s cn68xx; + struct cvmx_mio_boot_dma_intx_s cn68xxp1; }; union cvmx_mio_boot_dma_int_enx { @@ -260,8 +310,12 @@ union cvmx_mio_boot_dma_int_enx { struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; struct cvmx_mio_boot_dma_int_enx_s cn56xx; struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; + struct cvmx_mio_boot_dma_int_enx_s cn61xx; struct cvmx_mio_boot_dma_int_enx_s cn63xx; struct cvmx_mio_boot_dma_int_enx_s cn63xxp1; + struct cvmx_mio_boot_dma_int_enx_s cn66xx; + struct cvmx_mio_boot_dma_int_enx_s cn68xx; + struct cvmx_mio_boot_dma_int_enx_s cn68xxp1; }; union cvmx_mio_boot_dma_timx { @@ -287,8 +341,12 @@ union cvmx_mio_boot_dma_timx { struct cvmx_mio_boot_dma_timx_s cn52xxp1; struct cvmx_mio_boot_dma_timx_s cn56xx; struct cvmx_mio_boot_dma_timx_s cn56xxp1; + struct cvmx_mio_boot_dma_timx_s cn61xx; struct cvmx_mio_boot_dma_timx_s cn63xx; struct cvmx_mio_boot_dma_timx_s cn63xxp1; + struct cvmx_mio_boot_dma_timx_s cn66xx; + struct cvmx_mio_boot_dma_timx_s cn68xx; + struct cvmx_mio_boot_dma_timx_s cn68xxp1; }; union cvmx_mio_boot_err { @@ -309,8 +367,12 @@ union cvmx_mio_boot_err { struct cvmx_mio_boot_err_s cn56xxp1; struct cvmx_mio_boot_err_s cn58xx; struct cvmx_mio_boot_err_s cn58xxp1; + struct cvmx_mio_boot_err_s cn61xx; struct cvmx_mio_boot_err_s cn63xx; struct cvmx_mio_boot_err_s cn63xxp1; + struct cvmx_mio_boot_err_s cn66xx; + struct cvmx_mio_boot_err_s cn68xx; + struct cvmx_mio_boot_err_s cn68xxp1; }; union cvmx_mio_boot_int { @@ -331,8 +393,12 @@ union cvmx_mio_boot_int { struct cvmx_mio_boot_int_s cn56xxp1; struct cvmx_mio_boot_int_s cn58xx; struct cvmx_mio_boot_int_s cn58xxp1; + struct cvmx_mio_boot_int_s cn61xx; struct cvmx_mio_boot_int_s cn63xx; struct cvmx_mio_boot_int_s cn63xxp1; + struct cvmx_mio_boot_int_s cn66xx; + struct cvmx_mio_boot_int_s cn68xx; + struct cvmx_mio_boot_int_s cn68xxp1; }; union cvmx_mio_boot_loc_adr { @@ -353,8 +419,12 @@ union cvmx_mio_boot_loc_adr { struct cvmx_mio_boot_loc_adr_s cn56xxp1; struct cvmx_mio_boot_loc_adr_s cn58xx; struct cvmx_mio_boot_loc_adr_s cn58xxp1; + struct cvmx_mio_boot_loc_adr_s cn61xx; struct cvmx_mio_boot_loc_adr_s cn63xx; struct cvmx_mio_boot_loc_adr_s cn63xxp1; + struct cvmx_mio_boot_loc_adr_s cn66xx; + struct cvmx_mio_boot_loc_adr_s cn68xx; + struct cvmx_mio_boot_loc_adr_s cn68xxp1; }; union cvmx_mio_boot_loc_cfgx { @@ -377,8 +447,12 @@ union cvmx_mio_boot_loc_cfgx { struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; struct cvmx_mio_boot_loc_cfgx_s cn58xx; struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; + struct cvmx_mio_boot_loc_cfgx_s cn61xx; struct cvmx_mio_boot_loc_cfgx_s cn63xx; struct cvmx_mio_boot_loc_cfgx_s cn63xxp1; + struct cvmx_mio_boot_loc_cfgx_s cn66xx; + struct cvmx_mio_boot_loc_cfgx_s cn68xx; + struct cvmx_mio_boot_loc_cfgx_s cn68xxp1; }; union cvmx_mio_boot_loc_dat { @@ -397,14 +471,19 @@ union cvmx_mio_boot_loc_dat { struct cvmx_mio_boot_loc_dat_s cn56xxp1; struct cvmx_mio_boot_loc_dat_s cn58xx; struct cvmx_mio_boot_loc_dat_s cn58xxp1; + struct cvmx_mio_boot_loc_dat_s cn61xx; struct cvmx_mio_boot_loc_dat_s cn63xx; struct cvmx_mio_boot_loc_dat_s cn63xxp1; + struct cvmx_mio_boot_loc_dat_s cn66xx; + struct cvmx_mio_boot_loc_dat_s cn68xx; + struct cvmx_mio_boot_loc_dat_s cn68xxp1; }; union cvmx_mio_boot_pin_defs { uint64_t u64; struct cvmx_mio_boot_pin_defs_s { - uint64_t reserved_16_63:48; + uint64_t reserved_32_63:32; + uint64_t user1:16; uint64_t ale:1; uint64_t width:1; uint64_t dmack_p2:1; @@ -412,7 +491,7 @@ union cvmx_mio_boot_pin_defs { uint64_t dmack_p0:1; uint64_t term:2; uint64_t nand:1; - uint64_t reserved_0_7:8; + uint64_t user0:8; } s; struct cvmx_mio_boot_pin_defs_cn52xx { uint64_t reserved_16_63:48; @@ -435,8 +514,23 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t reserved_0_8:9; } cn56xx; + struct cvmx_mio_boot_pin_defs_cn61xx { + uint64_t reserved_32_63:32; + uint64_t user1:16; + uint64_t ale:1; + uint64_t width:1; + uint64_t reserved_13_13:1; + uint64_t dmack_p1:1; + uint64_t dmack_p0:1; + uint64_t term:2; + uint64_t nand:1; + uint64_t user0:8; + } cn61xx; struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; + struct cvmx_mio_boot_pin_defs_cn52xx cn66xx; + struct cvmx_mio_boot_pin_defs_cn52xx cn68xx; + struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1; }; union cvmx_mio_boot_reg_cfgx { @@ -498,8 +592,12 @@ union cvmx_mio_boot_reg_cfgx { struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; + struct cvmx_mio_boot_reg_cfgx_s cn61xx; struct cvmx_mio_boot_reg_cfgx_s cn63xx; struct cvmx_mio_boot_reg_cfgx_s cn63xxp1; + struct cvmx_mio_boot_reg_cfgx_s cn66xx; + struct cvmx_mio_boot_reg_cfgx_s cn68xx; + struct cvmx_mio_boot_reg_cfgx_s cn68xxp1; }; union cvmx_mio_boot_reg_timx { @@ -544,8 +642,12 @@ union cvmx_mio_boot_reg_timx { struct cvmx_mio_boot_reg_timx_s cn56xxp1; struct cvmx_mio_boot_reg_timx_s cn58xx; struct cvmx_mio_boot_reg_timx_s cn58xxp1; + struct cvmx_mio_boot_reg_timx_s cn61xx; struct cvmx_mio_boot_reg_timx_s cn63xx; struct cvmx_mio_boot_reg_timx_s cn63xxp1; + struct cvmx_mio_boot_reg_timx_s cn66xx; + struct cvmx_mio_boot_reg_timx_s cn68xx; + struct cvmx_mio_boot_reg_timx_s cn68xxp1; }; union cvmx_mio_boot_thr { @@ -574,8 +676,231 @@ union cvmx_mio_boot_thr { struct cvmx_mio_boot_thr_s cn56xxp1; struct cvmx_mio_boot_thr_cn30xx cn58xx; struct cvmx_mio_boot_thr_cn30xx cn58xxp1; + struct cvmx_mio_boot_thr_s cn61xx; struct cvmx_mio_boot_thr_s cn63xx; struct cvmx_mio_boot_thr_s cn63xxp1; + struct cvmx_mio_boot_thr_s cn66xx; + struct cvmx_mio_boot_thr_s cn68xx; + struct cvmx_mio_boot_thr_s cn68xxp1; +}; + +union cvmx_mio_emm_buf_dat { + uint64_t u64; + struct cvmx_mio_emm_buf_dat_s { + uint64_t dat:64; + } s; + struct cvmx_mio_emm_buf_dat_s cn61xx; +}; + +union cvmx_mio_emm_buf_idx { + uint64_t u64; + struct cvmx_mio_emm_buf_idx_s { + uint64_t reserved_17_63:47; + uint64_t inc:1; + uint64_t reserved_7_15:9; + uint64_t buf_num:1; + uint64_t offset:6; + } s; + struct cvmx_mio_emm_buf_idx_s cn61xx; +}; + +union cvmx_mio_emm_cfg { + uint64_t u64; + struct cvmx_mio_emm_cfg_s { + uint64_t reserved_17_63:47; + uint64_t boot_fail:1; + uint64_t reserved_4_15:12; + uint64_t bus_ena:4; + } s; + struct cvmx_mio_emm_cfg_s cn61xx; +}; + +union cvmx_mio_emm_cmd { + uint64_t u64; + struct cvmx_mio_emm_cmd_s { + uint64_t reserved_62_63:2; + uint64_t bus_id:2; + uint64_t cmd_val:1; + uint64_t reserved_56_58:3; + uint64_t dbuf:1; + uint64_t offset:6; + uint64_t reserved_43_48:6; + uint64_t ctype_xor:2; + uint64_t rtype_xor:3; + uint64_t cmd_idx:6; + uint64_t arg:32; + } s; + struct cvmx_mio_emm_cmd_s cn61xx; +}; + +union cvmx_mio_emm_dma { + uint64_t u64; + struct cvmx_mio_emm_dma_s { + uint64_t reserved_62_63:2; + uint64_t bus_id:2; + uint64_t dma_val:1; + uint64_t sector:1; + uint64_t dat_null:1; + uint64_t thres:6; + uint64_t rel_wr:1; + uint64_t rw:1; + uint64_t multi:1; + uint64_t block_cnt:16; + uint64_t card_addr:32; + } s; + struct cvmx_mio_emm_dma_s cn61xx; +}; + +union cvmx_mio_emm_int { + uint64_t u64; + struct cvmx_mio_emm_int_s { + uint64_t reserved_7_63:57; + uint64_t switch_err:1; + uint64_t switch_done:1; + uint64_t dma_err:1; + uint64_t cmd_err:1; + uint64_t dma_done:1; + uint64_t cmd_done:1; + uint64_t buf_done:1; + } s; + struct cvmx_mio_emm_int_s cn61xx; +}; + +union cvmx_mio_emm_int_en { + uint64_t u64; + struct cvmx_mio_emm_int_en_s { + uint64_t reserved_7_63:57; + uint64_t switch_err:1; + uint64_t switch_done:1; + uint64_t dma_err:1; + uint64_t cmd_err:1; + uint64_t dma_done:1; + uint64_t cmd_done:1; + uint64_t buf_done:1; + } s; + struct cvmx_mio_emm_int_en_s cn61xx; +}; + +union cvmx_mio_emm_modex { + uint64_t u64; + struct cvmx_mio_emm_modex_s { + uint64_t reserved_49_63:15; + uint64_t hs_timing:1; + uint64_t reserved_43_47:5; + uint64_t bus_width:3; + uint64_t reserved_36_39:4; + uint64_t power_class:4; + uint64_t clk_hi:16; + uint64_t clk_lo:16; + } s; + struct cvmx_mio_emm_modex_s cn61xx; +}; + +union cvmx_mio_emm_rca { + uint64_t u64; + struct cvmx_mio_emm_rca_s { + uint64_t reserved_16_63:48; + uint64_t card_rca:16; + } s; + struct cvmx_mio_emm_rca_s cn61xx; +}; + +union cvmx_mio_emm_rsp_hi { + uint64_t u64; + struct cvmx_mio_emm_rsp_hi_s { + uint64_t dat:64; + } s; + struct cvmx_mio_emm_rsp_hi_s cn61xx; +}; + +union cvmx_mio_emm_rsp_lo { + uint64_t u64; + struct cvmx_mio_emm_rsp_lo_s { + uint64_t dat:64; + } s; + struct cvmx_mio_emm_rsp_lo_s cn61xx; +}; + +union cvmx_mio_emm_rsp_sts { + uint64_t u64; + struct cvmx_mio_emm_rsp_sts_s { + uint64_t reserved_62_63:2; + uint64_t bus_id:2; + uint64_t cmd_val:1; + uint64_t switch_val:1; + uint64_t dma_val:1; + uint64_t dma_pend:1; + uint64_t reserved_29_55:27; + uint64_t dbuf_err:1; + uint64_t reserved_24_27:4; + uint64_t dbuf:1; + uint64_t blk_timeout:1; + uint64_t blk_crc_err:1; + uint64_t rsp_busybit:1; + uint64_t stp_timeout:1; + uint64_t stp_crc_err:1; + uint64_t stp_bad_sts:1; + uint64_t stp_val:1; + uint64_t rsp_timeout:1; + uint64_t rsp_crc_err:1; + uint64_t rsp_bad_sts:1; + uint64_t rsp_val:1; + uint64_t rsp_type:3; + uint64_t cmd_type:2; + uint64_t cmd_idx:6; + uint64_t cmd_done:1; + } s; + struct cvmx_mio_emm_rsp_sts_s cn61xx; +}; + +union cvmx_mio_emm_sample { + uint64_t u64; + struct cvmx_mio_emm_sample_s { + uint64_t reserved_26_63:38; + uint64_t cmd_cnt:10; + uint64_t reserved_10_15:6; + uint64_t dat_cnt:10; + } s; + struct cvmx_mio_emm_sample_s cn61xx; +}; + +union cvmx_mio_emm_sts_mask { + uint64_t u64; + struct cvmx_mio_emm_sts_mask_s { + uint64_t reserved_32_63:32; + uint64_t sts_msk:32; + } s; + struct cvmx_mio_emm_sts_mask_s cn61xx; +}; + +union cvmx_mio_emm_switch { + uint64_t u64; + struct cvmx_mio_emm_switch_s { + uint64_t reserved_62_63:2; + uint64_t bus_id:2; + uint64_t switch_exe:1; + uint64_t switch_err0:1; + uint64_t switch_err1:1; + uint64_t switch_err2:1; + uint64_t reserved_49_55:7; + uint64_t hs_timing:1; + uint64_t reserved_43_47:5; + uint64_t bus_width:3; + uint64_t reserved_36_39:4; + uint64_t power_class:4; + uint64_t clk_hi:16; + uint64_t clk_lo:16; + } s; + struct cvmx_mio_emm_switch_s cn61xx; +}; + +union cvmx_mio_emm_wdog { + uint64_t u64; + struct cvmx_mio_emm_wdog_s { + uint64_t reserved_26_63:38; + uint64_t clk_cnt:26; + } s; + struct cvmx_mio_emm_wdog_s cn61xx; }; union cvmx_mio_fus_bnk_datx { @@ -590,8 +915,12 @@ union cvmx_mio_fus_bnk_datx { struct cvmx_mio_fus_bnk_datx_s cn56xxp1; struct cvmx_mio_fus_bnk_datx_s cn58xx; struct cvmx_mio_fus_bnk_datx_s cn58xxp1; + struct cvmx_mio_fus_bnk_datx_s cn61xx; struct cvmx_mio_fus_bnk_datx_s cn63xx; struct cvmx_mio_fus_bnk_datx_s cn63xxp1; + struct cvmx_mio_fus_bnk_datx_s cn66xx; + struct cvmx_mio_fus_bnk_datx_s cn68xx; + struct cvmx_mio_fus_bnk_datx_s cn68xxp1; }; union cvmx_mio_fus_dat0 { @@ -611,8 +940,12 @@ union cvmx_mio_fus_dat0 { struct cvmx_mio_fus_dat0_s cn56xxp1; struct cvmx_mio_fus_dat0_s cn58xx; struct cvmx_mio_fus_dat0_s cn58xxp1; + struct cvmx_mio_fus_dat0_s cn61xx; struct cvmx_mio_fus_dat0_s cn63xx; struct cvmx_mio_fus_dat0_s cn63xxp1; + struct cvmx_mio_fus_dat0_s cn66xx; + struct cvmx_mio_fus_dat0_s cn68xx; + struct cvmx_mio_fus_dat0_s cn68xxp1; }; union cvmx_mio_fus_dat1 { @@ -632,14 +965,21 @@ union cvmx_mio_fus_dat1 { struct cvmx_mio_fus_dat1_s cn56xxp1; struct cvmx_mio_fus_dat1_s cn58xx; struct cvmx_mio_fus_dat1_s cn58xxp1; + struct cvmx_mio_fus_dat1_s cn61xx; struct cvmx_mio_fus_dat1_s cn63xx; struct cvmx_mio_fus_dat1_s cn63xxp1; + struct cvmx_mio_fus_dat1_s cn66xx; + struct cvmx_mio_fus_dat1_s cn68xx; + struct cvmx_mio_fus_dat1_s cn68xxp1; }; union cvmx_mio_fus_dat2 { uint64_t u64; struct cvmx_mio_fus_dat2_s { - uint64_t reserved_35_63:29; + uint64_t reserved_48_63:16; + uint64_t fus118:1; + uint64_t rom_info:10; + uint64_t power_limit:2; uint64_t dorm_crypto:1; uint64_t fus318:1; uint64_t raid_en:1; @@ -747,6 +1087,23 @@ union cvmx_mio_fus_dat2 { uint64_t pp_dis:16; } cn58xx; struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; + struct cvmx_mio_fus_dat2_cn61xx { + uint64_t reserved_48_63:16; + uint64_t fus118:1; + uint64_t rom_info:10; + uint64_t power_limit:2; + uint64_t dorm_crypto:1; + uint64_t fus318:1; + uint64_t raid_en:1; + uint64_t reserved_29_31:3; + uint64_t nodfa_cp2:1; + uint64_t nomul:1; + uint64_t nocrypto:1; + uint64_t reserved_24_25:2; + uint64_t chip_id:8; + uint64_t reserved_4_15:12; + uint64_t pp_dis:4; + } cn61xx; struct cvmx_mio_fus_dat2_cn63xx { uint64_t reserved_35_63:29; uint64_t dorm_crypto:1; @@ -762,6 +1119,38 @@ union cvmx_mio_fus_dat2 { uint64_t pp_dis:6; } cn63xx; struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; + struct cvmx_mio_fus_dat2_cn66xx { + uint64_t reserved_48_63:16; + uint64_t fus118:1; + uint64_t rom_info:10; + uint64_t power_limit:2; + uint64_t dorm_crypto:1; + uint64_t fus318:1; + uint64_t raid_en:1; + uint64_t reserved_29_31:3; + uint64_t nodfa_cp2:1; + uint64_t nomul:1; + uint64_t nocrypto:1; + uint64_t reserved_24_25:2; + uint64_t chip_id:8; + uint64_t reserved_10_15:6; + uint64_t pp_dis:10; + } cn66xx; + struct cvmx_mio_fus_dat2_cn68xx { + uint64_t reserved_37_63:27; + uint64_t power_limit:2; + uint64_t dorm_crypto:1; + uint64_t fus318:1; + uint64_t raid_en:1; + uint64_t reserved_29_31:3; + uint64_t nodfa_cp2:1; + uint64_t nomul:1; + uint64_t nocrypto:1; + uint64_t reserved_24_25:2; + uint64_t chip_id:8; + uint64_t reserved_0_15:16; + } cn68xx; + struct cvmx_mio_fus_dat2_cn68xx cn68xxp1; }; union cvmx_mio_fus_dat3 { @@ -834,7 +1223,7 @@ union cvmx_mio_fus_dat3 { struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; struct cvmx_mio_fus_dat3_cn38xx cn58xx; struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; - struct cvmx_mio_fus_dat3_cn63xx { + struct cvmx_mio_fus_dat3_cn61xx { uint64_t reserved_58_63:6; uint64_t pll_ctl:10; uint64_t dfa_info_dte:3; @@ -853,8 +1242,12 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t reserved_0_23:24; - } cn63xx; - struct cvmx_mio_fus_dat3_cn63xx cn63xxp1; + } cn61xx; + struct cvmx_mio_fus_dat3_cn61xx cn63xx; + struct cvmx_mio_fus_dat3_cn61xx cn63xxp1; + struct cvmx_mio_fus_dat3_cn61xx cn66xx; + struct cvmx_mio_fus_dat3_cn61xx cn68xx; + struct cvmx_mio_fus_dat3_cn61xx cn68xxp1; }; union cvmx_mio_fus_ema { @@ -875,8 +1268,12 @@ union cvmx_mio_fus_ema { uint64_t ema:2; } cn58xx; struct cvmx_mio_fus_ema_cn58xx cn58xxp1; + struct cvmx_mio_fus_ema_s cn61xx; struct cvmx_mio_fus_ema_s cn63xx; struct cvmx_mio_fus_ema_s cn63xxp1; + struct cvmx_mio_fus_ema_s cn66xx; + struct cvmx_mio_fus_ema_s cn68xx; + struct cvmx_mio_fus_ema_s cn68xxp1; }; union cvmx_mio_fus_pdf { @@ -890,14 +1287,21 @@ union cvmx_mio_fus_pdf { struct cvmx_mio_fus_pdf_s cn56xx; struct cvmx_mio_fus_pdf_s cn56xxp1; struct cvmx_mio_fus_pdf_s cn58xx; + struct cvmx_mio_fus_pdf_s cn61xx; struct cvmx_mio_fus_pdf_s cn63xx; struct cvmx_mio_fus_pdf_s cn63xxp1; + struct cvmx_mio_fus_pdf_s cn66xx; + struct cvmx_mio_fus_pdf_s cn68xx; + struct cvmx_mio_fus_pdf_s cn68xxp1; }; union cvmx_mio_fus_pll { uint64_t u64; struct cvmx_mio_fus_pll_s { - uint64_t reserved_8_63:56; + uint64_t reserved_48_63:16; + uint64_t rclk_align_r:8; + uint64_t rclk_align_l:8; + uint64_t reserved_8_31:24; uint64_t c_cout_rst:1; uint64_t c_cout_sel:2; uint64_t pnr_cout_rst:1; @@ -916,8 +1320,20 @@ union cvmx_mio_fus_pll { struct cvmx_mio_fus_pll_cn50xx cn56xxp1; struct cvmx_mio_fus_pll_cn50xx cn58xx; struct cvmx_mio_fus_pll_cn50xx cn58xxp1; - struct cvmx_mio_fus_pll_s cn63xx; - struct cvmx_mio_fus_pll_s cn63xxp1; + struct cvmx_mio_fus_pll_cn61xx { + uint64_t reserved_8_63:56; + uint64_t c_cout_rst:1; + uint64_t c_cout_sel:2; + uint64_t pnr_cout_rst:1; + uint64_t pnr_cout_sel:2; + uint64_t rfslip:1; + uint64_t fbslip:1; + } cn61xx; + struct cvmx_mio_fus_pll_cn61xx cn63xx; + struct cvmx_mio_fus_pll_cn61xx cn63xxp1; + struct cvmx_mio_fus_pll_cn61xx cn66xx; + struct cvmx_mio_fus_pll_s cn68xx; + struct cvmx_mio_fus_pll_s cn68xxp1; }; union cvmx_mio_fus_prog { @@ -941,8 +1357,12 @@ union cvmx_mio_fus_prog { struct cvmx_mio_fus_prog_cn30xx cn56xxp1; struct cvmx_mio_fus_prog_cn30xx cn58xx; struct cvmx_mio_fus_prog_cn30xx cn58xxp1; + struct cvmx_mio_fus_prog_s cn61xx; struct cvmx_mio_fus_prog_s cn63xx; struct cvmx_mio_fus_prog_s cn63xxp1; + struct cvmx_mio_fus_prog_s cn66xx; + struct cvmx_mio_fus_prog_s cn68xx; + struct cvmx_mio_fus_prog_s cn68xxp1; }; union cvmx_mio_fus_prog_times { @@ -969,7 +1389,7 @@ union cvmx_mio_fus_prog_times { struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1; struct cvmx_mio_fus_prog_times_cn50xx cn58xx; struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; - struct cvmx_mio_fus_prog_times_cn63xx { + struct cvmx_mio_fus_prog_times_cn61xx { uint64_t reserved_35_63:29; uint64_t vgate_pin:1; uint64_t fsrc_pin:1; @@ -978,8 +1398,12 @@ union cvmx_mio_fus_prog_times { uint64_t sclk_lo:4; uint64_t sclk_hi:15; uint64_t setup:6; - } cn63xx; - struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1; + } cn61xx; + struct cvmx_mio_fus_prog_times_cn61xx cn63xx; + struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1; + struct cvmx_mio_fus_prog_times_cn61xx cn66xx; + struct cvmx_mio_fus_prog_times_cn61xx cn68xx; + struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1; }; union cvmx_mio_fus_rcmd { @@ -1013,8 +1437,12 @@ union cvmx_mio_fus_rcmd { struct cvmx_mio_fus_rcmd_s cn56xxp1; struct cvmx_mio_fus_rcmd_cn30xx cn58xx; struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; + struct cvmx_mio_fus_rcmd_s cn61xx; struct cvmx_mio_fus_rcmd_s cn63xx; struct cvmx_mio_fus_rcmd_s cn63xxp1; + struct cvmx_mio_fus_rcmd_s cn66xx; + struct cvmx_mio_fus_rcmd_s cn68xx; + struct cvmx_mio_fus_rcmd_s cn68xxp1; }; union cvmx_mio_fus_read_times { @@ -1027,8 +1455,12 @@ union cvmx_mio_fus_read_times { uint64_t sdh:4; uint64_t setup:10; } s; + struct cvmx_mio_fus_read_times_s cn61xx; struct cvmx_mio_fus_read_times_s cn63xx; struct cvmx_mio_fus_read_times_s cn63xxp1; + struct cvmx_mio_fus_read_times_s cn66xx; + struct cvmx_mio_fus_read_times_s cn68xx; + struct cvmx_mio_fus_read_times_s cn68xxp1; }; union cvmx_mio_fus_repair_res0 { @@ -1040,8 +1472,12 @@ union cvmx_mio_fus_repair_res0 { uint64_t repair1:18; uint64_t repair0:18; } s; + struct cvmx_mio_fus_repair_res0_s cn61xx; struct cvmx_mio_fus_repair_res0_s cn63xx; struct cvmx_mio_fus_repair_res0_s cn63xxp1; + struct cvmx_mio_fus_repair_res0_s cn66xx; + struct cvmx_mio_fus_repair_res0_s cn68xx; + struct cvmx_mio_fus_repair_res0_s cn68xxp1; }; union cvmx_mio_fus_repair_res1 { @@ -1052,8 +1488,12 @@ union cvmx_mio_fus_repair_res1 { uint64_t repair4:18; uint64_t repair3:18; } s; + struct cvmx_mio_fus_repair_res1_s cn61xx; struct cvmx_mio_fus_repair_res1_s cn63xx; struct cvmx_mio_fus_repair_res1_s cn63xxp1; + struct cvmx_mio_fus_repair_res1_s cn66xx; + struct cvmx_mio_fus_repair_res1_s cn68xx; + struct cvmx_mio_fus_repair_res1_s cn68xxp1; }; union cvmx_mio_fus_repair_res2 { @@ -1062,8 +1502,12 @@ union cvmx_mio_fus_repair_res2 { uint64_t reserved_18_63:46; uint64_t repair6:18; } s; + struct cvmx_mio_fus_repair_res2_s cn61xx; struct cvmx_mio_fus_repair_res2_s cn63xx; struct cvmx_mio_fus_repair_res2_s cn63xxp1; + struct cvmx_mio_fus_repair_res2_s cn66xx; + struct cvmx_mio_fus_repair_res2_s cn68xx; + struct cvmx_mio_fus_repair_res2_s cn68xxp1; }; union cvmx_mio_fus_spr_repair_res { @@ -1084,8 +1528,12 @@ union cvmx_mio_fus_spr_repair_res { struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; struct cvmx_mio_fus_spr_repair_res_s cn58xx; struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; + struct cvmx_mio_fus_spr_repair_res_s cn61xx; struct cvmx_mio_fus_spr_repair_res_s cn63xx; struct cvmx_mio_fus_spr_repair_res_s cn63xxp1; + struct cvmx_mio_fus_spr_repair_res_s cn66xx; + struct cvmx_mio_fus_spr_repair_res_s cn68xx; + struct cvmx_mio_fus_spr_repair_res_s cn68xxp1; }; union cvmx_mio_fus_spr_repair_sum { @@ -1104,8 +1552,22 @@ union cvmx_mio_fus_spr_repair_sum { struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; struct cvmx_mio_fus_spr_repair_sum_s cn58xx; struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; + struct cvmx_mio_fus_spr_repair_sum_s cn61xx; struct cvmx_mio_fus_spr_repair_sum_s cn63xx; struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1; + struct cvmx_mio_fus_spr_repair_sum_s cn66xx; + struct cvmx_mio_fus_spr_repair_sum_s cn68xx; + struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1; +}; + +union cvmx_mio_fus_tgg { + uint64_t u64; + struct cvmx_mio_fus_tgg_s { + uint64_t val:1; + uint64_t dat:63; + } s; + struct cvmx_mio_fus_tgg_s cn61xx; + struct cvmx_mio_fus_tgg_s cn66xx; }; union cvmx_mio_fus_unlock { @@ -1141,11 +1603,15 @@ union cvmx_mio_fus_wadr { struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; struct cvmx_mio_fus_wadr_cn50xx cn58xx; struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; - struct cvmx_mio_fus_wadr_cn63xx { + struct cvmx_mio_fus_wadr_cn61xx { uint64_t reserved_4_63:60; uint64_t addr:4; - } cn63xx; - struct cvmx_mio_fus_wadr_cn63xx cn63xxp1; + } cn61xx; + struct cvmx_mio_fus_wadr_cn61xx cn63xx; + struct cvmx_mio_fus_wadr_cn61xx cn63xxp1; + struct cvmx_mio_fus_wadr_cn61xx cn66xx; + struct cvmx_mio_fus_wadr_cn61xx cn68xx; + struct cvmx_mio_fus_wadr_cn61xx cn68xxp1; }; union cvmx_mio_gpio_comp { @@ -1155,8 +1621,12 @@ union cvmx_mio_gpio_comp { uint64_t pctl:6; uint64_t nctl:6; } s; + struct cvmx_mio_gpio_comp_s cn61xx; struct cvmx_mio_gpio_comp_s cn63xx; struct cvmx_mio_gpio_comp_s cn63xxp1; + struct cvmx_mio_gpio_comp_s cn66xx; + struct cvmx_mio_gpio_comp_s cn68xx; + struct cvmx_mio_gpio_comp_s cn68xxp1; }; union cvmx_mio_ndf_dma_cfg { @@ -1174,8 +1644,12 @@ union cvmx_mio_ndf_dma_cfg { uint64_t adr:36; } s; struct cvmx_mio_ndf_dma_cfg_s cn52xx; + struct cvmx_mio_ndf_dma_cfg_s cn61xx; struct cvmx_mio_ndf_dma_cfg_s cn63xx; struct cvmx_mio_ndf_dma_cfg_s cn63xxp1; + struct cvmx_mio_ndf_dma_cfg_s cn66xx; + struct cvmx_mio_ndf_dma_cfg_s cn68xx; + struct cvmx_mio_ndf_dma_cfg_s cn68xxp1; }; union cvmx_mio_ndf_dma_int { @@ -1185,8 +1659,12 @@ union cvmx_mio_ndf_dma_int { uint64_t done:1; } s; struct cvmx_mio_ndf_dma_int_s cn52xx; + struct cvmx_mio_ndf_dma_int_s cn61xx; struct cvmx_mio_ndf_dma_int_s cn63xx; struct cvmx_mio_ndf_dma_int_s cn63xxp1; + struct cvmx_mio_ndf_dma_int_s cn66xx; + struct cvmx_mio_ndf_dma_int_s cn68xx; + struct cvmx_mio_ndf_dma_int_s cn68xxp1; }; union cvmx_mio_ndf_dma_int_en { @@ -1196,8 +1674,12 @@ union cvmx_mio_ndf_dma_int_en { uint64_t done:1; } s; struct cvmx_mio_ndf_dma_int_en_s cn52xx; + struct cvmx_mio_ndf_dma_int_en_s cn61xx; struct cvmx_mio_ndf_dma_int_en_s cn63xx; struct cvmx_mio_ndf_dma_int_en_s cn63xxp1; + struct cvmx_mio_ndf_dma_int_en_s cn66xx; + struct cvmx_mio_ndf_dma_int_en_s cn68xx; + struct cvmx_mio_ndf_dma_int_en_s cn68xxp1; }; union cvmx_mio_pll_ctl { @@ -1220,10 +1702,63 @@ union cvmx_mio_pll_setting { struct cvmx_mio_pll_setting_s cn31xx; }; +union cvmx_mio_ptp_ckout_hi_incr { + uint64_t u64; + struct cvmx_mio_ptp_ckout_hi_incr_s { + uint64_t nanosec:32; + uint64_t frnanosec:32; + } s; + struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx; + struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx; + struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx; +}; + +union cvmx_mio_ptp_ckout_lo_incr { + uint64_t u64; + struct cvmx_mio_ptp_ckout_lo_incr_s { + uint64_t nanosec:32; + uint64_t frnanosec:32; + } s; + struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx; + struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx; + struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx; +}; + +union cvmx_mio_ptp_ckout_thresh_hi { + uint64_t u64; + struct cvmx_mio_ptp_ckout_thresh_hi_s { + uint64_t nanosec:64; + } s; + struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx; + struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx; + struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx; +}; + +union cvmx_mio_ptp_ckout_thresh_lo { + uint64_t u64; + struct cvmx_mio_ptp_ckout_thresh_lo_s { + uint64_t reserved_32_63:32; + uint64_t frnanosec:32; + } s; + struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx; + struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx; + struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx; +}; + union cvmx_mio_ptp_clock_cfg { uint64_t u64; struct cvmx_mio_ptp_clock_cfg_s { - uint64_t reserved_24_63:40; + uint64_t reserved_42_63:22; + uint64_t pps:1; + uint64_t ckout:1; + uint64_t ext_clk_edge:2; + uint64_t ckout_out4:1; + uint64_t pps_out:5; + uint64_t pps_inv:1; + uint64_t pps_en:1; + uint64_t ckout_out:4; + uint64_t ckout_inv:1; + uint64_t ckout_en:1; uint64_t evcnt_in:6; uint64_t evcnt_edge:1; uint64_t evcnt_en:1; @@ -1234,8 +1769,42 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_en:1; uint64_t ptp_en:1; } s; - struct cvmx_mio_ptp_clock_cfg_s cn63xx; - struct cvmx_mio_ptp_clock_cfg_s cn63xxp1; + struct cvmx_mio_ptp_clock_cfg_s cn61xx; + struct cvmx_mio_ptp_clock_cfg_cn63xx { + uint64_t reserved_24_63:40; + uint64_t evcnt_in:6; + uint64_t evcnt_edge:1; + uint64_t evcnt_en:1; + uint64_t tstmp_in:6; + uint64_t tstmp_edge:1; + uint64_t tstmp_en:1; + uint64_t ext_clk_in:6; + uint64_t ext_clk_en:1; + uint64_t ptp_en:1; + } cn63xx; + struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1; + struct cvmx_mio_ptp_clock_cfg_cn66xx { + uint64_t reserved_40_63:24; + uint64_t ext_clk_edge:2; + uint64_t ckout_out4:1; + uint64_t pps_out:5; + uint64_t pps_inv:1; + uint64_t pps_en:1; + uint64_t ckout_out:4; + uint64_t ckout_inv:1; + uint64_t ckout_en:1; + uint64_t evcnt_in:6; + uint64_t evcnt_edge:1; + uint64_t evcnt_en:1; + uint64_t tstmp_in:6; + uint64_t tstmp_edge:1; + uint64_t tstmp_en:1; + uint64_t ext_clk_in:6; + uint64_t ext_clk_en:1; + uint64_t ptp_en:1; + } cn66xx; + struct cvmx_mio_ptp_clock_cfg_s cn68xx; + struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1; }; union cvmx_mio_ptp_clock_comp { @@ -1244,8 +1813,12 @@ union cvmx_mio_ptp_clock_comp { uint64_t nanosec:32; uint64_t frnanosec:32; } s; + struct cvmx_mio_ptp_clock_comp_s cn61xx; struct cvmx_mio_ptp_clock_comp_s cn63xx; struct cvmx_mio_ptp_clock_comp_s cn63xxp1; + struct cvmx_mio_ptp_clock_comp_s cn66xx; + struct cvmx_mio_ptp_clock_comp_s cn68xx; + struct cvmx_mio_ptp_clock_comp_s cn68xxp1; }; union cvmx_mio_ptp_clock_hi { @@ -1253,8 +1826,12 @@ union cvmx_mio_ptp_clock_hi { struct cvmx_mio_ptp_clock_hi_s { uint64_t nanosec:64; } s; + struct cvmx_mio_ptp_clock_hi_s cn61xx; struct cvmx_mio_ptp_clock_hi_s cn63xx; struct cvmx_mio_ptp_clock_hi_s cn63xxp1; + struct cvmx_mio_ptp_clock_hi_s cn66xx; + struct cvmx_mio_ptp_clock_hi_s cn68xx; + struct cvmx_mio_ptp_clock_hi_s cn68xxp1; }; union cvmx_mio_ptp_clock_lo { @@ -1263,8 +1840,12 @@ union cvmx_mio_ptp_clock_lo { uint64_t reserved_32_63:32; uint64_t frnanosec:32; } s; + struct cvmx_mio_ptp_clock_lo_s cn61xx; struct cvmx_mio_ptp_clock_lo_s cn63xx; struct cvmx_mio_ptp_clock_lo_s cn63xxp1; + struct cvmx_mio_ptp_clock_lo_s cn66xx; + struct cvmx_mio_ptp_clock_lo_s cn68xx; + struct cvmx_mio_ptp_clock_lo_s cn68xxp1; }; union cvmx_mio_ptp_evt_cnt { @@ -1272,8 +1853,55 @@ union cvmx_mio_ptp_evt_cnt { struct cvmx_mio_ptp_evt_cnt_s { uint64_t cntr:64; } s; + struct cvmx_mio_ptp_evt_cnt_s cn61xx; struct cvmx_mio_ptp_evt_cnt_s cn63xx; struct cvmx_mio_ptp_evt_cnt_s cn63xxp1; + struct cvmx_mio_ptp_evt_cnt_s cn66xx; + struct cvmx_mio_ptp_evt_cnt_s cn68xx; + struct cvmx_mio_ptp_evt_cnt_s cn68xxp1; +}; + +union cvmx_mio_ptp_pps_hi_incr { + uint64_t u64; + struct cvmx_mio_ptp_pps_hi_incr_s { + uint64_t nanosec:32; + uint64_t frnanosec:32; + } s; + struct cvmx_mio_ptp_pps_hi_incr_s cn61xx; + struct cvmx_mio_ptp_pps_hi_incr_s cn66xx; + struct cvmx_mio_ptp_pps_hi_incr_s cn68xx; +}; + +union cvmx_mio_ptp_pps_lo_incr { + uint64_t u64; + struct cvmx_mio_ptp_pps_lo_incr_s { + uint64_t nanosec:32; + uint64_t frnanosec:32; + } s; + struct cvmx_mio_ptp_pps_lo_incr_s cn61xx; + struct cvmx_mio_ptp_pps_lo_incr_s cn66xx; + struct cvmx_mio_ptp_pps_lo_incr_s cn68xx; +}; + +union cvmx_mio_ptp_pps_thresh_hi { + uint64_t u64; + struct cvmx_mio_ptp_pps_thresh_hi_s { + uint64_t nanosec:64; + } s; + struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx; + struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx; + struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx; +}; + +union cvmx_mio_ptp_pps_thresh_lo { + uint64_t u64; + struct cvmx_mio_ptp_pps_thresh_lo_s { + uint64_t reserved_32_63:32; + uint64_t frnanosec:32; + } s; + struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx; + struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx; + struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx; }; union cvmx_mio_ptp_timestamp { @@ -1281,14 +1909,52 @@ union cvmx_mio_ptp_timestamp { struct cvmx_mio_ptp_timestamp_s { uint64_t nanosec:64; } s; + struct cvmx_mio_ptp_timestamp_s cn61xx; struct cvmx_mio_ptp_timestamp_s cn63xx; struct cvmx_mio_ptp_timestamp_s cn63xxp1; + struct cvmx_mio_ptp_timestamp_s cn66xx; + struct cvmx_mio_ptp_timestamp_s cn68xx; + struct cvmx_mio_ptp_timestamp_s cn68xxp1; +}; + +union cvmx_mio_qlmx_cfg { + uint64_t u64; + struct cvmx_mio_qlmx_cfg_s { + uint64_t reserved_12_63:52; + uint64_t qlm_spd:4; + uint64_t reserved_4_7:4; + uint64_t qlm_cfg:4; + } s; + struct cvmx_mio_qlmx_cfg_cn61xx { + uint64_t reserved_12_63:52; + uint64_t qlm_spd:4; + uint64_t reserved_2_7:6; + uint64_t qlm_cfg:2; + } cn61xx; + struct cvmx_mio_qlmx_cfg_s cn66xx; + struct cvmx_mio_qlmx_cfg_cn68xx { + uint64_t reserved_12_63:52; + uint64_t qlm_spd:4; + uint64_t reserved_3_7:5; + uint64_t qlm_cfg:3; + } cn68xx; + struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1; }; union cvmx_mio_rst_boot { uint64_t u64; struct cvmx_mio_rst_boot_s { - uint64_t reserved_36_63:28; + uint64_t chipkill:1; + uint64_t jtcsrdis:1; + uint64_t ejtagdis:1; + uint64_t romen:1; + uint64_t ckill_ppdis:1; + uint64_t jt_tstmode:1; + uint64_t reserved_50_57:8; + uint64_t lboot_ext:2; + uint64_t reserved_44_47:4; + uint64_t qlm4_spd:4; + uint64_t qlm3_spd:4; uint64_t c_mul:6; uint64_t pnr_mul:6; uint64_t qlm2_spd:4; @@ -1298,32 +1964,135 @@ union cvmx_mio_rst_boot { uint64_t rboot:1; uint64_t rboot_pin:1; } s; - struct cvmx_mio_rst_boot_s cn63xx; - struct cvmx_mio_rst_boot_s cn63xxp1; + struct cvmx_mio_rst_boot_cn61xx { + uint64_t chipkill:1; + uint64_t jtcsrdis:1; + uint64_t ejtagdis:1; + uint64_t romen:1; + uint64_t ckill_ppdis:1; + uint64_t jt_tstmode:1; + uint64_t reserved_50_57:8; + uint64_t lboot_ext:2; + uint64_t reserved_36_47:12; + uint64_t c_mul:6; + uint64_t pnr_mul:6; + uint64_t qlm2_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm0_spd:4; + uint64_t lboot:10; + uint64_t rboot:1; + uint64_t rboot_pin:1; + } cn61xx; + struct cvmx_mio_rst_boot_cn63xx { + uint64_t reserved_36_63:28; + uint64_t c_mul:6; + uint64_t pnr_mul:6; + uint64_t qlm2_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm0_spd:4; + uint64_t lboot:10; + uint64_t rboot:1; + uint64_t rboot_pin:1; + } cn63xx; + struct cvmx_mio_rst_boot_cn63xx cn63xxp1; + struct cvmx_mio_rst_boot_cn66xx { + uint64_t chipkill:1; + uint64_t jtcsrdis:1; + uint64_t ejtagdis:1; + uint64_t romen:1; + uint64_t ckill_ppdis:1; + uint64_t reserved_50_58:9; + uint64_t lboot_ext:2; + uint64_t reserved_36_47:12; + uint64_t c_mul:6; + uint64_t pnr_mul:6; + uint64_t qlm2_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm0_spd:4; + uint64_t lboot:10; + uint64_t rboot:1; + uint64_t rboot_pin:1; + } cn66xx; + struct cvmx_mio_rst_boot_cn68xx { + uint64_t reserved_59_63:5; + uint64_t jt_tstmode:1; + uint64_t reserved_44_57:14; + uint64_t qlm4_spd:4; + uint64_t qlm3_spd:4; + uint64_t c_mul:6; + uint64_t pnr_mul:6; + uint64_t qlm2_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm0_spd:4; + uint64_t lboot:10; + uint64_t rboot:1; + uint64_t rboot_pin:1; + } cn68xx; + struct cvmx_mio_rst_boot_cn68xxp1 { + uint64_t reserved_44_63:20; + uint64_t qlm4_spd:4; + uint64_t qlm3_spd:4; + uint64_t c_mul:6; + uint64_t pnr_mul:6; + uint64_t qlm2_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm0_spd:4; + uint64_t lboot:10; + uint64_t rboot:1; + uint64_t rboot_pin:1; + } cn68xxp1; }; union cvmx_mio_rst_cfg { uint64_t u64; struct cvmx_mio_rst_cfg_s { + uint64_t reserved_3_63:61; + uint64_t cntl_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t soft_clr_bist:1; + } s; + struct cvmx_mio_rst_cfg_cn61xx { uint64_t bist_delay:58; uint64_t reserved_3_5:3; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; - } s; - struct cvmx_mio_rst_cfg_s cn63xx; + } cn61xx; + struct cvmx_mio_rst_cfg_cn61xx cn63xx; struct cvmx_mio_rst_cfg_cn63xxp1 { uint64_t bist_delay:58; uint64_t reserved_2_5:4; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; } cn63xxp1; + struct cvmx_mio_rst_cfg_cn61xx cn66xx; + struct cvmx_mio_rst_cfg_cn68xx { + uint64_t bist_delay:56; + uint64_t reserved_3_7:5; + uint64_t cntl_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t soft_clr_bist:1; + } cn68xx; + struct cvmx_mio_rst_cfg_cn68xx cn68xxp1; }; -union cvmx_mio_rst_ctlx { +union cvmx_mio_rst_ckill { uint64_t u64; - struct cvmx_mio_rst_ctlx_s { - uint64_t reserved_10_63:54; + struct cvmx_mio_rst_ckill_s { + uint64_t reserved_47_63:17; + uint64_t timer:47; + } s; + struct cvmx_mio_rst_ckill_s cn61xx; + struct cvmx_mio_rst_ckill_s cn66xx; +}; + +union cvmx_mio_rst_cntlx { + uint64_t u64; + struct cvmx_mio_rst_cntlx_s { + uint64_t reserved_13_63:51; + uint64_t in_rev_ln:1; + uint64_t rev_lanes:1; + uint64_t gen1_only:1; uint64_t prst_link:1; uint64_t rst_done:1; uint64_t rst_link:1; @@ -1334,7 +2103,52 @@ union cvmx_mio_rst_ctlx { uint64_t rst_chip:1; uint64_t rst_val:1; } s; - struct cvmx_mio_rst_ctlx_s cn63xx; + struct cvmx_mio_rst_cntlx_s cn61xx; + struct cvmx_mio_rst_cntlx_cn66xx { + uint64_t reserved_10_63:54; + uint64_t prst_link:1; + uint64_t rst_done:1; + uint64_t rst_link:1; + uint64_t host_mode:1; + uint64_t prtmode:2; + uint64_t rst_drv:1; + uint64_t rst_rcv:1; + uint64_t rst_chip:1; + uint64_t rst_val:1; + } cn66xx; + struct cvmx_mio_rst_cntlx_cn66xx cn68xx; +}; + +union cvmx_mio_rst_ctlx { + uint64_t u64; + struct cvmx_mio_rst_ctlx_s { + uint64_t reserved_13_63:51; + uint64_t in_rev_ln:1; + uint64_t rev_lanes:1; + uint64_t gen1_only:1; + uint64_t prst_link:1; + uint64_t rst_done:1; + uint64_t rst_link:1; + uint64_t host_mode:1; + uint64_t prtmode:2; + uint64_t rst_drv:1; + uint64_t rst_rcv:1; + uint64_t rst_chip:1; + uint64_t rst_val:1; + } s; + struct cvmx_mio_rst_ctlx_s cn61xx; + struct cvmx_mio_rst_ctlx_cn63xx { + uint64_t reserved_10_63:54; + uint64_t prst_link:1; + uint64_t rst_done:1; + uint64_t rst_link:1; + uint64_t host_mode:1; + uint64_t prtmode:2; + uint64_t rst_drv:1; + uint64_t rst_rcv:1; + uint64_t rst_chip:1; + uint64_t rst_val:1; + } cn63xx; struct cvmx_mio_rst_ctlx_cn63xxp1 { uint64_t reserved_9_63:55; uint64_t rst_done:1; @@ -1346,17 +2160,24 @@ union cvmx_mio_rst_ctlx { uint64_t rst_chip:1; uint64_t rst_val:1; } cn63xxp1; + struct cvmx_mio_rst_ctlx_cn63xx cn66xx; + struct cvmx_mio_rst_ctlx_cn63xx cn68xx; + struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1; }; union cvmx_mio_rst_delay { uint64_t u64; struct cvmx_mio_rst_delay_s { uint64_t reserved_32_63:32; - uint64_t soft_rst_dly:16; uint64_t warm_rst_dly:16; + uint64_t soft_rst_dly:16; } s; + struct cvmx_mio_rst_delay_s cn61xx; struct cvmx_mio_rst_delay_s cn63xx; struct cvmx_mio_rst_delay_s cn63xxp1; + struct cvmx_mio_rst_delay_s cn66xx; + struct cvmx_mio_rst_delay_s cn68xx; + struct cvmx_mio_rst_delay_s cn68xxp1; }; union cvmx_mio_rst_int { @@ -1365,12 +2186,25 @@ union cvmx_mio_rst_int { uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; - uint64_t reserved_2_7:6; + uint64_t reserved_4_7:4; + uint64_t rst_link3:1; + uint64_t rst_link2:1; uint64_t rst_link1:1; uint64_t rst_link0:1; } s; - struct cvmx_mio_rst_int_s cn63xx; - struct cvmx_mio_rst_int_s cn63xxp1; + struct cvmx_mio_rst_int_cn61xx { + uint64_t reserved_10_63:54; + uint64_t perst1:1; + uint64_t perst0:1; + uint64_t reserved_2_7:6; + uint64_t rst_link1:1; + uint64_t rst_link0:1; + } cn61xx; + struct cvmx_mio_rst_int_cn61xx cn63xx; + struct cvmx_mio_rst_int_cn61xx cn63xxp1; + struct cvmx_mio_rst_int_s cn66xx; + struct cvmx_mio_rst_int_cn61xx cn68xx; + struct cvmx_mio_rst_int_cn61xx cn68xxp1; }; union cvmx_mio_rst_int_en { @@ -1379,12 +2213,25 @@ union cvmx_mio_rst_int_en { uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; - uint64_t reserved_2_7:6; + uint64_t reserved_4_7:4; + uint64_t rst_link3:1; + uint64_t rst_link2:1; uint64_t rst_link1:1; uint64_t rst_link0:1; } s; - struct cvmx_mio_rst_int_en_s cn63xx; - struct cvmx_mio_rst_int_en_s cn63xxp1; + struct cvmx_mio_rst_int_en_cn61xx { + uint64_t reserved_10_63:54; + uint64_t perst1:1; + uint64_t perst0:1; + uint64_t reserved_2_7:6; + uint64_t rst_link1:1; + uint64_t rst_link0:1; + } cn61xx; + struct cvmx_mio_rst_int_en_cn61xx cn63xx; + struct cvmx_mio_rst_int_en_cn61xx cn63xxp1; + struct cvmx_mio_rst_int_en_s cn66xx; + struct cvmx_mio_rst_int_en_cn61xx cn68xx; + struct cvmx_mio_rst_int_en_cn61xx cn68xxp1; }; union cvmx_mio_twsx_int { @@ -1424,8 +2271,12 @@ union cvmx_mio_twsx_int { struct cvmx_mio_twsx_int_s cn56xxp1; struct cvmx_mio_twsx_int_s cn58xx; struct cvmx_mio_twsx_int_s cn58xxp1; + struct cvmx_mio_twsx_int_s cn61xx; struct cvmx_mio_twsx_int_s cn63xx; struct cvmx_mio_twsx_int_s cn63xxp1; + struct cvmx_mio_twsx_int_s cn66xx; + struct cvmx_mio_twsx_int_s cn68xx; + struct cvmx_mio_twsx_int_s cn68xxp1; }; union cvmx_mio_twsx_sw_twsi { @@ -1455,8 +2306,12 @@ union cvmx_mio_twsx_sw_twsi { struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; struct cvmx_mio_twsx_sw_twsi_s cn58xx; struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; + struct cvmx_mio_twsx_sw_twsi_s cn61xx; struct cvmx_mio_twsx_sw_twsi_s cn63xx; struct cvmx_mio_twsx_sw_twsi_s cn63xxp1; + struct cvmx_mio_twsx_sw_twsi_s cn66xx; + struct cvmx_mio_twsx_sw_twsi_s cn68xx; + struct cvmx_mio_twsx_sw_twsi_s cn68xxp1; }; union cvmx_mio_twsx_sw_twsi_ext { @@ -1477,8 +2332,12 @@ union cvmx_mio_twsx_sw_twsi_ext { struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; + struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1; + struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx; + struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx; + struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1; }; union cvmx_mio_twsx_twsi_sw { @@ -1499,8 +2358,12 @@ union cvmx_mio_twsx_twsi_sw { struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; struct cvmx_mio_twsx_twsi_sw_s cn58xx; struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; + struct cvmx_mio_twsx_twsi_sw_s cn61xx; struct cvmx_mio_twsx_twsi_sw_s cn63xx; struct cvmx_mio_twsx_twsi_sw_s cn63xxp1; + struct cvmx_mio_twsx_twsi_sw_s cn66xx; + struct cvmx_mio_twsx_twsi_sw_s cn68xx; + struct cvmx_mio_twsx_twsi_sw_s cn68xxp1; }; union cvmx_mio_uartx_dlh { @@ -1520,8 +2383,12 @@ union cvmx_mio_uartx_dlh { struct cvmx_mio_uartx_dlh_s cn56xxp1; struct cvmx_mio_uartx_dlh_s cn58xx; struct cvmx_mio_uartx_dlh_s cn58xxp1; + struct cvmx_mio_uartx_dlh_s cn61xx; struct cvmx_mio_uartx_dlh_s cn63xx; struct cvmx_mio_uartx_dlh_s cn63xxp1; + struct cvmx_mio_uartx_dlh_s cn66xx; + struct cvmx_mio_uartx_dlh_s cn68xx; + struct cvmx_mio_uartx_dlh_s cn68xxp1; }; union cvmx_mio_uartx_dll { @@ -1541,8 +2408,12 @@ union cvmx_mio_uartx_dll { struct cvmx_mio_uartx_dll_s cn56xxp1; struct cvmx_mio_uartx_dll_s cn58xx; struct cvmx_mio_uartx_dll_s cn58xxp1; + struct cvmx_mio_uartx_dll_s cn61xx; struct cvmx_mio_uartx_dll_s cn63xx; struct cvmx_mio_uartx_dll_s cn63xxp1; + struct cvmx_mio_uartx_dll_s cn66xx; + struct cvmx_mio_uartx_dll_s cn68xx; + struct cvmx_mio_uartx_dll_s cn68xxp1; }; union cvmx_mio_uartx_far { @@ -1562,8 +2433,12 @@ union cvmx_mio_uartx_far { struct cvmx_mio_uartx_far_s cn56xxp1; struct cvmx_mio_uartx_far_s cn58xx; struct cvmx_mio_uartx_far_s cn58xxp1; + struct cvmx_mio_uartx_far_s cn61xx; struct cvmx_mio_uartx_far_s cn63xx; struct cvmx_mio_uartx_far_s cn63xxp1; + struct cvmx_mio_uartx_far_s cn66xx; + struct cvmx_mio_uartx_far_s cn68xx; + struct cvmx_mio_uartx_far_s cn68xxp1; }; union cvmx_mio_uartx_fcr { @@ -1588,8 +2463,12 @@ union cvmx_mio_uartx_fcr { struct cvmx_mio_uartx_fcr_s cn56xxp1; struct cvmx_mio_uartx_fcr_s cn58xx; struct cvmx_mio_uartx_fcr_s cn58xxp1; + struct cvmx_mio_uartx_fcr_s cn61xx; struct cvmx_mio_uartx_fcr_s cn63xx; struct cvmx_mio_uartx_fcr_s cn63xxp1; + struct cvmx_mio_uartx_fcr_s cn66xx; + struct cvmx_mio_uartx_fcr_s cn68xx; + struct cvmx_mio_uartx_fcr_s cn68xxp1; }; union cvmx_mio_uartx_htx { @@ -1609,8 +2488,12 @@ union cvmx_mio_uartx_htx { struct cvmx_mio_uartx_htx_s cn56xxp1; struct cvmx_mio_uartx_htx_s cn58xx; struct cvmx_mio_uartx_htx_s cn58xxp1; + struct cvmx_mio_uartx_htx_s cn61xx; struct cvmx_mio_uartx_htx_s cn63xx; struct cvmx_mio_uartx_htx_s cn63xxp1; + struct cvmx_mio_uartx_htx_s cn66xx; + struct cvmx_mio_uartx_htx_s cn68xx; + struct cvmx_mio_uartx_htx_s cn68xxp1; }; union cvmx_mio_uartx_ier { @@ -1635,8 +2518,12 @@ union cvmx_mio_uartx_ier { struct cvmx_mio_uartx_ier_s cn56xxp1; struct cvmx_mio_uartx_ier_s cn58xx; struct cvmx_mio_uartx_ier_s cn58xxp1; + struct cvmx_mio_uartx_ier_s cn61xx; struct cvmx_mio_uartx_ier_s cn63xx; struct cvmx_mio_uartx_ier_s cn63xxp1; + struct cvmx_mio_uartx_ier_s cn66xx; + struct cvmx_mio_uartx_ier_s cn68xx; + struct cvmx_mio_uartx_ier_s cn68xxp1; }; union cvmx_mio_uartx_iir { @@ -1658,8 +2545,12 @@ union cvmx_mio_uartx_iir { struct cvmx_mio_uartx_iir_s cn56xxp1; struct cvmx_mio_uartx_iir_s cn58xx; struct cvmx_mio_uartx_iir_s cn58xxp1; + struct cvmx_mio_uartx_iir_s cn61xx; struct cvmx_mio_uartx_iir_s cn63xx; struct cvmx_mio_uartx_iir_s cn63xxp1; + struct cvmx_mio_uartx_iir_s cn66xx; + struct cvmx_mio_uartx_iir_s cn68xx; + struct cvmx_mio_uartx_iir_s cn68xxp1; }; union cvmx_mio_uartx_lcr { @@ -1685,8 +2576,12 @@ union cvmx_mio_uartx_lcr { struct cvmx_mio_uartx_lcr_s cn56xxp1; struct cvmx_mio_uartx_lcr_s cn58xx; struct cvmx_mio_uartx_lcr_s cn58xxp1; + struct cvmx_mio_uartx_lcr_s cn61xx; struct cvmx_mio_uartx_lcr_s cn63xx; struct cvmx_mio_uartx_lcr_s cn63xxp1; + struct cvmx_mio_uartx_lcr_s cn66xx; + struct cvmx_mio_uartx_lcr_s cn68xx; + struct cvmx_mio_uartx_lcr_s cn68xxp1; }; union cvmx_mio_uartx_lsr { @@ -1713,8 +2608,12 @@ union cvmx_mio_uartx_lsr { struct cvmx_mio_uartx_lsr_s cn56xxp1; struct cvmx_mio_uartx_lsr_s cn58xx; struct cvmx_mio_uartx_lsr_s cn58xxp1; + struct cvmx_mio_uartx_lsr_s cn61xx; struct cvmx_mio_uartx_lsr_s cn63xx; struct cvmx_mio_uartx_lsr_s cn63xxp1; + struct cvmx_mio_uartx_lsr_s cn66xx; + struct cvmx_mio_uartx_lsr_s cn68xx; + struct cvmx_mio_uartx_lsr_s cn68xxp1; }; union cvmx_mio_uartx_mcr { @@ -1739,8 +2638,12 @@ union cvmx_mio_uartx_mcr { struct cvmx_mio_uartx_mcr_s cn56xxp1; struct cvmx_mio_uartx_mcr_s cn58xx; struct cvmx_mio_uartx_mcr_s cn58xxp1; + struct cvmx_mio_uartx_mcr_s cn61xx; struct cvmx_mio_uartx_mcr_s cn63xx; struct cvmx_mio_uartx_mcr_s cn63xxp1; + struct cvmx_mio_uartx_mcr_s cn66xx; + struct cvmx_mio_uartx_mcr_s cn68xx; + struct cvmx_mio_uartx_mcr_s cn68xxp1; }; union cvmx_mio_uartx_msr { @@ -1767,8 +2670,12 @@ union cvmx_mio_uartx_msr { struct cvmx_mio_uartx_msr_s cn56xxp1; struct cvmx_mio_uartx_msr_s cn58xx; struct cvmx_mio_uartx_msr_s cn58xxp1; + struct cvmx_mio_uartx_msr_s cn61xx; struct cvmx_mio_uartx_msr_s cn63xx; struct cvmx_mio_uartx_msr_s cn63xxp1; + struct cvmx_mio_uartx_msr_s cn66xx; + struct cvmx_mio_uartx_msr_s cn68xx; + struct cvmx_mio_uartx_msr_s cn68xxp1; }; union cvmx_mio_uartx_rbr { @@ -1788,8 +2695,12 @@ union cvmx_mio_uartx_rbr { struct cvmx_mio_uartx_rbr_s cn56xxp1; struct cvmx_mio_uartx_rbr_s cn58xx; struct cvmx_mio_uartx_rbr_s cn58xxp1; + struct cvmx_mio_uartx_rbr_s cn61xx; struct cvmx_mio_uartx_rbr_s cn63xx; struct cvmx_mio_uartx_rbr_s cn63xxp1; + struct cvmx_mio_uartx_rbr_s cn66xx; + struct cvmx_mio_uartx_rbr_s cn68xx; + struct cvmx_mio_uartx_rbr_s cn68xxp1; }; union cvmx_mio_uartx_rfl { @@ -1809,8 +2720,12 @@ union cvmx_mio_uartx_rfl { struct cvmx_mio_uartx_rfl_s cn56xxp1; struct cvmx_mio_uartx_rfl_s cn58xx; struct cvmx_mio_uartx_rfl_s cn58xxp1; + struct cvmx_mio_uartx_rfl_s cn61xx; struct cvmx_mio_uartx_rfl_s cn63xx; struct cvmx_mio_uartx_rfl_s cn63xxp1; + struct cvmx_mio_uartx_rfl_s cn66xx; + struct cvmx_mio_uartx_rfl_s cn68xx; + struct cvmx_mio_uartx_rfl_s cn68xxp1; }; union cvmx_mio_uartx_rfw { @@ -1832,8 +2747,12 @@ union cvmx_mio_uartx_rfw { struct cvmx_mio_uartx_rfw_s cn56xxp1; struct cvmx_mio_uartx_rfw_s cn58xx; struct cvmx_mio_uartx_rfw_s cn58xxp1; + struct cvmx_mio_uartx_rfw_s cn61xx; struct cvmx_mio_uartx_rfw_s cn63xx; struct cvmx_mio_uartx_rfw_s cn63xxp1; + struct cvmx_mio_uartx_rfw_s cn66xx; + struct cvmx_mio_uartx_rfw_s cn68xx; + struct cvmx_mio_uartx_rfw_s cn68xxp1; }; union cvmx_mio_uartx_sbcr { @@ -1853,8 +2772,12 @@ union cvmx_mio_uartx_sbcr { struct cvmx_mio_uartx_sbcr_s cn56xxp1; struct cvmx_mio_uartx_sbcr_s cn58xx; struct cvmx_mio_uartx_sbcr_s cn58xxp1; + struct cvmx_mio_uartx_sbcr_s cn61xx; struct cvmx_mio_uartx_sbcr_s cn63xx; struct cvmx_mio_uartx_sbcr_s cn63xxp1; + struct cvmx_mio_uartx_sbcr_s cn66xx; + struct cvmx_mio_uartx_sbcr_s cn68xx; + struct cvmx_mio_uartx_sbcr_s cn68xxp1; }; union cvmx_mio_uartx_scr { @@ -1874,8 +2797,12 @@ union cvmx_mio_uartx_scr { struct cvmx_mio_uartx_scr_s cn56xxp1; struct cvmx_mio_uartx_scr_s cn58xx; struct cvmx_mio_uartx_scr_s cn58xxp1; + struct cvmx_mio_uartx_scr_s cn61xx; struct cvmx_mio_uartx_scr_s cn63xx; struct cvmx_mio_uartx_scr_s cn63xxp1; + struct cvmx_mio_uartx_scr_s cn66xx; + struct cvmx_mio_uartx_scr_s cn68xx; + struct cvmx_mio_uartx_scr_s cn68xxp1; }; union cvmx_mio_uartx_sfe { @@ -1895,8 +2822,12 @@ union cvmx_mio_uartx_sfe { struct cvmx_mio_uartx_sfe_s cn56xxp1; struct cvmx_mio_uartx_sfe_s cn58xx; struct cvmx_mio_uartx_sfe_s cn58xxp1; + struct cvmx_mio_uartx_sfe_s cn61xx; struct cvmx_mio_uartx_sfe_s cn63xx; struct cvmx_mio_uartx_sfe_s cn63xxp1; + struct cvmx_mio_uartx_sfe_s cn66xx; + struct cvmx_mio_uartx_sfe_s cn68xx; + struct cvmx_mio_uartx_sfe_s cn68xxp1; }; union cvmx_mio_uartx_srr { @@ -1918,8 +2849,12 @@ union cvmx_mio_uartx_srr { struct cvmx_mio_uartx_srr_s cn56xxp1; struct cvmx_mio_uartx_srr_s cn58xx; struct cvmx_mio_uartx_srr_s cn58xxp1; + struct cvmx_mio_uartx_srr_s cn61xx; struct cvmx_mio_uartx_srr_s cn63xx; struct cvmx_mio_uartx_srr_s cn63xxp1; + struct cvmx_mio_uartx_srr_s cn66xx; + struct cvmx_mio_uartx_srr_s cn68xx; + struct cvmx_mio_uartx_srr_s cn68xxp1; }; union cvmx_mio_uartx_srt { @@ -1939,8 +2874,12 @@ union cvmx_mio_uartx_srt { struct cvmx_mio_uartx_srt_s cn56xxp1; struct cvmx_mio_uartx_srt_s cn58xx; struct cvmx_mio_uartx_srt_s cn58xxp1; + struct cvmx_mio_uartx_srt_s cn61xx; struct cvmx_mio_uartx_srt_s cn63xx; struct cvmx_mio_uartx_srt_s cn63xxp1; + struct cvmx_mio_uartx_srt_s cn66xx; + struct cvmx_mio_uartx_srt_s cn68xx; + struct cvmx_mio_uartx_srt_s cn68xxp1; }; union cvmx_mio_uartx_srts { @@ -1960,8 +2899,12 @@ union cvmx_mio_uartx_srts { struct cvmx_mio_uartx_srts_s cn56xxp1; struct cvmx_mio_uartx_srts_s cn58xx; struct cvmx_mio_uartx_srts_s cn58xxp1; + struct cvmx_mio_uartx_srts_s cn61xx; struct cvmx_mio_uartx_srts_s cn63xx; struct cvmx_mio_uartx_srts_s cn63xxp1; + struct cvmx_mio_uartx_srts_s cn66xx; + struct cvmx_mio_uartx_srts_s cn68xx; + struct cvmx_mio_uartx_srts_s cn68xxp1; }; union cvmx_mio_uartx_stt { @@ -1981,8 +2924,12 @@ union cvmx_mio_uartx_stt { struct cvmx_mio_uartx_stt_s cn56xxp1; struct cvmx_mio_uartx_stt_s cn58xx; struct cvmx_mio_uartx_stt_s cn58xxp1; + struct cvmx_mio_uartx_stt_s cn61xx; struct cvmx_mio_uartx_stt_s cn63xx; struct cvmx_mio_uartx_stt_s cn63xxp1; + struct cvmx_mio_uartx_stt_s cn66xx; + struct cvmx_mio_uartx_stt_s cn68xx; + struct cvmx_mio_uartx_stt_s cn68xxp1; }; union cvmx_mio_uartx_tfl { @@ -2002,8 +2949,12 @@ union cvmx_mio_uartx_tfl { struct cvmx_mio_uartx_tfl_s cn56xxp1; struct cvmx_mio_uartx_tfl_s cn58xx; struct cvmx_mio_uartx_tfl_s cn58xxp1; + struct cvmx_mio_uartx_tfl_s cn61xx; struct cvmx_mio_uartx_tfl_s cn63xx; struct cvmx_mio_uartx_tfl_s cn63xxp1; + struct cvmx_mio_uartx_tfl_s cn66xx; + struct cvmx_mio_uartx_tfl_s cn68xx; + struct cvmx_mio_uartx_tfl_s cn68xxp1; }; union cvmx_mio_uartx_tfr { @@ -2023,8 +2974,12 @@ union cvmx_mio_uartx_tfr { struct cvmx_mio_uartx_tfr_s cn56xxp1; struct cvmx_mio_uartx_tfr_s cn58xx; struct cvmx_mio_uartx_tfr_s cn58xxp1; + struct cvmx_mio_uartx_tfr_s cn61xx; struct cvmx_mio_uartx_tfr_s cn63xx; struct cvmx_mio_uartx_tfr_s cn63xxp1; + struct cvmx_mio_uartx_tfr_s cn66xx; + struct cvmx_mio_uartx_tfr_s cn68xx; + struct cvmx_mio_uartx_tfr_s cn68xxp1; }; union cvmx_mio_uartx_thr { @@ -2044,8 +2999,12 @@ union cvmx_mio_uartx_thr { struct cvmx_mio_uartx_thr_s cn56xxp1; struct cvmx_mio_uartx_thr_s cn58xx; struct cvmx_mio_uartx_thr_s cn58xxp1; + struct cvmx_mio_uartx_thr_s cn61xx; struct cvmx_mio_uartx_thr_s cn63xx; struct cvmx_mio_uartx_thr_s cn63xxp1; + struct cvmx_mio_uartx_thr_s cn66xx; + struct cvmx_mio_uartx_thr_s cn68xx; + struct cvmx_mio_uartx_thr_s cn68xxp1; }; union cvmx_mio_uartx_usr { @@ -2069,8 +3028,12 @@ union cvmx_mio_uartx_usr { struct cvmx_mio_uartx_usr_s cn56xxp1; struct cvmx_mio_uartx_usr_s cn58xx; struct cvmx_mio_uartx_usr_s cn58xxp1; + struct cvmx_mio_uartx_usr_s cn61xx; struct cvmx_mio_uartx_usr_s cn63xx; struct cvmx_mio_uartx_usr_s cn63xxp1; + struct cvmx_mio_uartx_usr_s cn66xx; + struct cvmx_mio_uartx_usr_s cn68xx; + struct cvmx_mio_uartx_usr_s cn68xxp1; }; union cvmx_mio_uart2_dlh { diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h index 700f88e31cad..4e338a4d9424 100644 --- a/arch/mips/include/asm/octeon/octeon-model.h +++ b/arch/mips/include/asm/octeon/octeon-model.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -24,14 +24,6 @@ * This file may also be available under a different license from Cavium. * Contact Cavium Networks for more information ***********************license end**************************************/ - -/* - * - * File defining different Octeon model IDs and macros to - * compare them. - * - */ - #ifndef __OCTEON_MODEL_H__ #define __OCTEON_MODEL_H__ @@ -52,6 +44,8 @@ * for internal use only, and may change without notice. */ +#define OCTEON_FAMILY_MASK 0x00ffff00 + /* Flag bits in top byte */ /* Ignores revision in model checks */ #define OM_IGNORE_REVISION 0x01000000 @@ -63,21 +57,48 @@ #define OM_IGNORE_MINOR_REVISION 0x08000000 #define OM_FLAG_MASK 0xff000000 -#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn5XXX Octeon models. */ -#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 /* Match all cn6XXX Octeon models. */ +/* Match all cn5XXX Octeon models. */ +#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 +/* Match all cn6XXX Octeon models. */ +#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 /* * CN6XXX models with new revision encoding */ +#define OCTEON_CN68XX_PASS1_0 0x000d9100 +#define OCTEON_CN68XX_PASS1_1 0x000d9101 +#define OCTEON_CN68XX_PASS1_2 0x000d9102 +#define OCTEON_CN68XX_PASS2_0 0x000d9108 + +#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN68XX_PASS1 OCTEON_CN68XX_PASS1_X +#define OCTEON_CN68XX_PASS2 OCTEON_CN68XX_PASS2_X + +#define OCTEON_CN66XX_PASS1_0 0x000d9200 +#define OCTEON_CN66XX_PASS1_2 0x000d9202 + +#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) + #define OCTEON_CN63XX_PASS1_0 0x000d9000 #define OCTEON_CN63XX_PASS1_1 0x000d9001 #define OCTEON_CN63XX_PASS1_2 0x000d9002 #define OCTEON_CN63XX_PASS2_0 0x000d9008 +#define OCTEON_CN63XX_PASS2_1 0x000d9009 +#define OCTEON_CN63XX_PASS2_2 0x000d900a #define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) #define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) #define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN61XX_PASS1_0 0x000d9300 + +#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) + /* * CN5XXX models with new revision encoding */ @@ -90,10 +111,8 @@ #define OCTEON_CN58XX_PASS2_3 0x000d030b #define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \ - | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) #define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X #define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X @@ -103,10 +122,8 @@ #define OCTEON_CN56XX_PASS2_1 0x000d0409 #define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \ - | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) #define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X #define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X @@ -125,8 +142,7 @@ #define OCTEON_CN50XX_PASS1_0 0x000d0600 #define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \ - | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) #define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X /* @@ -138,10 +154,8 @@ #define OCTEON_CN52XX_PASS2_0 0x000d0708 #define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \ - | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) #define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X #define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X @@ -174,28 +188,23 @@ #define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) #define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) #define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \ - | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) #define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) #define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) #define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \ - | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) #define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) #define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) #define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \ - | OM_CHECK_SUBMODEL) - - - -/* This matches the complete family of CN3xxx CPUs, and not subsequent models */ -#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \ - | OM_MATCH_PREVIOUS_MODELS \ - | OM_IGNORE_REVISION) +#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) +/* + * This matches the complete family of CN3xxx CPUs, and not subsequent + * models + */ +#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) #define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) #define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) @@ -221,90 +230,55 @@ #define OCTEON_38XX_FAMILY_MASK 0x00ffff00 #define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f #define OCTEON_38XX_MODEL_MASK 0x00ffff10 -#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \ - | OCTEON_38XX_MODEL_MASK) +#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK) /* CN5XXX and later use different layout of bits in the revision ID field */ #define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK #define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f #define OCTEON_58XX_MODEL_MASK 0x00ffffc0 -#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \ - | OCTEON_58XX_MODEL_MASK) -#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \ - & 0x00fffff8) +#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK) +#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8) #define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 -#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z))) - -/* NOTE: This is for internal (to this file) use only. */ -static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model, - uint32_t chip_model) -{ - uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL; - - if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) { - if (((arg_model & OM_FLAG_MASK) == rev_and_sub) && - __OCTEON_MATCH_MASK__(chip_model, arg_model, - OCTEON_38XX_MODEL_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == 0) && - __OCTEON_MATCH_MASK__(chip_model, arg_model, - OCTEON_38XX_FAMILY_REV_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) && - __OCTEON_MATCH_MASK__(chip_model, arg_model, - OCTEON_38XX_FAMILY_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_38XX_MODEL_REV_MASK)) - return 1; - if ((arg_model & OM_MATCH_PREVIOUS_MODELS) && - ((chip_model & OCTEON_38XX_MODEL_MASK) < - (arg_model & OCTEON_38XX_MODEL_MASK))) - return 1; - } else { - if (((arg_model & OM_FLAG_MASK) == rev_and_sub) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_MODEL_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == 0) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_FAMILY_REV_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_MODEL_MINOR_REV_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_FAMILY_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_MODEL_REV_MASK)) - return 1; - - if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) && - ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) - return 1; - - if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) && - ((chip_model) >= OCTEON_CN63XX_PASS1_0)) - return 1; - - if ((arg_model & OM_MATCH_PREVIOUS_MODELS) && - ((chip_model & OCTEON_58XX_MODEL_MASK) < - (arg_model & OCTEON_58XX_MODEL_MASK))) - return 1; - } - return 0; -} - /* forward declarations */ static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); static inline uint64_t cvmx_read_csr(uint64_t csr_addr); +#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z))) + +/* NOTE: This for internal use only! */ +#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \ +((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \ + ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == 0) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \ + ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \ + && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \ + )) || \ + (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \ + ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == 0) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \ + ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \ + && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \ + ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \ + && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \ + ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \ + && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \ + ))) + /* NOTE: This for internal use only!!!!! */ static inline int __octeon_is_model_runtime__(uint32_t model) { @@ -312,22 +286,25 @@ static inline int __octeon_is_model_runtime__(uint32_t model) /* * Check for special case of mismarked 3005 samples. We only - * need to check if the sub model isn't being ignored. + * need to check if the sub model isn't being ignored */ if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) { - if (cpuid == OCTEON_CN3010_PASS1 \ - && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34))) + if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34))) cpuid |= 0x10; } return __OCTEON_IS_MODEL_COMPILE__(model, cpuid); } /* - * The OCTEON_IS_MODEL macro should be used for all Octeon model - * checking done in a program. This should be kept runtime if at all - * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be - * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking - * support is required. + * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done + * in a program. + * This should be kept runtime if at all possible and must be conditionalized + * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required. + * + * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) ) + * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR() + * I.e.: + * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX) */ #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) #define OCTEON_IS_COMMON_BINARY() 1 From af866496c7752d2c0bd97fcbb4627cac72aa9a64 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:47:00 +0000 Subject: [PATCH 069/119] MIPS: Octeon: Move some Ethernet support files out of staging. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman Patchwork: https://patchwork.linux-mips.org/patch/2942/ Patchwork: https://patchwork.linux-mips.org/patch/3012/ Signed-off-by: Ralf Baechle --- arch/mips/cavium-octeon/Kconfig | 4 - arch/mips/cavium-octeon/executive/Makefile | 7 +- .../cavium-octeon/executive}/cvmx-cmd-queue.c | 8 +- .../mips/cavium-octeon/executive}/cvmx-fpa.c | 0 .../executive}/cvmx-helper-board.c | 18 +- .../executive}/cvmx-helper-fpa.c | 0 .../executive}/cvmx-helper-loop.c | 6 +- .../executive}/cvmx-helper-npi.c | 6 +- .../executive}/cvmx-helper-rgmii.c | 17 +- .../executive}/cvmx-helper-sgmii.c | 12 +- .../executive}/cvmx-helper-spi.c | 10 +- .../executive}/cvmx-helper-util.c | 16 +- .../executive}/cvmx-helper-xaui.c | 10 +- .../cavium-octeon/executive}/cvmx-helper.c | 27 ++- .../executive}/cvmx-interrupt-decodes.c | 10 +- .../executive}/cvmx-interrupt-rsl.c | 4 +- .../mips/cavium-octeon/executive}/cvmx-pko.c | 8 +- .../mips/cavium-octeon/executive}/cvmx-spi.c | 12 +- .../mips/include/asm}/octeon/cvmx-address.h | 0 .../mips/include/asm}/octeon/cvmx-asxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-cmd-queue.h | 0 .../mips/include/asm}/octeon/cvmx-config.h | 1 - .../mips/include/asm}/octeon/cvmx-dbg-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fau.h | 0 .../mips/include/asm}/octeon/cvmx-fpa-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-gmxx-defs.h | 0 .../include/asm}/octeon/cvmx-helper-board.h | 0 .../include/asm}/octeon/cvmx-helper-fpa.h | 0 .../include/asm}/octeon/cvmx-helper-loop.h | 0 .../include/asm}/octeon/cvmx-helper-npi.h | 0 .../include/asm}/octeon/cvmx-helper-rgmii.h | 0 .../include/asm}/octeon/cvmx-helper-sgmii.h | 0 .../include/asm}/octeon/cvmx-helper-spi.h | 0 .../include/asm}/octeon/cvmx-helper-util.h | 0 .../include/asm}/octeon/cvmx-helper-xaui.h | 0 .../mips/include/asm}/octeon/cvmx-helper.h | 0 .../mips/include/asm}/octeon/cvmx-ipd.h | 0 .../mips/include/asm}/octeon/cvmx-mdio.h | 0 .../mips/include/asm}/octeon/cvmx-pcsx-defs.h | 0 .../include/asm}/octeon/cvmx-pcsxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip.h | 0 .../mips/include/asm}/octeon/cvmx-pko-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pko.h | 0 .../mips/include/asm}/octeon/cvmx-pow.h | 0 .../mips/include/asm}/octeon/cvmx-scratch.h | 0 .../mips/include/asm}/octeon/cvmx-spi.h | 0 .../mips/include/asm}/octeon/cvmx-spxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-srxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-stxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-wqe.h | 0 drivers/staging/octeon/Makefile | 5 - drivers/staging/octeon/cvmx-packet.h | 65 ------- drivers/staging/octeon/cvmx-smix-defs.h | 178 ------------------ drivers/staging/octeon/ethernet-defines.h | 2 +- drivers/staging/octeon/ethernet-mdio.c | 4 +- drivers/staging/octeon/ethernet-mem.c | 2 +- drivers/staging/octeon/ethernet-rgmii.c | 4 +- drivers/staging/octeon/ethernet-rx.c | 14 +- drivers/staging/octeon/ethernet-rx.h | 2 +- drivers/staging/octeon/ethernet-sgmii.c | 4 +- drivers/staging/octeon/ethernet-spi.c | 6 +- drivers/staging/octeon/ethernet-tx.c | 12 +- drivers/staging/octeon/ethernet-xaui.c | 4 +- drivers/staging/octeon/ethernet.c | 14 +- 66 files changed, 118 insertions(+), 374 deletions(-) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-cmd-queue.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-board.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-loop.c (95%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-npi.c (96%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-rgmii.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-sgmii.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-spi.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-util.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-xaui.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-decodes.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-rsl.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-pko.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-spi.c (99%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-address.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-asxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-cmd-queue.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-config.h (99%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-dbg-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fau.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-gmxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-board.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-loop.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-npi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-rgmii.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-sgmii.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-spi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-util.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-xaui.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-ipd.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-mdio.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pow.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-scratch.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-srxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-stxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-wqe.h (100%) delete mode 100644 drivers/staging/octeon/cvmx-packet.h delete mode 100644 drivers/staging/octeon/cvmx-smix-defs.h diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index cad555ebeca3..f9e275a50d98 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -86,10 +86,6 @@ config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC -config CAVIUM_OCTEON_HELPER - def_bool y - depends on OCTEON_ETHERNET || PCI - config IOMMU_HELPER bool diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile index 7f41c5be2190..b6d6e841a984 100644 --- a/arch/mips/cavium-octeon/executive/Makefile +++ b/arch/mips/cavium-octeon/executive/Makefile @@ -10,5 +10,10 @@ # obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o +obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ + cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ + cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ + cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ + cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o -obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o +obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c similarity index 98% rename from drivers/staging/octeon/cvmx-cmd-queue.c rename to arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c index e9809d375162..132bccc66a93 100644 --- a/drivers/staging/octeon/cvmx-cmd-queue.c +++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c @@ -34,13 +34,13 @@ #include -#include "cvmx-config.h" -#include "cvmx-fpa.h" -#include "cvmx-cmd-queue.h" +#include +#include +#include #include #include -#include "cvmx-pko-defs.h" +#include /** * This application uses this pointer to access the global queue diff --git a/drivers/staging/octeon/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c similarity index 100% rename from drivers/staging/octeon/cvmx-fpa.c rename to arch/mips/cavium-octeon/executive/cvmx-fpa.c diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-board.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-board.c index 57d35dc63ddb..71590a35163b 100644 --- a/drivers/staging/octeon/cvmx-helper-board.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -34,16 +34,16 @@ #include #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" +#include -#include "cvmx-helper.h" -#include "cvmx-helper-util.h" -#include "cvmx-helper-board.h" +#include +#include +#include -#include "cvmx-gmxx-defs.h" -#include "cvmx-asxx-defs.h" +#include +#include /** * cvmx_override_board_link_get(int ipd_port) is a function @@ -493,7 +493,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_mdio_phy_reg_control_t reg_control; cvmx_mdio_phy_reg_status_t reg_status; cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; - cvmx_mdio_phy_reg_extended_status_t reg_extended_status; cvmx_mdio_phy_reg_control_1000_t reg_control_1000; reg_status.u16 = @@ -508,9 +507,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, reg_autoneg_adver.s.advert_100base_tx_full = 0; reg_autoneg_adver.s.advert_100base_tx_half = 0; if (reg_status.s.capable_extended_status) { - reg_extended_status.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_EXTENDED_STATUS); reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000); diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c similarity index 100% rename from drivers/staging/octeon/cvmx-helper-fpa.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c similarity index 95% rename from drivers/staging/octeon/cvmx-helper-loop.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-loop.c index 55a571a69529..bfbd46115e71 100644 --- a/drivers/staging/octeon/cvmx-helper-loop.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c @@ -31,10 +31,10 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" -#include "cvmx-pip-defs.h" +#include +#include /** * Probe a LOOP interface and determine the number of ports diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c similarity index 96% rename from drivers/staging/octeon/cvmx-helper-npi.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-npi.c index 7388a1e72b38..cc94cfa545b4 100644 --- a/drivers/staging/octeon/cvmx-helper-npi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c @@ -31,11 +31,11 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" +#include -#include "cvmx-pip-defs.h" +#include /** * Probe a NPI interface and determine the number of ports diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-rgmii.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c index aa2d5d7fee2b..82b21843421c 100644 --- a/drivers/staging/octeon/cvmx-helper-rgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c @@ -31,18 +31,18 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include +#include #include -#include "cvmx-gmxx-defs.h" -#include "cvmx-asxx-defs.h" -#include "cvmx-dbg-defs.h" +#include +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_asxx_enable(int block); @@ -326,6 +326,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & ~(1 << index)); + memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save)); /* Disable all queues so that TX should become idle */ for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { int queue = cvmx_pko_get_base_queue(ipd_port) + i; diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-sgmii.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c index 6214e3b6d975..464347ffd362 100644 --- a/drivers/staging/octeon/cvmx-helper-sgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -32,14 +32,14 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsx-defs.h" +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-spi.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-spi.c index 8ba6c832471e..02a444230ef7 100644 --- a/drivers/staging/octeon/cvmx-helper-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -35,12 +35,12 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index); */ #include -#include "cvmx-config.h" -#include "cvmx-spi.h" -#include "cvmx-helper.h" +#include +#include +#include -#include "cvmx-pip-defs.h" -#include "cvmx-pko-defs.h" +#include +#include /* * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-util.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-util.c index 131182bf5abb..116dea17acf5 100644 --- a/drivers/staging/octeon/cvmx-helper-util.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c @@ -32,16 +32,16 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-fpa.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-ipd.h" -#include "cvmx-spi.h" +#include +#include +#include +#include +#include -#include "cvmx-helper.h" -#include "cvmx-helper-util.h" +#include +#include #include diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-xaui.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index a11e6769e234..667a8e3cb142 100644 --- a/drivers/staging/octeon/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -33,13 +33,13 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" +#include -#include "cvmx-pko-defs.h" -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsxx-defs.h" +#include +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); diff --git a/drivers/staging/octeon/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper.c rename to arch/mips/cavium-octeon/executive/cvmx-helper.c index e9c5c836ceff..daa8c8bbcfe4 100644 --- a/drivers/staging/octeon/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -32,19 +32,19 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-fpa.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-ipd.h" -#include "cvmx-spi.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include +#include +#include +#include +#include -#include "cvmx-pip-defs.h" -#include "cvmx-smix-defs.h" -#include "cvmx-asxx-defs.h" +#include +#include +#include /** * cvmx_override_pko_queue_priority(int ipd_port, uint64_t @@ -548,7 +548,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) union cvmx_gmxx_prtx_cfg gmx_cfg; int retry_cnt; int retry_loop_cnt; - int mtu; int i; cvmx_helper_link_info_t link_info; @@ -662,10 +661,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); - mtu = - cvmx_read_csr(CVMX_GMXX_RXX_JABBER - (INDEX(FIX_IPD_OUTPORT), - INTERFACE(FIX_IPD_OUTPORT))); cvmx_write_csr(CVMX_GMXX_RXX_JABBER (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c similarity index 98% rename from drivers/staging/octeon/cvmx-interrupt-decodes.c rename to arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c index a3337e382ee9..e59d1b79f24c 100644 --- a/drivers/staging/octeon/cvmx-interrupt-decodes.c +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c @@ -34,11 +34,11 @@ #include -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsx-defs.h" -#include "cvmx-pcsxx-defs.h" -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" +#include +#include +#include +#include +#include #ifndef PRINT_ERROR #define PRINT_ERROR(format, ...) diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c similarity index 97% rename from drivers/staging/octeon/cvmx-interrupt-rsl.c rename to arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c index df50048cfbc0..bea7538ea4e9 100644 --- a/drivers/staging/octeon/cvmx-interrupt-rsl.c +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c @@ -32,8 +32,8 @@ #include -#include "cvmx-asxx-defs.h" -#include "cvmx-gmxx-defs.h" +#include +#include #ifndef PRINT_ERROR #define PRINT_ERROR(format, ...) diff --git a/drivers/staging/octeon/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c similarity index 98% rename from drivers/staging/octeon/cvmx-pko.c rename to arch/mips/cavium-octeon/executive/cvmx-pko.c index 50a2c9bd5a55..f557084b1092 100644 --- a/drivers/staging/octeon/cvmx-pko.c +++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c @@ -31,9 +31,9 @@ #include -#include "cvmx-config.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" +#include +#include +#include /** * Internal state of packet output @@ -54,7 +54,7 @@ void cvmx_pko_initialize_global(void) /* * Set the size of the PKO command buffers to an odd number of * 64bit words. This allows the normal two word send to stay - * aligned and never span a command word buffer. + * aligned and never span a comamnd word buffer. */ config.u64 = 0; config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL; diff --git a/drivers/staging/octeon/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c similarity index 99% rename from drivers/staging/octeon/cvmx-spi.c rename to arch/mips/cavium-octeon/executive/cvmx-spi.c index 82794d920cec..74afb1710cd9 100644 --- a/drivers/staging/octeon/cvmx-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c @@ -31,14 +31,14 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-pko.h" -#include "cvmx-spi.h" +#include +#include -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" -#include "cvmx-srxx-defs.h" +#include +#include +#include #define INVOKE_CB(function_p, args...) \ do { \ diff --git a/drivers/staging/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h similarity index 100% rename from drivers/staging/octeon/cvmx-address.h rename to arch/mips/include/asm/octeon/cvmx-address.h diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-asxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-asxx-defs.h diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h similarity index 100% rename from drivers/staging/octeon/cvmx-cmd-queue.h rename to arch/mips/include/asm/octeon/cvmx-cmd-queue.h diff --git a/drivers/staging/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h similarity index 99% rename from drivers/staging/octeon/cvmx-config.h rename to arch/mips/include/asm/octeon/cvmx-config.h index 078a520481cf..26835d1b43b8 100644 --- a/drivers/staging/octeon/cvmx-config.h +++ b/arch/mips/include/asm/octeon/cvmx-config.h @@ -166,4 +166,3 @@ typedef enum { #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0 #endif /* __CVMX_CONFIG_H__ */ - diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-dbg-defs.h rename to arch/mips/include/asm/octeon/cvmx-dbg-defs.h diff --git a/drivers/staging/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h similarity index 100% rename from drivers/staging/octeon/cvmx-fau.h rename to arch/mips/include/asm/octeon/cvmx-fau.h diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-fpa-defs.h rename to arch/mips/include/asm/octeon/cvmx-fpa-defs.h diff --git a/drivers/staging/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h similarity index 100% rename from drivers/staging/octeon/cvmx-fpa.h rename to arch/mips/include/asm/octeon/cvmx-fpa.h diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-gmxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-gmxx-defs.h diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-board.h rename to arch/mips/include/asm/octeon/cvmx-helper-board.h diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-fpa.h rename to arch/mips/include/asm/octeon/cvmx-helper-fpa.h diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-loop.h rename to arch/mips/include/asm/octeon/cvmx-helper-loop.h diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-npi.h rename to arch/mips/include/asm/octeon/cvmx-helper-npi.h diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-rgmii.h rename to arch/mips/include/asm/octeon/cvmx-helper-rgmii.h diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-sgmii.h rename to arch/mips/include/asm/octeon/cvmx-helper-sgmii.h diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-spi.h rename to arch/mips/include/asm/octeon/cvmx-helper-spi.h diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-util.h rename to arch/mips/include/asm/octeon/cvmx-helper-util.h diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-xaui.h rename to arch/mips/include/asm/octeon/cvmx-helper-xaui.h diff --git a/drivers/staging/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper.h rename to arch/mips/include/asm/octeon/cvmx-helper.h diff --git a/drivers/staging/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h similarity index 100% rename from drivers/staging/octeon/cvmx-ipd.h rename to arch/mips/include/asm/octeon/cvmx-ipd.h diff --git a/drivers/staging/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h similarity index 100% rename from drivers/staging/octeon/cvmx-mdio.h rename to arch/mips/include/asm/octeon/cvmx-mdio.h diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pcsx-defs.h rename to arch/mips/include/asm/octeon/cvmx-pcsx-defs.h diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pcsxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pip-defs.h rename to arch/mips/include/asm/octeon/cvmx-pip-defs.h diff --git a/drivers/staging/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h similarity index 100% rename from drivers/staging/octeon/cvmx-pip.h rename to arch/mips/include/asm/octeon/cvmx-pip.h diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pko-defs.h rename to arch/mips/include/asm/octeon/cvmx-pko-defs.h diff --git a/drivers/staging/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h similarity index 100% rename from drivers/staging/octeon/cvmx-pko.h rename to arch/mips/include/asm/octeon/cvmx-pko.h diff --git a/drivers/staging/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h similarity index 100% rename from drivers/staging/octeon/cvmx-pow.h rename to arch/mips/include/asm/octeon/cvmx-pow.h diff --git a/drivers/staging/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h similarity index 100% rename from drivers/staging/octeon/cvmx-scratch.h rename to arch/mips/include/asm/octeon/cvmx-scratch.h diff --git a/drivers/staging/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h similarity index 100% rename from drivers/staging/octeon/cvmx-spi.h rename to arch/mips/include/asm/octeon/cvmx-spi.h diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-spxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-spxx-defs.h diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-srxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-srxx-defs.h diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-stxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-stxx-defs.h diff --git a/drivers/staging/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h similarity index 100% rename from drivers/staging/octeon/cvmx-wqe.h rename to arch/mips/include/asm/octeon/cvmx-wqe.h diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile index fc850bac88c1..9012dee0c348 100644 --- a/drivers/staging/octeon/Makefile +++ b/drivers/staging/octeon/Makefile @@ -20,9 +20,4 @@ octeon-ethernet-y += ethernet-sgmii.o octeon-ethernet-y += ethernet-spi.o octeon-ethernet-y += ethernet-tx.o octeon-ethernet-y += ethernet-xaui.o -octeon-ethernet-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ - cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ - cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ - cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ - cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h deleted file mode 100644 index 62ffe78a8c81..000000000000 --- a/drivers/staging/octeon/cvmx-packet.h +++ /dev/null @@ -1,65 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Packet buffer defines. - */ - -#ifndef __CVMX_PACKET_H__ -#define __CVMX_PACKET_H__ - -/** - * This structure defines a buffer pointer on Octeon - */ -union cvmx_buf_ptr { - void *ptr; - uint64_t u64; - struct { - /* - * if set, invert the "free" pick of the overall - * packet. HW always sets this bit to 0 on inbound - * packet - */ - uint64_t i:1; - /* - * Indicates the amount to back up to get to the - * buffer start in cache lines. In most cases this is - * less than one complete cache line, so the value is - * zero. - */ - uint64_t back:4; - /* The pool that the buffer came from / goes to */ - uint64_t pool:3; - /* The size of the segment pointed to by addr (in bytes) */ - uint64_t size:16; - /* Pointer to the first byte of the data, NOT buffer */ - uint64_t addr:40; - } s; -}; - -#endif /* __CVMX_PACKET_H__ */ diff --git a/drivers/staging/octeon/cvmx-smix-defs.h b/drivers/staging/octeon/cvmx-smix-defs.h deleted file mode 100644 index 9ae45fcbe3e3..000000000000 --- a/drivers/staging/octeon/cvmx-smix-defs.h +++ /dev/null @@ -1,178 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_SMIX_DEFS_H__ -#define __CVMX_SMIX_DEFS_H__ - -#define CVMX_SMIX_CLK(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_CMD(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_EN(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_RD_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_WR_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256)) - -union cvmx_smix_clk { - uint64_t u64; - struct cvmx_smix_clk_s { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t sample_mode:1; - uint64_t reserved_14_14:1; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } s; - struct cvmx_smix_clk_cn30xx { - uint64_t reserved_21_63:43; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn30xx; - struct cvmx_smix_clk_cn30xx cn31xx; - struct cvmx_smix_clk_cn30xx cn38xx; - struct cvmx_smix_clk_cn30xx cn38xxp2; - struct cvmx_smix_clk_cn50xx { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn50xx; - struct cvmx_smix_clk_s cn52xx; - struct cvmx_smix_clk_cn50xx cn52xxp1; - struct cvmx_smix_clk_s cn56xx; - struct cvmx_smix_clk_cn50xx cn56xxp1; - struct cvmx_smix_clk_cn30xx cn58xx; - struct cvmx_smix_clk_cn30xx cn58xxp1; -}; - -union cvmx_smix_cmd { - uint64_t u64; - struct cvmx_smix_cmd_s { - uint64_t reserved_18_63:46; - uint64_t phy_op:2; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } s; - struct cvmx_smix_cmd_cn30xx { - uint64_t reserved_17_63:47; - uint64_t phy_op:1; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } cn30xx; - struct cvmx_smix_cmd_cn30xx cn31xx; - struct cvmx_smix_cmd_cn30xx cn38xx; - struct cvmx_smix_cmd_cn30xx cn38xxp2; - struct cvmx_smix_cmd_s cn50xx; - struct cvmx_smix_cmd_s cn52xx; - struct cvmx_smix_cmd_s cn52xxp1; - struct cvmx_smix_cmd_s cn56xx; - struct cvmx_smix_cmd_s cn56xxp1; - struct cvmx_smix_cmd_cn30xx cn58xx; - struct cvmx_smix_cmd_cn30xx cn58xxp1; -}; - -union cvmx_smix_en { - uint64_t u64; - struct cvmx_smix_en_s { - uint64_t reserved_1_63:63; - uint64_t en:1; - } s; - struct cvmx_smix_en_s cn30xx; - struct cvmx_smix_en_s cn31xx; - struct cvmx_smix_en_s cn38xx; - struct cvmx_smix_en_s cn38xxp2; - struct cvmx_smix_en_s cn50xx; - struct cvmx_smix_en_s cn52xx; - struct cvmx_smix_en_s cn52xxp1; - struct cvmx_smix_en_s cn56xx; - struct cvmx_smix_en_s cn56xxp1; - struct cvmx_smix_en_s cn58xx; - struct cvmx_smix_en_s cn58xxp1; -}; - -union cvmx_smix_rd_dat { - uint64_t u64; - struct cvmx_smix_rd_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_rd_dat_s cn30xx; - struct cvmx_smix_rd_dat_s cn31xx; - struct cvmx_smix_rd_dat_s cn38xx; - struct cvmx_smix_rd_dat_s cn38xxp2; - struct cvmx_smix_rd_dat_s cn50xx; - struct cvmx_smix_rd_dat_s cn52xx; - struct cvmx_smix_rd_dat_s cn52xxp1; - struct cvmx_smix_rd_dat_s cn56xx; - struct cvmx_smix_rd_dat_s cn56xxp1; - struct cvmx_smix_rd_dat_s cn58xx; - struct cvmx_smix_rd_dat_s cn58xxp1; -}; - -union cvmx_smix_wr_dat { - uint64_t u64; - struct cvmx_smix_wr_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_wr_dat_s cn30xx; - struct cvmx_smix_wr_dat_s cn31xx; - struct cvmx_smix_wr_dat_s cn38xx; - struct cvmx_smix_wr_dat_s cn38xxp2; - struct cvmx_smix_wr_dat_s cn50xx; - struct cvmx_smix_wr_dat_s cn52xx; - struct cvmx_smix_wr_dat_s cn52xxp1; - struct cvmx_smix_wr_dat_s cn56xx; - struct cvmx_smix_wr_dat_s cn56xxp1; - struct cvmx_smix_wr_dat_s cn58xx; - struct cvmx_smix_wr_dat_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h index 6a2cd50a17df..bdaec8d2ca0c 100644 --- a/drivers/staging/octeon/ethernet-defines.h +++ b/drivers/staging/octeon/ethernet-defines.h @@ -59,7 +59,7 @@ #ifndef __ETHERNET_DEFINES_H__ #define __ETHERNET_DEFINES_H__ -#include "cvmx-config.h" +#include #define OCTEON_ETHERNET_VERSION "1.9" diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index f18e3e140413..63800ba71d06 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -38,9 +38,9 @@ #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "cvmx-helper-board.h" +#include -#include "cvmx-smix-defs.h" +#include static void cvm_oct_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c index 635bb86cdcff..78b6cb743769 100644 --- a/drivers/staging/octeon/ethernet-mem.c +++ b/drivers/staging/octeon/ethernet-mem.c @@ -32,7 +32,7 @@ #include "ethernet-defines.h" -#include "cvmx-fpa.h" +#include /** * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c index c3d73f8431ae..d8f5f694ec35 100644 --- a/drivers/staging/octeon/ethernet-rgmii.c +++ b/drivers/staging/octeon/ethernet-rgmii.c @@ -37,11 +37,11 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include #include #include -#include "cvmx-gmxx-defs.h" +#include DEFINE_SPINLOCK(global_register_lock); diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c index 8b307b428791..400df8cbee53 100644 --- a/drivers/staging/octeon/ethernet-rx.c +++ b/drivers/staging/octeon/ethernet-rx.c @@ -52,14 +52,14 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" -#include "cvmx-wqe.h" -#include "cvmx-fau.h" -#include "cvmx-pow.h" -#include "cvmx-pip.h" -#include "cvmx-scratch.h" +#include +#include +#include +#include +#include +#include -#include "cvmx-gmxx-defs.h" +#include struct cvm_napi_wrapper { struct napi_struct napi; diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h index a0743b85d54e..9240c85ce241 100644 --- a/drivers/staging/octeon/ethernet-rx.h +++ b/drivers/staging/octeon/ethernet-rx.h @@ -24,7 +24,7 @@ * This file may also be available under a different license from Cavium. * Contact Cavium Networks for more information *********************************************************************/ -#include "cvmx-fau.h" +#include void cvm_oct_poll_controller(struct net_device *dev); void cvm_oct_rx_initialize(void); diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c index 5e148b512c97..d3e82430eba6 100644 --- a/drivers/staging/octeon/ethernet-sgmii.c +++ b/drivers/staging/octeon/ethernet-sgmii.c @@ -35,9 +35,9 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include -#include "cvmx-gmxx-defs.h" +#include int cvm_oct_sgmii_open(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c index d0e2d514968a..af8d62818f13 100644 --- a/drivers/staging/octeon/ethernet-spi.c +++ b/drivers/staging/octeon/ethernet-spi.c @@ -35,11 +35,11 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-spi.h" +#include #include -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" +#include +#include static int number_spi_ports; static int need_retrain[2] = { 0, 0 }; diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c index 2542c3743904..56d74dc2fbd5 100644 --- a/drivers/staging/octeon/ethernet-tx.c +++ b/drivers/staging/octeon/ethernet-tx.c @@ -47,13 +47,13 @@ #include "ethernet-tx.h" #include "ethernet-util.h" -#include "cvmx-wqe.h" -#include "cvmx-fau.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" +#include +#include +#include +#include +#include -#include "cvmx-gmxx-defs.h" +#include #define CVM_OCT_SKB_CB(skb) ((u64 *)((skb)->cb)) diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c index 861a4b3fe857..419f8c34ecdf 100644 --- a/drivers/staging/octeon/ethernet-xaui.c +++ b/drivers/staging/octeon/ethernet-xaui.c @@ -35,9 +35,9 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include -#include "cvmx-gmxx-defs.h" +#include int cvm_oct_xaui_open(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 076f86675ce6..9112cd882154 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -44,14 +44,14 @@ #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-fau.h" -#include "cvmx-ipd.h" -#include "cvmx-helper.h" +#include +#include +#include +#include +#include -#include "cvmx-gmxx-defs.h" -#include "cvmx-smix-defs.h" +#include +#include #if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \ && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS From ada11a339dc1dd5cf6724638675bfc008de99fac Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:47:03 +0000 Subject: [PATCH 070/119] MIPS: Octeon: Update bootloader board type constants. Many new types of boards exist, so lets recognize them. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman Patchwork: https://patchwork.linux-mips.org/patch/2940/ Signed-off-by: Ralf Baechle --- .../executive/cvmx-helper-board.c | 20 ++++++ arch/mips/include/asm/octeon/cvmx-bootinfo.h | 72 ++++++++++++++++++- .../include/asm/octeon/cvmx-helper-board.h | 6 ++ 3 files changed, 95 insertions(+), 3 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c index 71590a35163b..fd2015331a20 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -117,6 +117,10 @@ int cvmx_helper_board_get_mii_address(int ipd_port) case CVMX_BOARD_TYPE_EBH5200: case CVMX_BOARD_TYPE_EBH5201: case CVMX_BOARD_TYPE_EBT5200: + /* Board has 2 management ports */ + if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && + (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) + return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT; /* * Board has 4 SGMII ports. The PHYs start right after the MII * ports MII0 = 0, MII1 = 1, SGMII = 2-5. @@ -128,6 +132,9 @@ int cvmx_helper_board_get_mii_address(int ipd_port) case CVMX_BOARD_TYPE_EBH5600: case CVMX_BOARD_TYPE_EBH5601: case CVMX_BOARD_TYPE_EBH5610: + /* Board has 1 management port */ + if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) + return 0; /* * Board has 8 SGMII ports. 4 connect out, two connect * to a switch, and 2 loop to each other @@ -147,6 +154,19 @@ int cvmx_helper_board_get_mii_address(int ipd_port) return ipd_port - 16 + 1; else return -1; + case CVMX_BOARD_TYPE_NIC_XLE_10G: + case CVMX_BOARD_TYPE_NIC10E: + return -1; + case CVMX_BOARD_TYPE_NIC4E: + if (ipd_port >= 0 && ipd_port <= 3) + return (ipd_port + 0x1f) & 0x1f; + else + return -1; + case CVMX_BOARD_TYPE_NIC2E: + if (ipd_port >= 0 && ipd_port <= 1) + return ipd_port + 1; + else + return -1; case CVMX_BOARD_TYPE_BBGW_REF: /* * No PHYs are connected to Octeon, everything is diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h index d9d1668ac779..1db1dc2724cb 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h @@ -170,6 +170,22 @@ enum cvmx_board_types_enum { /* Special 'generic' board type, supports many boards */ CVMX_BOARD_TYPE_GENERIC = 28, CVMX_BOARD_TYPE_EBH5610 = 29, + CVMX_BOARD_TYPE_LANAI2_A = 30, + CVMX_BOARD_TYPE_LANAI2_U = 31, + CVMX_BOARD_TYPE_EBB5600 = 32, + CVMX_BOARD_TYPE_EBB6300 = 33, + CVMX_BOARD_TYPE_NIC_XLE_10G = 34, + CVMX_BOARD_TYPE_LANAI2_G = 35, + CVMX_BOARD_TYPE_EBT5810 = 36, + CVMX_BOARD_TYPE_NIC10E = 37, + CVMX_BOARD_TYPE_EP6300C = 38, + CVMX_BOARD_TYPE_EBB6800 = 39, + CVMX_BOARD_TYPE_NIC4E = 40, + CVMX_BOARD_TYPE_NIC2E = 41, + CVMX_BOARD_TYPE_EBB6600 = 42, + CVMX_BOARD_TYPE_REDWING = 43, + CVMX_BOARD_TYPE_NIC68_4 = 44, + CVMX_BOARD_TYPE_NIC10E_66 = 45, CVMX_BOARD_TYPE_MAX, /* @@ -187,6 +203,23 @@ enum cvmx_board_types_enum { CVMX_BOARD_TYPE_CUST_NS0216 = 10002, CVMX_BOARD_TYPE_CUST_NB5 = 10003, CVMX_BOARD_TYPE_CUST_WMR500 = 10004, + CVMX_BOARD_TYPE_CUST_ITB101 = 10005, + CVMX_BOARD_TYPE_CUST_NTE102 = 10006, + CVMX_BOARD_TYPE_CUST_AGS103 = 10007, + CVMX_BOARD_TYPE_CUST_GST104 = 10008, + CVMX_BOARD_TYPE_CUST_GCT105 = 10009, + CVMX_BOARD_TYPE_CUST_AGS106 = 10010, + CVMX_BOARD_TYPE_CUST_SGM107 = 10011, + CVMX_BOARD_TYPE_CUST_GCT108 = 10012, + CVMX_BOARD_TYPE_CUST_AGS109 = 10013, + CVMX_BOARD_TYPE_CUST_GCT110 = 10014, + CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015, + CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016, + CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017, + CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018, + CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019, + CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020, + CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021, CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, /* @@ -247,6 +280,22 @@ static inline const char *cvmx_board_type_to_string(enum ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) /* Customer boards listed here */ @@ -255,6 +304,23 @@ static inline const char *cvmx_board_type_to_string(enum ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX) /* Customer private range */ @@ -271,9 +337,9 @@ static inline const char *cvmx_chip_type_to_string(enum { switch (type) { ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL) - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED) - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE) - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX) + ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED) + ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE) + ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX) } return "Unsupported Chip"; } diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h index b465bec43553..88527fa835c9 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-board.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h @@ -44,6 +44,12 @@ typedef enum { set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */ } cvmx_helper_board_set_phy_link_flags_types_t; +/* + * Fake IPD port, the RGMII/MII interface may use different PHY, use + * this macro to return appropriate MIX address to read the PHY. + */ +#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10 + /** * cvmx_override_board_link_get(int ipd_port) is a function * pointer. It is meant to allow customization of the process of From 37d3bfd9927a8c509d31eac1036b2c3c905f8241 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:47:03 +0000 Subject: [PATCH 071/119] MIPS: Octeon: Rearrange CVMX files in preperation for device tree Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman Patchwork: https://patchwork.linux-mips.org/patch/2941/ Signed-off-by: Ralf Baechle --- .../executive/cvmx-helper-sgmii.c | 6 +- .../cavium-octeon/executive/cvmx-helper-spi.c | 10 ++ .../executive/cvmx-helper-xaui.c | 22 +++-- .../cavium-octeon/executive/cvmx-helper.c | 99 +++++++++++++++---- .../include/asm/octeon/cvmx-helper-loop.h | 1 + .../mips/include/asm/octeon/cvmx-helper-npi.h | 1 + .../include/asm/octeon/cvmx-helper-rgmii.h | 1 + .../include/asm/octeon/cvmx-helper-sgmii.h | 1 + .../mips/include/asm/octeon/cvmx-helper-spi.h | 1 + .../include/asm/octeon/cvmx-helper-xaui.h | 1 + arch/mips/include/asm/octeon/cvmx-helper.h | 1 + 11 files changed, 117 insertions(+), 27 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c index 464347ffd362..0c0bf5d30e70 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -326,6 +326,10 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) return 0; } +int __cvmx_helper_sgmii_enumerate(int interface) +{ + return 4; +} /** * Probe a SGMII interface and determine the number of ports * connected to it. The SGMII interface should still be down after @@ -347,7 +351,7 @@ int __cvmx_helper_sgmii_probe(int interface) mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); mode.s.en = 1; cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); - return 4; + return __cvmx_helper_sgmii_enumerate(interface); } /** diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c index 02a444230ef7..2830e4bdf7f3 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -51,6 +51,16 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index); #define CVMX_HELPER_SPI_TIMEOUT 10 #endif +int __cvmx_helper_spi_enumerate(int interface) +{ + if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && + cvmx_spi4000_is_present(interface)) { + return 10; + } else { + return 16; + } +} + /** * Probe a SPI interface and determine the number of ports * connected to it. The SPI interface should still be down after diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index 667a8e3cb142..1723248e987d 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -44,6 +44,19 @@ void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); + +int __cvmx_helper_xaui_enumerate(int interface) +{ + union cvmx_gmxx_hg2_control gmx_hg2_control; + + /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ + gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); + if (gmx_hg2_control.s.hg2tx_en) + return 16; + else + return 1; +} + /** * Probe a XAUI interface and determine the number of ports * connected to it. The XAUI interface should still be down @@ -56,7 +69,6 @@ void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); int __cvmx_helper_xaui_probe(int interface) { int i; - union cvmx_gmxx_hg2_control gmx_hg2_control; union cvmx_gmxx_inf_mode mode; /* @@ -90,13 +102,7 @@ int __cvmx_helper_xaui_probe(int interface) pko_mem_port_ptrs.s.pid = interface * 16 + i; cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); } - - /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ - gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); - if (gmx_hg2_control.s.hg2tx_en) - return 16; - else - return 1; + return __cvmx_helper_xaui_enumerate(interface); } /** diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index daa8c8bbcfe4..fa4963856353 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -233,6 +233,80 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port) return 0; } +/** + * This function sets the interface_port_count[interface] correctly, + * without modifying any hardware configuration. Hardware setup of + * the ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_interface_enumerate(int interface) +{ + switch (cvmx_helper_interface_get_mode(interface)) { + /* These types don't support ports to IPD/PKO */ + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + interface_port_count[interface] = 0; + break; + /* XAUI is a single high speed port */ + case CVMX_HELPER_INTERFACE_MODE_XAUI: + interface_port_count[interface] = + __cvmx_helper_xaui_enumerate(interface); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII. + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + interface_port_count[interface] = + __cvmx_helper_rgmii_enumerate(interface); + break; + /* + * SPI4 can have 1-16 ports depending on the device at + * the other end. + */ + case CVMX_HELPER_INTERFACE_MODE_SPI: + interface_port_count[interface] = + __cvmx_helper_spi_enumerate(interface); + break; + /* + * SGMII can have 1-4 ports depending on how many are + * hooked up. + */ + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + interface_port_count[interface] = + __cvmx_helper_sgmii_enumerate(interface); + break; + /* PCI target Network Packet Interface */ + case CVMX_HELPER_INTERFACE_MODE_NPI: + interface_port_count[interface] = + __cvmx_helper_npi_enumerate(interface); + break; + /* + * Special loopback only ports. These are not the same + * as other ports in loopback mode. + */ + case CVMX_HELPER_INTERFACE_MODE_LOOP: + interface_port_count[interface] = + __cvmx_helper_loop_enumerate(interface); + break; + } + + interface_port_count[interface] = + __cvmx_helper_board_interface_probe(interface, + interface_port_count + [interface]); + + /* Make sure all global variables propagate to other cores */ + CVMX_SYNCWS; + + return 0; +} + /** * This function probes an interface to determine the actual * number of hardware ports connected to it. It doesn't setup the @@ -246,6 +320,7 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port) */ int cvmx_helper_interface_probe(int interface) { + cvmx_helper_interface_enumerate(interface); /* At this stage in the game we don't want packets to be moving yet. The following probe calls should perform hardware setup needed to determine port counts. Receive must still be disabled */ @@ -253,12 +328,10 @@ int cvmx_helper_interface_probe(int interface) /* These types don't support ports to IPD/PKO */ case CVMX_HELPER_INTERFACE_MODE_DISABLED: case CVMX_HELPER_INTERFACE_MODE_PCIE: - interface_port_count[interface] = 0; break; /* XAUI is a single high speed port */ case CVMX_HELPER_INTERFACE_MODE_XAUI: - interface_port_count[interface] = - __cvmx_helper_xaui_probe(interface); + __cvmx_helper_xaui_probe(interface); break; /* * RGMII/GMII/MII are all treated about the same. Most @@ -266,16 +339,14 @@ int cvmx_helper_interface_probe(int interface) */ case CVMX_HELPER_INTERFACE_MODE_RGMII: case CVMX_HELPER_INTERFACE_MODE_GMII: - interface_port_count[interface] = - __cvmx_helper_rgmii_probe(interface); + __cvmx_helper_rgmii_probe(interface); break; /* * SPI4 can have 1-16 ports depending on the device at * the other end. */ case CVMX_HELPER_INTERFACE_MODE_SPI: - interface_port_count[interface] = - __cvmx_helper_spi_probe(interface); + __cvmx_helper_spi_probe(interface); break; /* * SGMII can have 1-4 ports depending on how many are @@ -283,29 +354,21 @@ int cvmx_helper_interface_probe(int interface) */ case CVMX_HELPER_INTERFACE_MODE_SGMII: case CVMX_HELPER_INTERFACE_MODE_PICMG: - interface_port_count[interface] = - __cvmx_helper_sgmii_probe(interface); + __cvmx_helper_sgmii_probe(interface); break; /* PCI target Network Packet Interface */ case CVMX_HELPER_INTERFACE_MODE_NPI: - interface_port_count[interface] = - __cvmx_helper_npi_probe(interface); + __cvmx_helper_npi_probe(interface); break; /* * Special loopback only ports. These are not the same * as other ports in loopback mode. */ case CVMX_HELPER_INTERFACE_MODE_LOOP: - interface_port_count[interface] = - __cvmx_helper_loop_probe(interface); + __cvmx_helper_loop_probe(interface); break; } - interface_port_count[interface] = - __cvmx_helper_board_interface_probe(interface, - interface_port_count - [interface]); - /* Make sure all global variables propagate to other cores */ CVMX_SYNCWS; diff --git a/arch/mips/include/asm/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h index e646a6ccce75..077f0e9d3b2d 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-loop.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h @@ -44,6 +44,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_loop_probe(int interface); +static inline int __cvmx_helper_loop_enumerate(int interface) {return 4; } /** * Bringup and enable a LOOP interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h index 908e7b08c214..8df4c7fafdba 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-npi.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_npi_probe(int interface); +#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe /** * Bringup and enable a NPI interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h index ea2652604a57..78295ba0050f 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h @@ -43,6 +43,7 @@ * Returns Number of RGMII/GMII/MII ports (0-4). */ extern int __cvmx_helper_rgmii_probe(int interface); +#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe /** * Put an RGMII interface in loopback mode. Internal packets sent diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h index 19b48d60857f..9a9b6c103ede 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_sgmii_probe(int interface); +extern int __cvmx_helper_sgmii_enumerate(int interface); /** * Bringup and enable a SGMII interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h index 69bac036d10e..9f1c6b968f91 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-spi.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h @@ -42,6 +42,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_spi_probe(int interface); +extern int __cvmx_helper_spi_enumerate(int interface); /** * Bringup and enable a SPI interface. After this call packet I/O diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h index 4b4db2f93cd4..f6fbc4f45b56 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_xaui_probe(int interface); +extern int __cvmx_helper_xaui_enumerate(int interface); /** * Bringup and enable a XAUI interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h index 51916f3cc40c..3169cd79f2ac 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper.h +++ b/arch/mips/include/asm/octeon/cvmx-helper.h @@ -207,6 +207,7 @@ extern int cvmx_helper_link_set(int ipd_port, * Returns Zero on success, negative on failure */ extern int cvmx_helper_interface_probe(int interface); +extern int cvmx_helper_interface_enumerate(int interface); /** * Configure a port for internal and/or external loopback. Internal loopback From 412394d10447d585ded3eab85da34381c117d782 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:47:03 +0000 Subject: [PATCH 072/119] MIPS: Octeon: Update SOC PCI related register definitions for new chips. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2986/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/octeon/cvmx-dpi-defs.h | 643 +++++ arch/mips/include/asm/octeon/cvmx-npei-defs.h | 4 +- .../include/asm/octeon/cvmx-pciercx-defs.h | 609 ++++- arch/mips/include/asm/octeon/cvmx-pemx-defs.h | 509 ++++ arch/mips/include/asm/octeon/cvmx-pexp-defs.h | 19 +- arch/mips/include/asm/octeon/cvmx-sli-defs.h | 2172 +++++++++++++++++ .../mips/include/asm/octeon/cvmx-sriox-defs.h | 1036 ++++++++ 7 files changed, 4909 insertions(+), 83 deletions(-) create mode 100644 arch/mips/include/asm/octeon/cvmx-dpi-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-pemx-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-sli-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-sriox-defs.h diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h new file mode 100644 index 000000000000..c34ad04789ce --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h @@ -0,0 +1,643 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2011 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_DPI_DEFS_H__ +#define __CVMX_DPI_DEFS_H__ + +#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull)) +#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull)) +#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull)) +#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8) +#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8) +#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull)) +#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull)) +#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull)) +#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull)) +#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull)) +#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull)) +#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull)) +#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull)) +#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull)) +#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull)) +#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull)) +#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) +#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8) +#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8) + +union cvmx_dpi_bist_status { + uint64_t u64; + struct cvmx_dpi_bist_status_s { + uint64_t reserved_47_63:17; + uint64_t bist:47; + } s; + struct cvmx_dpi_bist_status_s cn61xx; + struct cvmx_dpi_bist_status_cn63xx { + uint64_t reserved_45_63:19; + uint64_t bist:45; + } cn63xx; + struct cvmx_dpi_bist_status_cn63xxp1 { + uint64_t reserved_37_63:27; + uint64_t bist:37; + } cn63xxp1; + struct cvmx_dpi_bist_status_s cn66xx; + struct cvmx_dpi_bist_status_cn63xx cn68xx; + struct cvmx_dpi_bist_status_cn63xx cn68xxp1; +}; + +union cvmx_dpi_ctl { + uint64_t u64; + struct cvmx_dpi_ctl_s { + uint64_t reserved_2_63:62; + uint64_t clk:1; + uint64_t en:1; + } s; + struct cvmx_dpi_ctl_cn61xx { + uint64_t reserved_1_63:63; + uint64_t en:1; + } cn61xx; + struct cvmx_dpi_ctl_s cn63xx; + struct cvmx_dpi_ctl_s cn63xxp1; + struct cvmx_dpi_ctl_s cn66xx; + struct cvmx_dpi_ctl_s cn68xx; + struct cvmx_dpi_ctl_s cn68xxp1; +}; + +union cvmx_dpi_dmax_counts { + uint64_t u64; + struct cvmx_dpi_dmax_counts_s { + uint64_t reserved_39_63:25; + uint64_t fcnt:7; + uint64_t dbell:32; + } s; + struct cvmx_dpi_dmax_counts_s cn61xx; + struct cvmx_dpi_dmax_counts_s cn63xx; + struct cvmx_dpi_dmax_counts_s cn63xxp1; + struct cvmx_dpi_dmax_counts_s cn66xx; + struct cvmx_dpi_dmax_counts_s cn68xx; + struct cvmx_dpi_dmax_counts_s cn68xxp1; +}; + +union cvmx_dpi_dmax_dbell { + uint64_t u64; + struct cvmx_dpi_dmax_dbell_s { + uint64_t reserved_16_63:48; + uint64_t dbell:16; + } s; + struct cvmx_dpi_dmax_dbell_s cn61xx; + struct cvmx_dpi_dmax_dbell_s cn63xx; + struct cvmx_dpi_dmax_dbell_s cn63xxp1; + struct cvmx_dpi_dmax_dbell_s cn66xx; + struct cvmx_dpi_dmax_dbell_s cn68xx; + struct cvmx_dpi_dmax_dbell_s cn68xxp1; +}; + +union cvmx_dpi_dmax_err_rsp_status { + uint64_t u64; + struct cvmx_dpi_dmax_err_rsp_status_s { + uint64_t reserved_6_63:58; + uint64_t status:6; + } s; + struct cvmx_dpi_dmax_err_rsp_status_s cn61xx; + struct cvmx_dpi_dmax_err_rsp_status_s cn66xx; + struct cvmx_dpi_dmax_err_rsp_status_s cn68xx; + struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1; +}; + +union cvmx_dpi_dmax_ibuff_saddr { + uint64_t u64; + struct cvmx_dpi_dmax_ibuff_saddr_s { + uint64_t reserved_62_63:2; + uint64_t csize:14; + uint64_t reserved_41_47:7; + uint64_t idle:1; + uint64_t saddr:33; + uint64_t reserved_0_6:7; + } s; + struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { + uint64_t reserved_62_63:2; + uint64_t csize:14; + uint64_t reserved_41_47:7; + uint64_t idle:1; + uint64_t reserved_36_39:4; + uint64_t saddr:29; + uint64_t reserved_0_6:7; + } cn61xx; + struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx; + struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1; + struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx; + struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx; + struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1; +}; + +union cvmx_dpi_dmax_iflight { + uint64_t u64; + struct cvmx_dpi_dmax_iflight_s { + uint64_t reserved_3_63:61; + uint64_t cnt:3; + } s; + struct cvmx_dpi_dmax_iflight_s cn61xx; + struct cvmx_dpi_dmax_iflight_s cn66xx; + struct cvmx_dpi_dmax_iflight_s cn68xx; + struct cvmx_dpi_dmax_iflight_s cn68xxp1; +}; + +union cvmx_dpi_dmax_naddr { + uint64_t u64; + struct cvmx_dpi_dmax_naddr_s { + uint64_t reserved_40_63:24; + uint64_t addr:40; + } s; + struct cvmx_dpi_dmax_naddr_cn61xx { + uint64_t reserved_36_63:28; + uint64_t addr:36; + } cn61xx; + struct cvmx_dpi_dmax_naddr_cn61xx cn63xx; + struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1; + struct cvmx_dpi_dmax_naddr_cn61xx cn66xx; + struct cvmx_dpi_dmax_naddr_s cn68xx; + struct cvmx_dpi_dmax_naddr_s cn68xxp1; +}; + +union cvmx_dpi_dmax_reqbnk0 { + uint64_t u64; + struct cvmx_dpi_dmax_reqbnk0_s { + uint64_t state:64; + } s; + struct cvmx_dpi_dmax_reqbnk0_s cn61xx; + struct cvmx_dpi_dmax_reqbnk0_s cn63xx; + struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1; + struct cvmx_dpi_dmax_reqbnk0_s cn66xx; + struct cvmx_dpi_dmax_reqbnk0_s cn68xx; + struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1; +}; + +union cvmx_dpi_dmax_reqbnk1 { + uint64_t u64; + struct cvmx_dpi_dmax_reqbnk1_s { + uint64_t state:64; + } s; + struct cvmx_dpi_dmax_reqbnk1_s cn61xx; + struct cvmx_dpi_dmax_reqbnk1_s cn63xx; + struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1; + struct cvmx_dpi_dmax_reqbnk1_s cn66xx; + struct cvmx_dpi_dmax_reqbnk1_s cn68xx; + struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1; +}; + +union cvmx_dpi_dma_control { + uint64_t u64; + struct cvmx_dpi_dma_control_s { + uint64_t reserved_62_63:2; + uint64_t dici_mode:1; + uint64_t pkt_en1:1; + uint64_t ffp_dis:1; + uint64_t commit_mode:1; + uint64_t pkt_hp:1; + uint64_t pkt_en:1; + uint64_t reserved_54_55:2; + uint64_t dma_enb:6; + uint64_t reserved_34_47:14; + uint64_t b0_lend:1; + uint64_t dwb_denb:1; + uint64_t dwb_ichk:9; + uint64_t fpa_que:3; + uint64_t o_add1:1; + uint64_t o_ro:1; + uint64_t o_ns:1; + uint64_t o_es:2; + uint64_t o_mode:1; + uint64_t reserved_0_13:14; + } s; + struct cvmx_dpi_dma_control_s cn61xx; + struct cvmx_dpi_dma_control_cn63xx { + uint64_t reserved_61_63:3; + uint64_t pkt_en1:1; + uint64_t ffp_dis:1; + uint64_t commit_mode:1; + uint64_t pkt_hp:1; + uint64_t pkt_en:1; + uint64_t reserved_54_55:2; + uint64_t dma_enb:6; + uint64_t reserved_34_47:14; + uint64_t b0_lend:1; + uint64_t dwb_denb:1; + uint64_t dwb_ichk:9; + uint64_t fpa_que:3; + uint64_t o_add1:1; + uint64_t o_ro:1; + uint64_t o_ns:1; + uint64_t o_es:2; + uint64_t o_mode:1; + uint64_t reserved_0_13:14; + } cn63xx; + struct cvmx_dpi_dma_control_cn63xxp1 { + uint64_t reserved_59_63:5; + uint64_t commit_mode:1; + uint64_t pkt_hp:1; + uint64_t pkt_en:1; + uint64_t reserved_54_55:2; + uint64_t dma_enb:6; + uint64_t reserved_34_47:14; + uint64_t b0_lend:1; + uint64_t dwb_denb:1; + uint64_t dwb_ichk:9; + uint64_t fpa_que:3; + uint64_t o_add1:1; + uint64_t o_ro:1; + uint64_t o_ns:1; + uint64_t o_es:2; + uint64_t o_mode:1; + uint64_t reserved_0_13:14; + } cn63xxp1; + struct cvmx_dpi_dma_control_cn63xx cn66xx; + struct cvmx_dpi_dma_control_s cn68xx; + struct cvmx_dpi_dma_control_cn63xx cn68xxp1; +}; + +union cvmx_dpi_dma_engx_en { + uint64_t u64; + struct cvmx_dpi_dma_engx_en_s { + uint64_t reserved_8_63:56; + uint64_t qen:8; + } s; + struct cvmx_dpi_dma_engx_en_s cn61xx; + struct cvmx_dpi_dma_engx_en_s cn63xx; + struct cvmx_dpi_dma_engx_en_s cn63xxp1; + struct cvmx_dpi_dma_engx_en_s cn66xx; + struct cvmx_dpi_dma_engx_en_s cn68xx; + struct cvmx_dpi_dma_engx_en_s cn68xxp1; +}; + +union cvmx_dpi_dma_ppx_cnt { + uint64_t u64; + struct cvmx_dpi_dma_ppx_cnt_s { + uint64_t reserved_16_63:48; + uint64_t cnt:16; + } s; + struct cvmx_dpi_dma_ppx_cnt_s cn61xx; + struct cvmx_dpi_dma_ppx_cnt_s cn68xx; +}; + +union cvmx_dpi_engx_buf { + uint64_t u64; + struct cvmx_dpi_engx_buf_s { + uint64_t reserved_37_63:27; + uint64_t compblks:5; + uint64_t reserved_9_31:23; + uint64_t base:5; + uint64_t blks:4; + } s; + struct cvmx_dpi_engx_buf_s cn61xx; + struct cvmx_dpi_engx_buf_cn63xx { + uint64_t reserved_8_63:56; + uint64_t base:4; + uint64_t blks:4; + } cn63xx; + struct cvmx_dpi_engx_buf_cn63xx cn63xxp1; + struct cvmx_dpi_engx_buf_s cn66xx; + struct cvmx_dpi_engx_buf_s cn68xx; + struct cvmx_dpi_engx_buf_s cn68xxp1; +}; + +union cvmx_dpi_info_reg { + uint64_t u64; + struct cvmx_dpi_info_reg_s { + uint64_t reserved_8_63:56; + uint64_t ffp:4; + uint64_t reserved_2_3:2; + uint64_t ncb:1; + uint64_t rsl:1; + } s; + struct cvmx_dpi_info_reg_s cn61xx; + struct cvmx_dpi_info_reg_s cn63xx; + struct cvmx_dpi_info_reg_cn63xxp1 { + uint64_t reserved_2_63:62; + uint64_t ncb:1; + uint64_t rsl:1; + } cn63xxp1; + struct cvmx_dpi_info_reg_s cn66xx; + struct cvmx_dpi_info_reg_s cn68xx; + struct cvmx_dpi_info_reg_s cn68xxp1; +}; + +union cvmx_dpi_int_en { + uint64_t u64; + struct cvmx_dpi_int_en_s { + uint64_t reserved_28_63:36; + uint64_t sprt3_rst:1; + uint64_t sprt2_rst:1; + uint64_t sprt1_rst:1; + uint64_t sprt0_rst:1; + uint64_t reserved_23_23:1; + uint64_t req_badfil:1; + uint64_t req_inull:1; + uint64_t req_anull:1; + uint64_t req_undflw:1; + uint64_t req_ovrflw:1; + uint64_t req_badlen:1; + uint64_t req_badadr:1; + uint64_t dmadbo:8; + uint64_t reserved_2_7:6; + uint64_t nfovr:1; + uint64_t nderr:1; + } s; + struct cvmx_dpi_int_en_s cn61xx; + struct cvmx_dpi_int_en_cn63xx { + uint64_t reserved_26_63:38; + uint64_t sprt1_rst:1; + uint64_t sprt0_rst:1; + uint64_t reserved_23_23:1; + uint64_t req_badfil:1; + uint64_t req_inull:1; + uint64_t req_anull:1; + uint64_t req_undflw:1; + uint64_t req_ovrflw:1; + uint64_t req_badlen:1; + uint64_t req_badadr:1; + uint64_t dmadbo:8; + uint64_t reserved_2_7:6; + uint64_t nfovr:1; + uint64_t nderr:1; + } cn63xx; + struct cvmx_dpi_int_en_cn63xx cn63xxp1; + struct cvmx_dpi_int_en_s cn66xx; + struct cvmx_dpi_int_en_cn63xx cn68xx; + struct cvmx_dpi_int_en_cn63xx cn68xxp1; +}; + +union cvmx_dpi_int_reg { + uint64_t u64; + struct cvmx_dpi_int_reg_s { + uint64_t reserved_28_63:36; + uint64_t sprt3_rst:1; + uint64_t sprt2_rst:1; + uint64_t sprt1_rst:1; + uint64_t sprt0_rst:1; + uint64_t reserved_23_23:1; + uint64_t req_badfil:1; + uint64_t req_inull:1; + uint64_t req_anull:1; + uint64_t req_undflw:1; + uint64_t req_ovrflw:1; + uint64_t req_badlen:1; + uint64_t req_badadr:1; + uint64_t dmadbo:8; + uint64_t reserved_2_7:6; + uint64_t nfovr:1; + uint64_t nderr:1; + } s; + struct cvmx_dpi_int_reg_s cn61xx; + struct cvmx_dpi_int_reg_cn63xx { + uint64_t reserved_26_63:38; + uint64_t sprt1_rst:1; + uint64_t sprt0_rst:1; + uint64_t reserved_23_23:1; + uint64_t req_badfil:1; + uint64_t req_inull:1; + uint64_t req_anull:1; + uint64_t req_undflw:1; + uint64_t req_ovrflw:1; + uint64_t req_badlen:1; + uint64_t req_badadr:1; + uint64_t dmadbo:8; + uint64_t reserved_2_7:6; + uint64_t nfovr:1; + uint64_t nderr:1; + } cn63xx; + struct cvmx_dpi_int_reg_cn63xx cn63xxp1; + struct cvmx_dpi_int_reg_s cn66xx; + struct cvmx_dpi_int_reg_cn63xx cn68xx; + struct cvmx_dpi_int_reg_cn63xx cn68xxp1; +}; + +union cvmx_dpi_ncbx_cfg { + uint64_t u64; + struct cvmx_dpi_ncbx_cfg_s { + uint64_t reserved_6_63:58; + uint64_t molr:6; + } s; + struct cvmx_dpi_ncbx_cfg_s cn61xx; + struct cvmx_dpi_ncbx_cfg_s cn66xx; + struct cvmx_dpi_ncbx_cfg_s cn68xx; +}; + +union cvmx_dpi_pint_info { + uint64_t u64; + struct cvmx_dpi_pint_info_s { + uint64_t reserved_14_63:50; + uint64_t iinfo:6; + uint64_t reserved_6_7:2; + uint64_t sinfo:6; + } s; + struct cvmx_dpi_pint_info_s cn61xx; + struct cvmx_dpi_pint_info_s cn63xx; + struct cvmx_dpi_pint_info_s cn63xxp1; + struct cvmx_dpi_pint_info_s cn66xx; + struct cvmx_dpi_pint_info_s cn68xx; + struct cvmx_dpi_pint_info_s cn68xxp1; +}; + +union cvmx_dpi_pkt_err_rsp { + uint64_t u64; + struct cvmx_dpi_pkt_err_rsp_s { + uint64_t reserved_1_63:63; + uint64_t pkterr:1; + } s; + struct cvmx_dpi_pkt_err_rsp_s cn61xx; + struct cvmx_dpi_pkt_err_rsp_s cn63xx; + struct cvmx_dpi_pkt_err_rsp_s cn63xxp1; + struct cvmx_dpi_pkt_err_rsp_s cn66xx; + struct cvmx_dpi_pkt_err_rsp_s cn68xx; + struct cvmx_dpi_pkt_err_rsp_s cn68xxp1; +}; + +union cvmx_dpi_req_err_rsp { + uint64_t u64; + struct cvmx_dpi_req_err_rsp_s { + uint64_t reserved_8_63:56; + uint64_t qerr:8; + } s; + struct cvmx_dpi_req_err_rsp_s cn61xx; + struct cvmx_dpi_req_err_rsp_s cn63xx; + struct cvmx_dpi_req_err_rsp_s cn63xxp1; + struct cvmx_dpi_req_err_rsp_s cn66xx; + struct cvmx_dpi_req_err_rsp_s cn68xx; + struct cvmx_dpi_req_err_rsp_s cn68xxp1; +}; + +union cvmx_dpi_req_err_rsp_en { + uint64_t u64; + struct cvmx_dpi_req_err_rsp_en_s { + uint64_t reserved_8_63:56; + uint64_t en:8; + } s; + struct cvmx_dpi_req_err_rsp_en_s cn61xx; + struct cvmx_dpi_req_err_rsp_en_s cn63xx; + struct cvmx_dpi_req_err_rsp_en_s cn63xxp1; + struct cvmx_dpi_req_err_rsp_en_s cn66xx; + struct cvmx_dpi_req_err_rsp_en_s cn68xx; + struct cvmx_dpi_req_err_rsp_en_s cn68xxp1; +}; + +union cvmx_dpi_req_err_rst { + uint64_t u64; + struct cvmx_dpi_req_err_rst_s { + uint64_t reserved_8_63:56; + uint64_t qerr:8; + } s; + struct cvmx_dpi_req_err_rst_s cn61xx; + struct cvmx_dpi_req_err_rst_s cn63xx; + struct cvmx_dpi_req_err_rst_s cn63xxp1; + struct cvmx_dpi_req_err_rst_s cn66xx; + struct cvmx_dpi_req_err_rst_s cn68xx; + struct cvmx_dpi_req_err_rst_s cn68xxp1; +}; + +union cvmx_dpi_req_err_rst_en { + uint64_t u64; + struct cvmx_dpi_req_err_rst_en_s { + uint64_t reserved_8_63:56; + uint64_t en:8; + } s; + struct cvmx_dpi_req_err_rst_en_s cn61xx; + struct cvmx_dpi_req_err_rst_en_s cn63xx; + struct cvmx_dpi_req_err_rst_en_s cn63xxp1; + struct cvmx_dpi_req_err_rst_en_s cn66xx; + struct cvmx_dpi_req_err_rst_en_s cn68xx; + struct cvmx_dpi_req_err_rst_en_s cn68xxp1; +}; + +union cvmx_dpi_req_err_skip_comp { + uint64_t u64; + struct cvmx_dpi_req_err_skip_comp_s { + uint64_t reserved_24_63:40; + uint64_t en_rst:8; + uint64_t reserved_8_15:8; + uint64_t en_rsp:8; + } s; + struct cvmx_dpi_req_err_skip_comp_s cn61xx; + struct cvmx_dpi_req_err_skip_comp_s cn66xx; + struct cvmx_dpi_req_err_skip_comp_s cn68xx; + struct cvmx_dpi_req_err_skip_comp_s cn68xxp1; +}; + +union cvmx_dpi_req_gbl_en { + uint64_t u64; + struct cvmx_dpi_req_gbl_en_s { + uint64_t reserved_8_63:56; + uint64_t qen:8; + } s; + struct cvmx_dpi_req_gbl_en_s cn61xx; + struct cvmx_dpi_req_gbl_en_s cn63xx; + struct cvmx_dpi_req_gbl_en_s cn63xxp1; + struct cvmx_dpi_req_gbl_en_s cn66xx; + struct cvmx_dpi_req_gbl_en_s cn68xx; + struct cvmx_dpi_req_gbl_en_s cn68xxp1; +}; + +union cvmx_dpi_sli_prtx_cfg { + uint64_t u64; + struct cvmx_dpi_sli_prtx_cfg_s { + uint64_t reserved_25_63:39; + uint64_t halt:1; + uint64_t qlm_cfg:4; + uint64_t reserved_17_19:3; + uint64_t rd_mode:1; + uint64_t reserved_14_15:2; + uint64_t molr:6; + uint64_t mps_lim:1; + uint64_t reserved_5_6:2; + uint64_t mps:1; + uint64_t mrrs_lim:1; + uint64_t reserved_2_2:1; + uint64_t mrrs:2; + } s; + struct cvmx_dpi_sli_prtx_cfg_s cn61xx; + struct cvmx_dpi_sli_prtx_cfg_cn63xx { + uint64_t reserved_25_63:39; + uint64_t halt:1; + uint64_t reserved_21_23:3; + uint64_t qlm_cfg:1; + uint64_t reserved_17_19:3; + uint64_t rd_mode:1; + uint64_t reserved_14_15:2; + uint64_t molr:6; + uint64_t mps_lim:1; + uint64_t reserved_5_6:2; + uint64_t mps:1; + uint64_t mrrs_lim:1; + uint64_t reserved_2_2:1; + uint64_t mrrs:2; + } cn63xx; + struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1; + struct cvmx_dpi_sli_prtx_cfg_s cn66xx; + struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx; + struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1; +}; + +union cvmx_dpi_sli_prtx_err { + uint64_t u64; + struct cvmx_dpi_sli_prtx_err_s { + uint64_t addr:61; + uint64_t reserved_0_2:3; + } s; + struct cvmx_dpi_sli_prtx_err_s cn61xx; + struct cvmx_dpi_sli_prtx_err_s cn63xx; + struct cvmx_dpi_sli_prtx_err_s cn63xxp1; + struct cvmx_dpi_sli_prtx_err_s cn66xx; + struct cvmx_dpi_sli_prtx_err_s cn68xx; + struct cvmx_dpi_sli_prtx_err_s cn68xxp1; +}; + +union cvmx_dpi_sli_prtx_err_info { + uint64_t u64; + struct cvmx_dpi_sli_prtx_err_info_s { + uint64_t reserved_9_63:55; + uint64_t lock:1; + uint64_t reserved_5_7:3; + uint64_t type:1; + uint64_t reserved_3_3:1; + uint64_t reqq:3; + } s; + struct cvmx_dpi_sli_prtx_err_info_s cn61xx; + struct cvmx_dpi_sli_prtx_err_info_s cn63xx; + struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1; + struct cvmx_dpi_sli_prtx_err_info_s cn66xx; + struct cvmx_dpi_sli_prtx_err_info_s cn68xx; + struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h index 9899a9d2ba72..a3075f733ca5 100644 --- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -65,7 +65,7 @@ #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) -#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12) +#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12) #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h index f8cb88902efb..7b1dc8b74e5b 100644 --- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -116,8 +116,12 @@ union cvmx_pciercx_cfg000 { struct cvmx_pciercx_cfg000_s cn52xxp1; struct cvmx_pciercx_cfg000_s cn56xx; struct cvmx_pciercx_cfg000_s cn56xxp1; + struct cvmx_pciercx_cfg000_s cn61xx; struct cvmx_pciercx_cfg000_s cn63xx; struct cvmx_pciercx_cfg000_s cn63xxp1; + struct cvmx_pciercx_cfg000_s cn66xx; + struct cvmx_pciercx_cfg000_s cn68xx; + struct cvmx_pciercx_cfg000_s cn68xxp1; }; union cvmx_pciercx_cfg001 { @@ -152,8 +156,12 @@ union cvmx_pciercx_cfg001 { struct cvmx_pciercx_cfg001_s cn52xxp1; struct cvmx_pciercx_cfg001_s cn56xx; struct cvmx_pciercx_cfg001_s cn56xxp1; + struct cvmx_pciercx_cfg001_s cn61xx; struct cvmx_pciercx_cfg001_s cn63xx; struct cvmx_pciercx_cfg001_s cn63xxp1; + struct cvmx_pciercx_cfg001_s cn66xx; + struct cvmx_pciercx_cfg001_s cn68xx; + struct cvmx_pciercx_cfg001_s cn68xxp1; }; union cvmx_pciercx_cfg002 { @@ -168,8 +176,12 @@ union cvmx_pciercx_cfg002 { struct cvmx_pciercx_cfg002_s cn52xxp1; struct cvmx_pciercx_cfg002_s cn56xx; struct cvmx_pciercx_cfg002_s cn56xxp1; + struct cvmx_pciercx_cfg002_s cn61xx; struct cvmx_pciercx_cfg002_s cn63xx; struct cvmx_pciercx_cfg002_s cn63xxp1; + struct cvmx_pciercx_cfg002_s cn66xx; + struct cvmx_pciercx_cfg002_s cn68xx; + struct cvmx_pciercx_cfg002_s cn68xxp1; }; union cvmx_pciercx_cfg003 { @@ -185,8 +197,12 @@ union cvmx_pciercx_cfg003 { struct cvmx_pciercx_cfg003_s cn52xxp1; struct cvmx_pciercx_cfg003_s cn56xx; struct cvmx_pciercx_cfg003_s cn56xxp1; + struct cvmx_pciercx_cfg003_s cn61xx; struct cvmx_pciercx_cfg003_s cn63xx; struct cvmx_pciercx_cfg003_s cn63xxp1; + struct cvmx_pciercx_cfg003_s cn66xx; + struct cvmx_pciercx_cfg003_s cn68xx; + struct cvmx_pciercx_cfg003_s cn68xxp1; }; union cvmx_pciercx_cfg004 { @@ -198,8 +214,12 @@ union cvmx_pciercx_cfg004 { struct cvmx_pciercx_cfg004_s cn52xxp1; struct cvmx_pciercx_cfg004_s cn56xx; struct cvmx_pciercx_cfg004_s cn56xxp1; + struct cvmx_pciercx_cfg004_s cn61xx; struct cvmx_pciercx_cfg004_s cn63xx; struct cvmx_pciercx_cfg004_s cn63xxp1; + struct cvmx_pciercx_cfg004_s cn66xx; + struct cvmx_pciercx_cfg004_s cn68xx; + struct cvmx_pciercx_cfg004_s cn68xxp1; }; union cvmx_pciercx_cfg005 { @@ -211,8 +231,12 @@ union cvmx_pciercx_cfg005 { struct cvmx_pciercx_cfg005_s cn52xxp1; struct cvmx_pciercx_cfg005_s cn56xx; struct cvmx_pciercx_cfg005_s cn56xxp1; + struct cvmx_pciercx_cfg005_s cn61xx; struct cvmx_pciercx_cfg005_s cn63xx; struct cvmx_pciercx_cfg005_s cn63xxp1; + struct cvmx_pciercx_cfg005_s cn66xx; + struct cvmx_pciercx_cfg005_s cn68xx; + struct cvmx_pciercx_cfg005_s cn68xxp1; }; union cvmx_pciercx_cfg006 { @@ -227,8 +251,12 @@ union cvmx_pciercx_cfg006 { struct cvmx_pciercx_cfg006_s cn52xxp1; struct cvmx_pciercx_cfg006_s cn56xx; struct cvmx_pciercx_cfg006_s cn56xxp1; + struct cvmx_pciercx_cfg006_s cn61xx; struct cvmx_pciercx_cfg006_s cn63xx; struct cvmx_pciercx_cfg006_s cn63xxp1; + struct cvmx_pciercx_cfg006_s cn66xx; + struct cvmx_pciercx_cfg006_s cn68xx; + struct cvmx_pciercx_cfg006_s cn68xxp1; }; union cvmx_pciercx_cfg007 { @@ -256,8 +284,12 @@ union cvmx_pciercx_cfg007 { struct cvmx_pciercx_cfg007_s cn52xxp1; struct cvmx_pciercx_cfg007_s cn56xx; struct cvmx_pciercx_cfg007_s cn56xxp1; + struct cvmx_pciercx_cfg007_s cn61xx; struct cvmx_pciercx_cfg007_s cn63xx; struct cvmx_pciercx_cfg007_s cn63xxp1; + struct cvmx_pciercx_cfg007_s cn66xx; + struct cvmx_pciercx_cfg007_s cn68xx; + struct cvmx_pciercx_cfg007_s cn68xxp1; }; union cvmx_pciercx_cfg008 { @@ -272,8 +304,12 @@ union cvmx_pciercx_cfg008 { struct cvmx_pciercx_cfg008_s cn52xxp1; struct cvmx_pciercx_cfg008_s cn56xx; struct cvmx_pciercx_cfg008_s cn56xxp1; + struct cvmx_pciercx_cfg008_s cn61xx; struct cvmx_pciercx_cfg008_s cn63xx; struct cvmx_pciercx_cfg008_s cn63xxp1; + struct cvmx_pciercx_cfg008_s cn66xx; + struct cvmx_pciercx_cfg008_s cn68xx; + struct cvmx_pciercx_cfg008_s cn68xxp1; }; union cvmx_pciercx_cfg009 { @@ -290,8 +326,12 @@ union cvmx_pciercx_cfg009 { struct cvmx_pciercx_cfg009_s cn52xxp1; struct cvmx_pciercx_cfg009_s cn56xx; struct cvmx_pciercx_cfg009_s cn56xxp1; + struct cvmx_pciercx_cfg009_s cn61xx; struct cvmx_pciercx_cfg009_s cn63xx; struct cvmx_pciercx_cfg009_s cn63xxp1; + struct cvmx_pciercx_cfg009_s cn66xx; + struct cvmx_pciercx_cfg009_s cn68xx; + struct cvmx_pciercx_cfg009_s cn68xxp1; }; union cvmx_pciercx_cfg010 { @@ -303,8 +343,12 @@ union cvmx_pciercx_cfg010 { struct cvmx_pciercx_cfg010_s cn52xxp1; struct cvmx_pciercx_cfg010_s cn56xx; struct cvmx_pciercx_cfg010_s cn56xxp1; + struct cvmx_pciercx_cfg010_s cn61xx; struct cvmx_pciercx_cfg010_s cn63xx; struct cvmx_pciercx_cfg010_s cn63xxp1; + struct cvmx_pciercx_cfg010_s cn66xx; + struct cvmx_pciercx_cfg010_s cn68xx; + struct cvmx_pciercx_cfg010_s cn68xxp1; }; union cvmx_pciercx_cfg011 { @@ -316,8 +360,12 @@ union cvmx_pciercx_cfg011 { struct cvmx_pciercx_cfg011_s cn52xxp1; struct cvmx_pciercx_cfg011_s cn56xx; struct cvmx_pciercx_cfg011_s cn56xxp1; + struct cvmx_pciercx_cfg011_s cn61xx; struct cvmx_pciercx_cfg011_s cn63xx; struct cvmx_pciercx_cfg011_s cn63xxp1; + struct cvmx_pciercx_cfg011_s cn66xx; + struct cvmx_pciercx_cfg011_s cn68xx; + struct cvmx_pciercx_cfg011_s cn68xxp1; }; union cvmx_pciercx_cfg012 { @@ -330,8 +378,12 @@ union cvmx_pciercx_cfg012 { struct cvmx_pciercx_cfg012_s cn52xxp1; struct cvmx_pciercx_cfg012_s cn56xx; struct cvmx_pciercx_cfg012_s cn56xxp1; + struct cvmx_pciercx_cfg012_s cn61xx; struct cvmx_pciercx_cfg012_s cn63xx; struct cvmx_pciercx_cfg012_s cn63xxp1; + struct cvmx_pciercx_cfg012_s cn66xx; + struct cvmx_pciercx_cfg012_s cn68xx; + struct cvmx_pciercx_cfg012_s cn68xxp1; }; union cvmx_pciercx_cfg013 { @@ -344,8 +396,12 @@ union cvmx_pciercx_cfg013 { struct cvmx_pciercx_cfg013_s cn52xxp1; struct cvmx_pciercx_cfg013_s cn56xx; struct cvmx_pciercx_cfg013_s cn56xxp1; + struct cvmx_pciercx_cfg013_s cn61xx; struct cvmx_pciercx_cfg013_s cn63xx; struct cvmx_pciercx_cfg013_s cn63xxp1; + struct cvmx_pciercx_cfg013_s cn66xx; + struct cvmx_pciercx_cfg013_s cn68xx; + struct cvmx_pciercx_cfg013_s cn68xxp1; }; union cvmx_pciercx_cfg014 { @@ -357,8 +413,12 @@ union cvmx_pciercx_cfg014 { struct cvmx_pciercx_cfg014_s cn52xxp1; struct cvmx_pciercx_cfg014_s cn56xx; struct cvmx_pciercx_cfg014_s cn56xxp1; + struct cvmx_pciercx_cfg014_s cn61xx; struct cvmx_pciercx_cfg014_s cn63xx; struct cvmx_pciercx_cfg014_s cn63xxp1; + struct cvmx_pciercx_cfg014_s cn66xx; + struct cvmx_pciercx_cfg014_s cn68xx; + struct cvmx_pciercx_cfg014_s cn68xxp1; }; union cvmx_pciercx_cfg015 { @@ -384,8 +444,12 @@ union cvmx_pciercx_cfg015 { struct cvmx_pciercx_cfg015_s cn52xxp1; struct cvmx_pciercx_cfg015_s cn56xx; struct cvmx_pciercx_cfg015_s cn56xxp1; + struct cvmx_pciercx_cfg015_s cn61xx; struct cvmx_pciercx_cfg015_s cn63xx; struct cvmx_pciercx_cfg015_s cn63xxp1; + struct cvmx_pciercx_cfg015_s cn66xx; + struct cvmx_pciercx_cfg015_s cn68xx; + struct cvmx_pciercx_cfg015_s cn68xxp1; }; union cvmx_pciercx_cfg016 { @@ -406,8 +470,12 @@ union cvmx_pciercx_cfg016 { struct cvmx_pciercx_cfg016_s cn52xxp1; struct cvmx_pciercx_cfg016_s cn56xx; struct cvmx_pciercx_cfg016_s cn56xxp1; + struct cvmx_pciercx_cfg016_s cn61xx; struct cvmx_pciercx_cfg016_s cn63xx; struct cvmx_pciercx_cfg016_s cn63xxp1; + struct cvmx_pciercx_cfg016_s cn66xx; + struct cvmx_pciercx_cfg016_s cn68xx; + struct cvmx_pciercx_cfg016_s cn68xxp1; }; union cvmx_pciercx_cfg017 { @@ -430,14 +498,19 @@ union cvmx_pciercx_cfg017 { struct cvmx_pciercx_cfg017_s cn52xxp1; struct cvmx_pciercx_cfg017_s cn56xx; struct cvmx_pciercx_cfg017_s cn56xxp1; + struct cvmx_pciercx_cfg017_s cn61xx; struct cvmx_pciercx_cfg017_s cn63xx; struct cvmx_pciercx_cfg017_s cn63xxp1; + struct cvmx_pciercx_cfg017_s cn66xx; + struct cvmx_pciercx_cfg017_s cn68xx; + struct cvmx_pciercx_cfg017_s cn68xxp1; }; union cvmx_pciercx_cfg020 { uint32_t u32; struct cvmx_pciercx_cfg020_s { - uint32_t reserved_24_31:8; + uint32_t reserved_25_31:7; + uint32_t pvm:1; uint32_t m64:1; uint32_t mme:3; uint32_t mmc:3; @@ -445,12 +518,24 @@ union cvmx_pciercx_cfg020 { uint32_t ncp:8; uint32_t msicid:8; } s; - struct cvmx_pciercx_cfg020_s cn52xx; - struct cvmx_pciercx_cfg020_s cn52xxp1; - struct cvmx_pciercx_cfg020_s cn56xx; - struct cvmx_pciercx_cfg020_s cn56xxp1; - struct cvmx_pciercx_cfg020_s cn63xx; - struct cvmx_pciercx_cfg020_s cn63xxp1; + struct cvmx_pciercx_cfg020_cn52xx { + uint32_t reserved_24_31:8; + uint32_t m64:1; + uint32_t mme:3; + uint32_t mmc:3; + uint32_t msien:1; + uint32_t ncp:8; + uint32_t msicid:8; + } cn52xx; + struct cvmx_pciercx_cfg020_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg020_cn52xx cn56xx; + struct cvmx_pciercx_cfg020_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg020_s cn61xx; + struct cvmx_pciercx_cfg020_cn52xx cn63xx; + struct cvmx_pciercx_cfg020_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg020_cn52xx cn66xx; + struct cvmx_pciercx_cfg020_cn52xx cn68xx; + struct cvmx_pciercx_cfg020_cn52xx cn68xxp1; }; union cvmx_pciercx_cfg021 { @@ -463,8 +548,12 @@ union cvmx_pciercx_cfg021 { struct cvmx_pciercx_cfg021_s cn52xxp1; struct cvmx_pciercx_cfg021_s cn56xx; struct cvmx_pciercx_cfg021_s cn56xxp1; + struct cvmx_pciercx_cfg021_s cn61xx; struct cvmx_pciercx_cfg021_s cn63xx; struct cvmx_pciercx_cfg021_s cn63xxp1; + struct cvmx_pciercx_cfg021_s cn66xx; + struct cvmx_pciercx_cfg021_s cn68xx; + struct cvmx_pciercx_cfg021_s cn68xxp1; }; union cvmx_pciercx_cfg022 { @@ -476,8 +565,12 @@ union cvmx_pciercx_cfg022 { struct cvmx_pciercx_cfg022_s cn52xxp1; struct cvmx_pciercx_cfg022_s cn56xx; struct cvmx_pciercx_cfg022_s cn56xxp1; + struct cvmx_pciercx_cfg022_s cn61xx; struct cvmx_pciercx_cfg022_s cn63xx; struct cvmx_pciercx_cfg022_s cn63xxp1; + struct cvmx_pciercx_cfg022_s cn66xx; + struct cvmx_pciercx_cfg022_s cn68xx; + struct cvmx_pciercx_cfg022_s cn68xxp1; }; union cvmx_pciercx_cfg023 { @@ -490,8 +583,12 @@ union cvmx_pciercx_cfg023 { struct cvmx_pciercx_cfg023_s cn52xxp1; struct cvmx_pciercx_cfg023_s cn56xx; struct cvmx_pciercx_cfg023_s cn56xxp1; + struct cvmx_pciercx_cfg023_s cn61xx; struct cvmx_pciercx_cfg023_s cn63xx; struct cvmx_pciercx_cfg023_s cn63xxp1; + struct cvmx_pciercx_cfg023_s cn66xx; + struct cvmx_pciercx_cfg023_s cn68xx; + struct cvmx_pciercx_cfg023_s cn68xxp1; }; union cvmx_pciercx_cfg028 { @@ -509,8 +606,12 @@ union cvmx_pciercx_cfg028 { struct cvmx_pciercx_cfg028_s cn52xxp1; struct cvmx_pciercx_cfg028_s cn56xx; struct cvmx_pciercx_cfg028_s cn56xxp1; + struct cvmx_pciercx_cfg028_s cn61xx; struct cvmx_pciercx_cfg028_s cn63xx; struct cvmx_pciercx_cfg028_s cn63xxp1; + struct cvmx_pciercx_cfg028_s cn66xx; + struct cvmx_pciercx_cfg028_s cn68xx; + struct cvmx_pciercx_cfg028_s cn68xxp1; }; union cvmx_pciercx_cfg029 { @@ -532,8 +633,12 @@ union cvmx_pciercx_cfg029 { struct cvmx_pciercx_cfg029_s cn52xxp1; struct cvmx_pciercx_cfg029_s cn56xx; struct cvmx_pciercx_cfg029_s cn56xxp1; + struct cvmx_pciercx_cfg029_s cn61xx; struct cvmx_pciercx_cfg029_s cn63xx; struct cvmx_pciercx_cfg029_s cn63xxp1; + struct cvmx_pciercx_cfg029_s cn66xx; + struct cvmx_pciercx_cfg029_s cn68xx; + struct cvmx_pciercx_cfg029_s cn68xxp1; }; union cvmx_pciercx_cfg030 { @@ -563,13 +668,31 @@ union cvmx_pciercx_cfg030 { struct cvmx_pciercx_cfg030_s cn52xxp1; struct cvmx_pciercx_cfg030_s cn56xx; struct cvmx_pciercx_cfg030_s cn56xxp1; + struct cvmx_pciercx_cfg030_s cn61xx; struct cvmx_pciercx_cfg030_s cn63xx; struct cvmx_pciercx_cfg030_s cn63xxp1; + struct cvmx_pciercx_cfg030_s cn66xx; + struct cvmx_pciercx_cfg030_s cn68xx; + struct cvmx_pciercx_cfg030_s cn68xxp1; }; union cvmx_pciercx_cfg031 { uint32_t u32; struct cvmx_pciercx_cfg031_s { + uint32_t pnum:8; + uint32_t reserved_23_23:1; + uint32_t aspm:1; + uint32_t lbnc:1; + uint32_t dllarc:1; + uint32_t sderc:1; + uint32_t cpm:1; + uint32_t l1el:3; + uint32_t l0el:3; + uint32_t aslpms:2; + uint32_t mlw:6; + uint32_t mls:4; + } s; + struct cvmx_pciercx_cfg031_cn52xx { uint32_t pnum:8; uint32_t reserved_22_23:2; uint32_t lbnc:1; @@ -581,13 +704,16 @@ union cvmx_pciercx_cfg031 { uint32_t aslpms:2; uint32_t mlw:6; uint32_t mls:4; - } s; - struct cvmx_pciercx_cfg031_s cn52xx; - struct cvmx_pciercx_cfg031_s cn52xxp1; - struct cvmx_pciercx_cfg031_s cn56xx; - struct cvmx_pciercx_cfg031_s cn56xxp1; - struct cvmx_pciercx_cfg031_s cn63xx; - struct cvmx_pciercx_cfg031_s cn63xxp1; + } cn52xx; + struct cvmx_pciercx_cfg031_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg031_cn52xx cn56xx; + struct cvmx_pciercx_cfg031_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg031_s cn61xx; + struct cvmx_pciercx_cfg031_cn52xx cn63xx; + struct cvmx_pciercx_cfg031_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg031_s cn66xx; + struct cvmx_pciercx_cfg031_s cn68xx; + struct cvmx_pciercx_cfg031_cn52xx cn68xxp1; }; union cvmx_pciercx_cfg032 { @@ -618,8 +744,12 @@ union cvmx_pciercx_cfg032 { struct cvmx_pciercx_cfg032_s cn52xxp1; struct cvmx_pciercx_cfg032_s cn56xx; struct cvmx_pciercx_cfg032_s cn56xxp1; + struct cvmx_pciercx_cfg032_s cn61xx; struct cvmx_pciercx_cfg032_s cn63xx; struct cvmx_pciercx_cfg032_s cn63xxp1; + struct cvmx_pciercx_cfg032_s cn66xx; + struct cvmx_pciercx_cfg032_s cn68xx; + struct cvmx_pciercx_cfg032_s cn68xxp1; }; union cvmx_pciercx_cfg033 { @@ -642,8 +772,12 @@ union cvmx_pciercx_cfg033 { struct cvmx_pciercx_cfg033_s cn52xxp1; struct cvmx_pciercx_cfg033_s cn56xx; struct cvmx_pciercx_cfg033_s cn56xxp1; + struct cvmx_pciercx_cfg033_s cn61xx; struct cvmx_pciercx_cfg033_s cn63xx; struct cvmx_pciercx_cfg033_s cn63xxp1; + struct cvmx_pciercx_cfg033_s cn66xx; + struct cvmx_pciercx_cfg033_s cn68xx; + struct cvmx_pciercx_cfg033_s cn68xxp1; }; union cvmx_pciercx_cfg034 { @@ -676,8 +810,12 @@ union cvmx_pciercx_cfg034 { struct cvmx_pciercx_cfg034_s cn52xxp1; struct cvmx_pciercx_cfg034_s cn56xx; struct cvmx_pciercx_cfg034_s cn56xxp1; + struct cvmx_pciercx_cfg034_s cn61xx; struct cvmx_pciercx_cfg034_s cn63xx; struct cvmx_pciercx_cfg034_s cn63xxp1; + struct cvmx_pciercx_cfg034_s cn66xx; + struct cvmx_pciercx_cfg034_s cn68xx; + struct cvmx_pciercx_cfg034_s cn68xxp1; }; union cvmx_pciercx_cfg035 { @@ -696,8 +834,12 @@ union cvmx_pciercx_cfg035 { struct cvmx_pciercx_cfg035_s cn52xxp1; struct cvmx_pciercx_cfg035_s cn56xx; struct cvmx_pciercx_cfg035_s cn56xxp1; + struct cvmx_pciercx_cfg035_s cn61xx; struct cvmx_pciercx_cfg035_s cn63xx; struct cvmx_pciercx_cfg035_s cn63xxp1; + struct cvmx_pciercx_cfg035_s cn66xx; + struct cvmx_pciercx_cfg035_s cn68xx; + struct cvmx_pciercx_cfg035_s cn68xxp1; }; union cvmx_pciercx_cfg036 { @@ -712,38 +854,95 @@ union cvmx_pciercx_cfg036 { struct cvmx_pciercx_cfg036_s cn52xxp1; struct cvmx_pciercx_cfg036_s cn56xx; struct cvmx_pciercx_cfg036_s cn56xxp1; + struct cvmx_pciercx_cfg036_s cn61xx; struct cvmx_pciercx_cfg036_s cn63xx; struct cvmx_pciercx_cfg036_s cn63xxp1; + struct cvmx_pciercx_cfg036_s cn66xx; + struct cvmx_pciercx_cfg036_s cn68xx; + struct cvmx_pciercx_cfg036_s cn68xxp1; }; union cvmx_pciercx_cfg037 { uint32_t u32; struct cvmx_pciercx_cfg037_s { - uint32_t reserved_5_31:27; + uint32_t reserved_14_31:18; + uint32_t tph:2; + uint32_t reserved_11_11:1; + uint32_t noroprpr:1; + uint32_t atom128s:1; + uint32_t atom64s:1; + uint32_t atom32s:1; + uint32_t atom_ops:1; + uint32_t reserved_5_5:1; uint32_t ctds:1; uint32_t ctrs:4; } s; - struct cvmx_pciercx_cfg037_s cn52xx; - struct cvmx_pciercx_cfg037_s cn52xxp1; - struct cvmx_pciercx_cfg037_s cn56xx; - struct cvmx_pciercx_cfg037_s cn56xxp1; - struct cvmx_pciercx_cfg037_s cn63xx; - struct cvmx_pciercx_cfg037_s cn63xxp1; + struct cvmx_pciercx_cfg037_cn52xx { + uint32_t reserved_5_31:27; + uint32_t ctds:1; + uint32_t ctrs:4; + } cn52xx; + struct cvmx_pciercx_cfg037_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg037_cn52xx cn56xx; + struct cvmx_pciercx_cfg037_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg037_cn61xx { + uint32_t reserved_14_31:18; + uint32_t tph:2; + uint32_t reserved_11_11:1; + uint32_t noroprpr:1; + uint32_t atom128s:1; + uint32_t atom64s:1; + uint32_t atom32s:1; + uint32_t atom_ops:1; + uint32_t ari_fw:1; + uint32_t ctds:1; + uint32_t ctrs:4; + } cn61xx; + struct cvmx_pciercx_cfg037_cn52xx cn63xx; + struct cvmx_pciercx_cfg037_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg037_cn66xx { + uint32_t reserved_14_31:18; + uint32_t tph:2; + uint32_t reserved_11_11:1; + uint32_t noroprpr:1; + uint32_t atom128s:1; + uint32_t atom64s:1; + uint32_t atom32s:1; + uint32_t atom_ops:1; + uint32_t ari:1; + uint32_t ctds:1; + uint32_t ctrs:4; + } cn66xx; + struct cvmx_pciercx_cfg037_cn66xx cn68xx; + struct cvmx_pciercx_cfg037_cn66xx cn68xxp1; }; union cvmx_pciercx_cfg038 { uint32_t u32; struct cvmx_pciercx_cfg038_s { - uint32_t reserved_5_31:27; + uint32_t reserved_10_31:22; + uint32_t id0_cp:1; + uint32_t id0_rq:1; + uint32_t atom_op_eb:1; + uint32_t atom_op:1; + uint32_t ari:1; uint32_t ctd:1; uint32_t ctv:4; } s; - struct cvmx_pciercx_cfg038_s cn52xx; - struct cvmx_pciercx_cfg038_s cn52xxp1; - struct cvmx_pciercx_cfg038_s cn56xx; - struct cvmx_pciercx_cfg038_s cn56xxp1; - struct cvmx_pciercx_cfg038_s cn63xx; - struct cvmx_pciercx_cfg038_s cn63xxp1; + struct cvmx_pciercx_cfg038_cn52xx { + uint32_t reserved_5_31:27; + uint32_t ctd:1; + uint32_t ctv:4; + } cn52xx; + struct cvmx_pciercx_cfg038_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg038_cn52xx cn56xx; + struct cvmx_pciercx_cfg038_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg038_s cn61xx; + struct cvmx_pciercx_cfg038_cn52xx cn63xx; + struct cvmx_pciercx_cfg038_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg038_s cn66xx; + struct cvmx_pciercx_cfg038_s cn68xx; + struct cvmx_pciercx_cfg038_s cn68xxp1; }; union cvmx_pciercx_cfg039 { @@ -760,8 +959,12 @@ union cvmx_pciercx_cfg039 { struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; struct cvmx_pciercx_cfg039_cn52xx cn56xx; struct cvmx_pciercx_cfg039_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg039_s cn61xx; struct cvmx_pciercx_cfg039_s cn63xx; struct cvmx_pciercx_cfg039_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg039_s cn66xx; + struct cvmx_pciercx_cfg039_s cn68xx; + struct cvmx_pciercx_cfg039_s cn68xxp1; }; union cvmx_pciercx_cfg040 { @@ -785,8 +988,12 @@ union cvmx_pciercx_cfg040 { struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; struct cvmx_pciercx_cfg040_cn52xx cn56xx; struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg040_s cn61xx; struct cvmx_pciercx_cfg040_s cn63xx; struct cvmx_pciercx_cfg040_s cn63xxp1; + struct cvmx_pciercx_cfg040_s cn66xx; + struct cvmx_pciercx_cfg040_s cn68xx; + struct cvmx_pciercx_cfg040_s cn68xxp1; }; union cvmx_pciercx_cfg041 { @@ -798,8 +1005,12 @@ union cvmx_pciercx_cfg041 { struct cvmx_pciercx_cfg041_s cn52xxp1; struct cvmx_pciercx_cfg041_s cn56xx; struct cvmx_pciercx_cfg041_s cn56xxp1; + struct cvmx_pciercx_cfg041_s cn61xx; struct cvmx_pciercx_cfg041_s cn63xx; struct cvmx_pciercx_cfg041_s cn63xxp1; + struct cvmx_pciercx_cfg041_s cn66xx; + struct cvmx_pciercx_cfg041_s cn68xx; + struct cvmx_pciercx_cfg041_s cn68xxp1; }; union cvmx_pciercx_cfg042 { @@ -811,8 +1022,12 @@ union cvmx_pciercx_cfg042 { struct cvmx_pciercx_cfg042_s cn52xxp1; struct cvmx_pciercx_cfg042_s cn56xx; struct cvmx_pciercx_cfg042_s cn56xxp1; + struct cvmx_pciercx_cfg042_s cn61xx; struct cvmx_pciercx_cfg042_s cn63xx; struct cvmx_pciercx_cfg042_s cn63xxp1; + struct cvmx_pciercx_cfg042_s cn66xx; + struct cvmx_pciercx_cfg042_s cn68xx; + struct cvmx_pciercx_cfg042_s cn68xxp1; }; union cvmx_pciercx_cfg064 { @@ -826,14 +1041,20 @@ union cvmx_pciercx_cfg064 { struct cvmx_pciercx_cfg064_s cn52xxp1; struct cvmx_pciercx_cfg064_s cn56xx; struct cvmx_pciercx_cfg064_s cn56xxp1; + struct cvmx_pciercx_cfg064_s cn61xx; struct cvmx_pciercx_cfg064_s cn63xx; struct cvmx_pciercx_cfg064_s cn63xxp1; + struct cvmx_pciercx_cfg064_s cn66xx; + struct cvmx_pciercx_cfg064_s cn68xx; + struct cvmx_pciercx_cfg064_s cn68xxp1; }; union cvmx_pciercx_cfg065 { uint32_t u32; struct cvmx_pciercx_cfg065_s { - uint32_t reserved_21_31:11; + uint32_t reserved_25_31:7; + uint32_t uatombs:1; + uint32_t reserved_21_23:3; uint32_t ures:1; uint32_t ecrces:1; uint32_t mtlps:1; @@ -848,18 +1069,39 @@ union cvmx_pciercx_cfg065 { uint32_t dlpes:1; uint32_t reserved_0_3:4; } s; - struct cvmx_pciercx_cfg065_s cn52xx; - struct cvmx_pciercx_cfg065_s cn52xxp1; - struct cvmx_pciercx_cfg065_s cn56xx; - struct cvmx_pciercx_cfg065_s cn56xxp1; - struct cvmx_pciercx_cfg065_s cn63xx; - struct cvmx_pciercx_cfg065_s cn63xxp1; + struct cvmx_pciercx_cfg065_cn52xx { + uint32_t reserved_21_31:11; + uint32_t ures:1; + uint32_t ecrces:1; + uint32_t mtlps:1; + uint32_t ros:1; + uint32_t ucs:1; + uint32_t cas:1; + uint32_t cts:1; + uint32_t fcpes:1; + uint32_t ptlps:1; + uint32_t reserved_6_11:6; + uint32_t sdes:1; + uint32_t dlpes:1; + uint32_t reserved_0_3:4; + } cn52xx; + struct cvmx_pciercx_cfg065_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg065_cn52xx cn56xx; + struct cvmx_pciercx_cfg065_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg065_s cn61xx; + struct cvmx_pciercx_cfg065_cn52xx cn63xx; + struct cvmx_pciercx_cfg065_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg065_s cn66xx; + struct cvmx_pciercx_cfg065_s cn68xx; + struct cvmx_pciercx_cfg065_cn52xx cn68xxp1; }; union cvmx_pciercx_cfg066 { uint32_t u32; struct cvmx_pciercx_cfg066_s { - uint32_t reserved_21_31:11; + uint32_t reserved_25_31:7; + uint32_t uatombm:1; + uint32_t reserved_21_23:3; uint32_t urem:1; uint32_t ecrcem:1; uint32_t mtlpm:1; @@ -874,18 +1116,39 @@ union cvmx_pciercx_cfg066 { uint32_t dlpem:1; uint32_t reserved_0_3:4; } s; - struct cvmx_pciercx_cfg066_s cn52xx; - struct cvmx_pciercx_cfg066_s cn52xxp1; - struct cvmx_pciercx_cfg066_s cn56xx; - struct cvmx_pciercx_cfg066_s cn56xxp1; - struct cvmx_pciercx_cfg066_s cn63xx; - struct cvmx_pciercx_cfg066_s cn63xxp1; + struct cvmx_pciercx_cfg066_cn52xx { + uint32_t reserved_21_31:11; + uint32_t urem:1; + uint32_t ecrcem:1; + uint32_t mtlpm:1; + uint32_t rom:1; + uint32_t ucm:1; + uint32_t cam:1; + uint32_t ctm:1; + uint32_t fcpem:1; + uint32_t ptlpm:1; + uint32_t reserved_6_11:6; + uint32_t sdem:1; + uint32_t dlpem:1; + uint32_t reserved_0_3:4; + } cn52xx; + struct cvmx_pciercx_cfg066_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg066_cn52xx cn56xx; + struct cvmx_pciercx_cfg066_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg066_s cn61xx; + struct cvmx_pciercx_cfg066_cn52xx cn63xx; + struct cvmx_pciercx_cfg066_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg066_s cn66xx; + struct cvmx_pciercx_cfg066_s cn68xx; + struct cvmx_pciercx_cfg066_cn52xx cn68xxp1; }; union cvmx_pciercx_cfg067 { uint32_t u32; struct cvmx_pciercx_cfg067_s { - uint32_t reserved_21_31:11; + uint32_t reserved_25_31:7; + uint32_t uatombs:1; + uint32_t reserved_21_23:3; uint32_t ures:1; uint32_t ecrces:1; uint32_t mtlps:1; @@ -900,12 +1163,31 @@ union cvmx_pciercx_cfg067 { uint32_t dlpes:1; uint32_t reserved_0_3:4; } s; - struct cvmx_pciercx_cfg067_s cn52xx; - struct cvmx_pciercx_cfg067_s cn52xxp1; - struct cvmx_pciercx_cfg067_s cn56xx; - struct cvmx_pciercx_cfg067_s cn56xxp1; - struct cvmx_pciercx_cfg067_s cn63xx; - struct cvmx_pciercx_cfg067_s cn63xxp1; + struct cvmx_pciercx_cfg067_cn52xx { + uint32_t reserved_21_31:11; + uint32_t ures:1; + uint32_t ecrces:1; + uint32_t mtlps:1; + uint32_t ros:1; + uint32_t ucs:1; + uint32_t cas:1; + uint32_t cts:1; + uint32_t fcpes:1; + uint32_t ptlps:1; + uint32_t reserved_6_11:6; + uint32_t sdes:1; + uint32_t dlpes:1; + uint32_t reserved_0_3:4; + } cn52xx; + struct cvmx_pciercx_cfg067_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg067_cn52xx cn56xx; + struct cvmx_pciercx_cfg067_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg067_s cn61xx; + struct cvmx_pciercx_cfg067_cn52xx cn63xx; + struct cvmx_pciercx_cfg067_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg067_s cn66xx; + struct cvmx_pciercx_cfg067_s cn68xx; + struct cvmx_pciercx_cfg067_cn52xx cn68xxp1; }; union cvmx_pciercx_cfg068 { @@ -925,8 +1207,12 @@ union cvmx_pciercx_cfg068 { struct cvmx_pciercx_cfg068_s cn52xxp1; struct cvmx_pciercx_cfg068_s cn56xx; struct cvmx_pciercx_cfg068_s cn56xxp1; + struct cvmx_pciercx_cfg068_s cn61xx; struct cvmx_pciercx_cfg068_s cn63xx; struct cvmx_pciercx_cfg068_s cn63xxp1; + struct cvmx_pciercx_cfg068_s cn66xx; + struct cvmx_pciercx_cfg068_s cn68xx; + struct cvmx_pciercx_cfg068_s cn68xxp1; }; union cvmx_pciercx_cfg069 { @@ -946,8 +1232,12 @@ union cvmx_pciercx_cfg069 { struct cvmx_pciercx_cfg069_s cn52xxp1; struct cvmx_pciercx_cfg069_s cn56xx; struct cvmx_pciercx_cfg069_s cn56xxp1; + struct cvmx_pciercx_cfg069_s cn61xx; struct cvmx_pciercx_cfg069_s cn63xx; struct cvmx_pciercx_cfg069_s cn63xxp1; + struct cvmx_pciercx_cfg069_s cn66xx; + struct cvmx_pciercx_cfg069_s cn68xx; + struct cvmx_pciercx_cfg069_s cn68xxp1; }; union cvmx_pciercx_cfg070 { @@ -964,8 +1254,12 @@ union cvmx_pciercx_cfg070 { struct cvmx_pciercx_cfg070_s cn52xxp1; struct cvmx_pciercx_cfg070_s cn56xx; struct cvmx_pciercx_cfg070_s cn56xxp1; + struct cvmx_pciercx_cfg070_s cn61xx; struct cvmx_pciercx_cfg070_s cn63xx; struct cvmx_pciercx_cfg070_s cn63xxp1; + struct cvmx_pciercx_cfg070_s cn66xx; + struct cvmx_pciercx_cfg070_s cn68xx; + struct cvmx_pciercx_cfg070_s cn68xxp1; }; union cvmx_pciercx_cfg071 { @@ -977,8 +1271,12 @@ union cvmx_pciercx_cfg071 { struct cvmx_pciercx_cfg071_s cn52xxp1; struct cvmx_pciercx_cfg071_s cn56xx; struct cvmx_pciercx_cfg071_s cn56xxp1; + struct cvmx_pciercx_cfg071_s cn61xx; struct cvmx_pciercx_cfg071_s cn63xx; struct cvmx_pciercx_cfg071_s cn63xxp1; + struct cvmx_pciercx_cfg071_s cn66xx; + struct cvmx_pciercx_cfg071_s cn68xx; + struct cvmx_pciercx_cfg071_s cn68xxp1; }; union cvmx_pciercx_cfg072 { @@ -990,8 +1288,12 @@ union cvmx_pciercx_cfg072 { struct cvmx_pciercx_cfg072_s cn52xxp1; struct cvmx_pciercx_cfg072_s cn56xx; struct cvmx_pciercx_cfg072_s cn56xxp1; + struct cvmx_pciercx_cfg072_s cn61xx; struct cvmx_pciercx_cfg072_s cn63xx; struct cvmx_pciercx_cfg072_s cn63xxp1; + struct cvmx_pciercx_cfg072_s cn66xx; + struct cvmx_pciercx_cfg072_s cn68xx; + struct cvmx_pciercx_cfg072_s cn68xxp1; }; union cvmx_pciercx_cfg073 { @@ -1003,8 +1305,12 @@ union cvmx_pciercx_cfg073 { struct cvmx_pciercx_cfg073_s cn52xxp1; struct cvmx_pciercx_cfg073_s cn56xx; struct cvmx_pciercx_cfg073_s cn56xxp1; + struct cvmx_pciercx_cfg073_s cn61xx; struct cvmx_pciercx_cfg073_s cn63xx; struct cvmx_pciercx_cfg073_s cn63xxp1; + struct cvmx_pciercx_cfg073_s cn66xx; + struct cvmx_pciercx_cfg073_s cn68xx; + struct cvmx_pciercx_cfg073_s cn68xxp1; }; union cvmx_pciercx_cfg074 { @@ -1016,8 +1322,12 @@ union cvmx_pciercx_cfg074 { struct cvmx_pciercx_cfg074_s cn52xxp1; struct cvmx_pciercx_cfg074_s cn56xx; struct cvmx_pciercx_cfg074_s cn56xxp1; + struct cvmx_pciercx_cfg074_s cn61xx; struct cvmx_pciercx_cfg074_s cn63xx; struct cvmx_pciercx_cfg074_s cn63xxp1; + struct cvmx_pciercx_cfg074_s cn66xx; + struct cvmx_pciercx_cfg074_s cn68xx; + struct cvmx_pciercx_cfg074_s cn68xxp1; }; union cvmx_pciercx_cfg075 { @@ -1032,8 +1342,12 @@ union cvmx_pciercx_cfg075 { struct cvmx_pciercx_cfg075_s cn52xxp1; struct cvmx_pciercx_cfg075_s cn56xx; struct cvmx_pciercx_cfg075_s cn56xxp1; + struct cvmx_pciercx_cfg075_s cn61xx; struct cvmx_pciercx_cfg075_s cn63xx; struct cvmx_pciercx_cfg075_s cn63xxp1; + struct cvmx_pciercx_cfg075_s cn66xx; + struct cvmx_pciercx_cfg075_s cn68xx; + struct cvmx_pciercx_cfg075_s cn68xxp1; }; union cvmx_pciercx_cfg076 { @@ -1053,8 +1367,12 @@ union cvmx_pciercx_cfg076 { struct cvmx_pciercx_cfg076_s cn52xxp1; struct cvmx_pciercx_cfg076_s cn56xx; struct cvmx_pciercx_cfg076_s cn56xxp1; + struct cvmx_pciercx_cfg076_s cn61xx; struct cvmx_pciercx_cfg076_s cn63xx; struct cvmx_pciercx_cfg076_s cn63xxp1; + struct cvmx_pciercx_cfg076_s cn66xx; + struct cvmx_pciercx_cfg076_s cn68xx; + struct cvmx_pciercx_cfg076_s cn68xxp1; }; union cvmx_pciercx_cfg077 { @@ -1067,8 +1385,12 @@ union cvmx_pciercx_cfg077 { struct cvmx_pciercx_cfg077_s cn52xxp1; struct cvmx_pciercx_cfg077_s cn56xx; struct cvmx_pciercx_cfg077_s cn56xxp1; + struct cvmx_pciercx_cfg077_s cn61xx; struct cvmx_pciercx_cfg077_s cn63xx; struct cvmx_pciercx_cfg077_s cn63xxp1; + struct cvmx_pciercx_cfg077_s cn66xx; + struct cvmx_pciercx_cfg077_s cn68xx; + struct cvmx_pciercx_cfg077_s cn68xxp1; }; union cvmx_pciercx_cfg448 { @@ -1081,8 +1403,12 @@ union cvmx_pciercx_cfg448 { struct cvmx_pciercx_cfg448_s cn52xxp1; struct cvmx_pciercx_cfg448_s cn56xx; struct cvmx_pciercx_cfg448_s cn56xxp1; + struct cvmx_pciercx_cfg448_s cn61xx; struct cvmx_pciercx_cfg448_s cn63xx; struct cvmx_pciercx_cfg448_s cn63xxp1; + struct cvmx_pciercx_cfg448_s cn66xx; + struct cvmx_pciercx_cfg448_s cn68xx; + struct cvmx_pciercx_cfg448_s cn68xxp1; }; union cvmx_pciercx_cfg449 { @@ -1094,8 +1420,12 @@ union cvmx_pciercx_cfg449 { struct cvmx_pciercx_cfg449_s cn52xxp1; struct cvmx_pciercx_cfg449_s cn56xx; struct cvmx_pciercx_cfg449_s cn56xxp1; + struct cvmx_pciercx_cfg449_s cn61xx; struct cvmx_pciercx_cfg449_s cn63xx; struct cvmx_pciercx_cfg449_s cn63xxp1; + struct cvmx_pciercx_cfg449_s cn66xx; + struct cvmx_pciercx_cfg449_s cn68xx; + struct cvmx_pciercx_cfg449_s cn68xxp1; }; union cvmx_pciercx_cfg450 { @@ -1112,26 +1442,42 @@ union cvmx_pciercx_cfg450 { struct cvmx_pciercx_cfg450_s cn52xxp1; struct cvmx_pciercx_cfg450_s cn56xx; struct cvmx_pciercx_cfg450_s cn56xxp1; + struct cvmx_pciercx_cfg450_s cn61xx; struct cvmx_pciercx_cfg450_s cn63xx; struct cvmx_pciercx_cfg450_s cn63xxp1; + struct cvmx_pciercx_cfg450_s cn66xx; + struct cvmx_pciercx_cfg450_s cn68xx; + struct cvmx_pciercx_cfg450_s cn68xxp1; }; union cvmx_pciercx_cfg451 { uint32_t u32; struct cvmx_pciercx_cfg451_s { - uint32_t reserved_30_31:2; + uint32_t reserved_31_31:1; + uint32_t easpml1:1; uint32_t l1el:3; uint32_t l0el:3; uint32_t n_fts_cc:8; uint32_t n_fts:8; uint32_t ack_freq:8; } s; - struct cvmx_pciercx_cfg451_s cn52xx; - struct cvmx_pciercx_cfg451_s cn52xxp1; - struct cvmx_pciercx_cfg451_s cn56xx; - struct cvmx_pciercx_cfg451_s cn56xxp1; - struct cvmx_pciercx_cfg451_s cn63xx; - struct cvmx_pciercx_cfg451_s cn63xxp1; + struct cvmx_pciercx_cfg451_cn52xx { + uint32_t reserved_30_31:2; + uint32_t l1el:3; + uint32_t l0el:3; + uint32_t n_fts_cc:8; + uint32_t n_fts:8; + uint32_t ack_freq:8; + } cn52xx; + struct cvmx_pciercx_cfg451_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg451_cn52xx cn56xx; + struct cvmx_pciercx_cfg451_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg451_s cn61xx; + struct cvmx_pciercx_cfg451_cn52xx cn63xx; + struct cvmx_pciercx_cfg451_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg451_s cn66xx; + struct cvmx_pciercx_cfg451_s cn68xx; + struct cvmx_pciercx_cfg451_s cn68xxp1; }; union cvmx_pciercx_cfg452 { @@ -1155,8 +1501,24 @@ union cvmx_pciercx_cfg452 { struct cvmx_pciercx_cfg452_s cn52xxp1; struct cvmx_pciercx_cfg452_s cn56xx; struct cvmx_pciercx_cfg452_s cn56xxp1; + struct cvmx_pciercx_cfg452_cn61xx { + uint32_t reserved_22_31:10; + uint32_t lme:6; + uint32_t reserved_8_15:8; + uint32_t flm:1; + uint32_t reserved_6_6:1; + uint32_t dllle:1; + uint32_t reserved_4_4:1; + uint32_t ra:1; + uint32_t le:1; + uint32_t sd:1; + uint32_t omr:1; + } cn61xx; struct cvmx_pciercx_cfg452_s cn63xx; struct cvmx_pciercx_cfg452_s cn63xxp1; + struct cvmx_pciercx_cfg452_cn61xx cn66xx; + struct cvmx_pciercx_cfg452_cn61xx cn68xx; + struct cvmx_pciercx_cfg452_cn61xx cn68xxp1; }; union cvmx_pciercx_cfg453 { @@ -1172,13 +1534,26 @@ union cvmx_pciercx_cfg453 { struct cvmx_pciercx_cfg453_s cn52xxp1; struct cvmx_pciercx_cfg453_s cn56xx; struct cvmx_pciercx_cfg453_s cn56xxp1; + struct cvmx_pciercx_cfg453_s cn61xx; struct cvmx_pciercx_cfg453_s cn63xx; struct cvmx_pciercx_cfg453_s cn63xxp1; + struct cvmx_pciercx_cfg453_s cn66xx; + struct cvmx_pciercx_cfg453_s cn68xx; + struct cvmx_pciercx_cfg453_s cn68xxp1; }; union cvmx_pciercx_cfg454 { uint32_t u32; struct cvmx_pciercx_cfg454_s { + uint32_t cx_nfunc:3; + uint32_t tmfcwt:5; + uint32_t tmanlt:5; + uint32_t tmrt:5; + uint32_t reserved_11_13:3; + uint32_t nskps:3; + uint32_t reserved_0_7:8; + } s; + struct cvmx_pciercx_cfg454_cn52xx { uint32_t reserved_29_31:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; @@ -1187,13 +1562,23 @@ union cvmx_pciercx_cfg454 { uint32_t nskps:3; uint32_t reserved_4_7:4; uint32_t ntss:4; - } s; - struct cvmx_pciercx_cfg454_s cn52xx; - struct cvmx_pciercx_cfg454_s cn52xxp1; - struct cvmx_pciercx_cfg454_s cn56xx; - struct cvmx_pciercx_cfg454_s cn56xxp1; - struct cvmx_pciercx_cfg454_s cn63xx; - struct cvmx_pciercx_cfg454_s cn63xxp1; + } cn52xx; + struct cvmx_pciercx_cfg454_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg454_cn52xx cn56xx; + struct cvmx_pciercx_cfg454_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg454_cn61xx { + uint32_t cx_nfunc:3; + uint32_t tmfcwt:5; + uint32_t tmanlt:5; + uint32_t tmrt:5; + uint32_t reserved_8_13:6; + uint32_t mfuncn:8; + } cn61xx; + struct cvmx_pciercx_cfg454_cn52xx cn63xx; + struct cvmx_pciercx_cfg454_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg454_cn61xx cn66xx; + struct cvmx_pciercx_cfg454_cn61xx cn68xx; + struct cvmx_pciercx_cfg454_cn52xx cn68xxp1; }; union cvmx_pciercx_cfg455 { @@ -1223,23 +1608,37 @@ union cvmx_pciercx_cfg455 { struct cvmx_pciercx_cfg455_s cn52xxp1; struct cvmx_pciercx_cfg455_s cn56xx; struct cvmx_pciercx_cfg455_s cn56xxp1; + struct cvmx_pciercx_cfg455_s cn61xx; struct cvmx_pciercx_cfg455_s cn63xx; struct cvmx_pciercx_cfg455_s cn63xxp1; + struct cvmx_pciercx_cfg455_s cn66xx; + struct cvmx_pciercx_cfg455_s cn68xx; + struct cvmx_pciercx_cfg455_s cn68xxp1; }; union cvmx_pciercx_cfg456 { uint32_t u32; struct cvmx_pciercx_cfg456_s { - uint32_t reserved_2_31:30; + uint32_t reserved_4_31:28; + uint32_t m_handle_flush:1; + uint32_t m_dabort_4ucpl:1; uint32_t m_vend1_drp:1; uint32_t m_vend0_drp:1; } s; - struct cvmx_pciercx_cfg456_s cn52xx; - struct cvmx_pciercx_cfg456_s cn52xxp1; - struct cvmx_pciercx_cfg456_s cn56xx; - struct cvmx_pciercx_cfg456_s cn56xxp1; - struct cvmx_pciercx_cfg456_s cn63xx; - struct cvmx_pciercx_cfg456_s cn63xxp1; + struct cvmx_pciercx_cfg456_cn52xx { + uint32_t reserved_2_31:30; + uint32_t m_vend1_drp:1; + uint32_t m_vend0_drp:1; + } cn52xx; + struct cvmx_pciercx_cfg456_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg456_cn52xx cn56xx; + struct cvmx_pciercx_cfg456_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg456_s cn61xx; + struct cvmx_pciercx_cfg456_cn52xx cn63xx; + struct cvmx_pciercx_cfg456_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg456_s cn66xx; + struct cvmx_pciercx_cfg456_s cn68xx; + struct cvmx_pciercx_cfg456_cn52xx cn68xxp1; }; union cvmx_pciercx_cfg458 { @@ -1251,8 +1650,12 @@ union cvmx_pciercx_cfg458 { struct cvmx_pciercx_cfg458_s cn52xxp1; struct cvmx_pciercx_cfg458_s cn56xx; struct cvmx_pciercx_cfg458_s cn56xxp1; + struct cvmx_pciercx_cfg458_s cn61xx; struct cvmx_pciercx_cfg458_s cn63xx; struct cvmx_pciercx_cfg458_s cn63xxp1; + struct cvmx_pciercx_cfg458_s cn66xx; + struct cvmx_pciercx_cfg458_s cn68xx; + struct cvmx_pciercx_cfg458_s cn68xxp1; }; union cvmx_pciercx_cfg459 { @@ -1264,8 +1667,12 @@ union cvmx_pciercx_cfg459 { struct cvmx_pciercx_cfg459_s cn52xxp1; struct cvmx_pciercx_cfg459_s cn56xx; struct cvmx_pciercx_cfg459_s cn56xxp1; + struct cvmx_pciercx_cfg459_s cn61xx; struct cvmx_pciercx_cfg459_s cn63xx; struct cvmx_pciercx_cfg459_s cn63xxp1; + struct cvmx_pciercx_cfg459_s cn66xx; + struct cvmx_pciercx_cfg459_s cn68xx; + struct cvmx_pciercx_cfg459_s cn68xxp1; }; union cvmx_pciercx_cfg460 { @@ -1279,8 +1686,12 @@ union cvmx_pciercx_cfg460 { struct cvmx_pciercx_cfg460_s cn52xxp1; struct cvmx_pciercx_cfg460_s cn56xx; struct cvmx_pciercx_cfg460_s cn56xxp1; + struct cvmx_pciercx_cfg460_s cn61xx; struct cvmx_pciercx_cfg460_s cn63xx; struct cvmx_pciercx_cfg460_s cn63xxp1; + struct cvmx_pciercx_cfg460_s cn66xx; + struct cvmx_pciercx_cfg460_s cn68xx; + struct cvmx_pciercx_cfg460_s cn68xxp1; }; union cvmx_pciercx_cfg461 { @@ -1294,8 +1705,12 @@ union cvmx_pciercx_cfg461 { struct cvmx_pciercx_cfg461_s cn52xxp1; struct cvmx_pciercx_cfg461_s cn56xx; struct cvmx_pciercx_cfg461_s cn56xxp1; + struct cvmx_pciercx_cfg461_s cn61xx; struct cvmx_pciercx_cfg461_s cn63xx; struct cvmx_pciercx_cfg461_s cn63xxp1; + struct cvmx_pciercx_cfg461_s cn66xx; + struct cvmx_pciercx_cfg461_s cn68xx; + struct cvmx_pciercx_cfg461_s cn68xxp1; }; union cvmx_pciercx_cfg462 { @@ -1309,8 +1724,12 @@ union cvmx_pciercx_cfg462 { struct cvmx_pciercx_cfg462_s cn52xxp1; struct cvmx_pciercx_cfg462_s cn56xx; struct cvmx_pciercx_cfg462_s cn56xxp1; + struct cvmx_pciercx_cfg462_s cn61xx; struct cvmx_pciercx_cfg462_s cn63xx; struct cvmx_pciercx_cfg462_s cn63xxp1; + struct cvmx_pciercx_cfg462_s cn66xx; + struct cvmx_pciercx_cfg462_s cn68xx; + struct cvmx_pciercx_cfg462_s cn68xxp1; }; union cvmx_pciercx_cfg463 { @@ -1325,8 +1744,12 @@ union cvmx_pciercx_cfg463 { struct cvmx_pciercx_cfg463_s cn52xxp1; struct cvmx_pciercx_cfg463_s cn56xx; struct cvmx_pciercx_cfg463_s cn56xxp1; + struct cvmx_pciercx_cfg463_s cn61xx; struct cvmx_pciercx_cfg463_s cn63xx; struct cvmx_pciercx_cfg463_s cn63xxp1; + struct cvmx_pciercx_cfg463_s cn66xx; + struct cvmx_pciercx_cfg463_s cn68xx; + struct cvmx_pciercx_cfg463_s cn68xxp1; }; union cvmx_pciercx_cfg464 { @@ -1341,8 +1764,12 @@ union cvmx_pciercx_cfg464 { struct cvmx_pciercx_cfg464_s cn52xxp1; struct cvmx_pciercx_cfg464_s cn56xx; struct cvmx_pciercx_cfg464_s cn56xxp1; + struct cvmx_pciercx_cfg464_s cn61xx; struct cvmx_pciercx_cfg464_s cn63xx; struct cvmx_pciercx_cfg464_s cn63xxp1; + struct cvmx_pciercx_cfg464_s cn66xx; + struct cvmx_pciercx_cfg464_s cn68xx; + struct cvmx_pciercx_cfg464_s cn68xxp1; }; union cvmx_pciercx_cfg465 { @@ -1357,8 +1784,12 @@ union cvmx_pciercx_cfg465 { struct cvmx_pciercx_cfg465_s cn52xxp1; struct cvmx_pciercx_cfg465_s cn56xx; struct cvmx_pciercx_cfg465_s cn56xxp1; + struct cvmx_pciercx_cfg465_s cn61xx; struct cvmx_pciercx_cfg465_s cn63xx; struct cvmx_pciercx_cfg465_s cn63xxp1; + struct cvmx_pciercx_cfg465_s cn66xx; + struct cvmx_pciercx_cfg465_s cn68xx; + struct cvmx_pciercx_cfg465_s cn68xxp1; }; union cvmx_pciercx_cfg466 { @@ -1376,8 +1807,12 @@ union cvmx_pciercx_cfg466 { struct cvmx_pciercx_cfg466_s cn52xxp1; struct cvmx_pciercx_cfg466_s cn56xx; struct cvmx_pciercx_cfg466_s cn56xxp1; + struct cvmx_pciercx_cfg466_s cn61xx; struct cvmx_pciercx_cfg466_s cn63xx; struct cvmx_pciercx_cfg466_s cn63xxp1; + struct cvmx_pciercx_cfg466_s cn66xx; + struct cvmx_pciercx_cfg466_s cn68xx; + struct cvmx_pciercx_cfg466_s cn68xxp1; }; union cvmx_pciercx_cfg467 { @@ -1393,8 +1828,12 @@ union cvmx_pciercx_cfg467 { struct cvmx_pciercx_cfg467_s cn52xxp1; struct cvmx_pciercx_cfg467_s cn56xx; struct cvmx_pciercx_cfg467_s cn56xxp1; + struct cvmx_pciercx_cfg467_s cn61xx; struct cvmx_pciercx_cfg467_s cn63xx; struct cvmx_pciercx_cfg467_s cn63xxp1; + struct cvmx_pciercx_cfg467_s cn66xx; + struct cvmx_pciercx_cfg467_s cn68xx; + struct cvmx_pciercx_cfg467_s cn68xxp1; }; union cvmx_pciercx_cfg468 { @@ -1410,8 +1849,12 @@ union cvmx_pciercx_cfg468 { struct cvmx_pciercx_cfg468_s cn52xxp1; struct cvmx_pciercx_cfg468_s cn56xx; struct cvmx_pciercx_cfg468_s cn56xxp1; + struct cvmx_pciercx_cfg468_s cn61xx; struct cvmx_pciercx_cfg468_s cn63xx; struct cvmx_pciercx_cfg468_s cn63xxp1; + struct cvmx_pciercx_cfg468_s cn66xx; + struct cvmx_pciercx_cfg468_s cn68xx; + struct cvmx_pciercx_cfg468_s cn68xxp1; }; union cvmx_pciercx_cfg490 { @@ -1426,8 +1869,12 @@ union cvmx_pciercx_cfg490 { struct cvmx_pciercx_cfg490_s cn52xxp1; struct cvmx_pciercx_cfg490_s cn56xx; struct cvmx_pciercx_cfg490_s cn56xxp1; + struct cvmx_pciercx_cfg490_s cn61xx; struct cvmx_pciercx_cfg490_s cn63xx; struct cvmx_pciercx_cfg490_s cn63xxp1; + struct cvmx_pciercx_cfg490_s cn66xx; + struct cvmx_pciercx_cfg490_s cn68xx; + struct cvmx_pciercx_cfg490_s cn68xxp1; }; union cvmx_pciercx_cfg491 { @@ -1442,8 +1889,12 @@ union cvmx_pciercx_cfg491 { struct cvmx_pciercx_cfg491_s cn52xxp1; struct cvmx_pciercx_cfg491_s cn56xx; struct cvmx_pciercx_cfg491_s cn56xxp1; + struct cvmx_pciercx_cfg491_s cn61xx; struct cvmx_pciercx_cfg491_s cn63xx; struct cvmx_pciercx_cfg491_s cn63xxp1; + struct cvmx_pciercx_cfg491_s cn66xx; + struct cvmx_pciercx_cfg491_s cn68xx; + struct cvmx_pciercx_cfg491_s cn68xxp1; }; union cvmx_pciercx_cfg492 { @@ -1458,8 +1909,12 @@ union cvmx_pciercx_cfg492 { struct cvmx_pciercx_cfg492_s cn52xxp1; struct cvmx_pciercx_cfg492_s cn56xx; struct cvmx_pciercx_cfg492_s cn56xxp1; + struct cvmx_pciercx_cfg492_s cn61xx; struct cvmx_pciercx_cfg492_s cn63xx; struct cvmx_pciercx_cfg492_s cn63xxp1; + struct cvmx_pciercx_cfg492_s cn66xx; + struct cvmx_pciercx_cfg492_s cn68xx; + struct cvmx_pciercx_cfg492_s cn68xxp1; }; union cvmx_pciercx_cfg515 { @@ -1473,8 +1928,12 @@ union cvmx_pciercx_cfg515 { uint32_t le:9; uint32_t n_fts:8; } s; + struct cvmx_pciercx_cfg515_s cn61xx; struct cvmx_pciercx_cfg515_s cn63xx; struct cvmx_pciercx_cfg515_s cn63xxp1; + struct cvmx_pciercx_cfg515_s cn66xx; + struct cvmx_pciercx_cfg515_s cn68xx; + struct cvmx_pciercx_cfg515_s cn68xxp1; }; union cvmx_pciercx_cfg516 { @@ -1486,8 +1945,12 @@ union cvmx_pciercx_cfg516 { struct cvmx_pciercx_cfg516_s cn52xxp1; struct cvmx_pciercx_cfg516_s cn56xx; struct cvmx_pciercx_cfg516_s cn56xxp1; + struct cvmx_pciercx_cfg516_s cn61xx; struct cvmx_pciercx_cfg516_s cn63xx; struct cvmx_pciercx_cfg516_s cn63xxp1; + struct cvmx_pciercx_cfg516_s cn66xx; + struct cvmx_pciercx_cfg516_s cn68xx; + struct cvmx_pciercx_cfg516_s cn68xxp1; }; union cvmx_pciercx_cfg517 { @@ -1499,8 +1962,12 @@ union cvmx_pciercx_cfg517 { struct cvmx_pciercx_cfg517_s cn52xxp1; struct cvmx_pciercx_cfg517_s cn56xx; struct cvmx_pciercx_cfg517_s cn56xxp1; + struct cvmx_pciercx_cfg517_s cn61xx; struct cvmx_pciercx_cfg517_s cn63xx; struct cvmx_pciercx_cfg517_s cn63xxp1; + struct cvmx_pciercx_cfg517_s cn66xx; + struct cvmx_pciercx_cfg517_s cn68xx; + struct cvmx_pciercx_cfg517_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h new file mode 100644 index 000000000000..be189a2585e0 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h @@ -0,0 +1,509 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2011 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PEMX_DEFS_H__ +#define __CVMX_PEMX_DEFS_H__ + +#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8) +#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16) +#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16) +#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull) + +union cvmx_pemx_bar1_indexx { + uint64_t u64; + struct cvmx_pemx_bar1_indexx_s { + uint64_t reserved_20_63:44; + uint64_t addr_idx:16; + uint64_t ca:1; + uint64_t end_swp:2; + uint64_t addr_v:1; + } s; + struct cvmx_pemx_bar1_indexx_s cn61xx; + struct cvmx_pemx_bar1_indexx_s cn63xx; + struct cvmx_pemx_bar1_indexx_s cn63xxp1; + struct cvmx_pemx_bar1_indexx_s cn66xx; + struct cvmx_pemx_bar1_indexx_s cn68xx; + struct cvmx_pemx_bar1_indexx_s cn68xxp1; +}; + +union cvmx_pemx_bar2_mask { + uint64_t u64; + struct cvmx_pemx_bar2_mask_s { + uint64_t reserved_38_63:26; + uint64_t mask:35; + uint64_t reserved_0_2:3; + } s; + struct cvmx_pemx_bar2_mask_s cn61xx; + struct cvmx_pemx_bar2_mask_s cn66xx; + struct cvmx_pemx_bar2_mask_s cn68xx; + struct cvmx_pemx_bar2_mask_s cn68xxp1; +}; + +union cvmx_pemx_bar_ctl { + uint64_t u64; + struct cvmx_pemx_bar_ctl_s { + uint64_t reserved_7_63:57; + uint64_t bar1_siz:3; + uint64_t bar2_enb:1; + uint64_t bar2_esx:2; + uint64_t bar2_cax:1; + } s; + struct cvmx_pemx_bar_ctl_s cn61xx; + struct cvmx_pemx_bar_ctl_s cn63xx; + struct cvmx_pemx_bar_ctl_s cn63xxp1; + struct cvmx_pemx_bar_ctl_s cn66xx; + struct cvmx_pemx_bar_ctl_s cn68xx; + struct cvmx_pemx_bar_ctl_s cn68xxp1; +}; + +union cvmx_pemx_bist_status { + uint64_t u64; + struct cvmx_pemx_bist_status_s { + uint64_t reserved_8_63:56; + uint64_t retry:1; + uint64_t rqdata0:1; + uint64_t rqdata1:1; + uint64_t rqdata2:1; + uint64_t rqdata3:1; + uint64_t rqhdr1:1; + uint64_t rqhdr0:1; + uint64_t sot:1; + } s; + struct cvmx_pemx_bist_status_s cn61xx; + struct cvmx_pemx_bist_status_s cn63xx; + struct cvmx_pemx_bist_status_s cn63xxp1; + struct cvmx_pemx_bist_status_s cn66xx; + struct cvmx_pemx_bist_status_s cn68xx; + struct cvmx_pemx_bist_status_s cn68xxp1; +}; + +union cvmx_pemx_bist_status2 { + uint64_t u64; + struct cvmx_pemx_bist_status2_s { + uint64_t reserved_10_63:54; + uint64_t e2p_cpl:1; + uint64_t e2p_n:1; + uint64_t e2p_p:1; + uint64_t peai_p2e:1; + uint64_t pef_tpf1:1; + uint64_t pef_tpf0:1; + uint64_t pef_tnf:1; + uint64_t pef_tcf1:1; + uint64_t pef_tc0:1; + uint64_t ppf:1; + } s; + struct cvmx_pemx_bist_status2_s cn61xx; + struct cvmx_pemx_bist_status2_s cn63xx; + struct cvmx_pemx_bist_status2_s cn63xxp1; + struct cvmx_pemx_bist_status2_s cn66xx; + struct cvmx_pemx_bist_status2_s cn68xx; + struct cvmx_pemx_bist_status2_s cn68xxp1; +}; + +union cvmx_pemx_cfg_rd { + uint64_t u64; + struct cvmx_pemx_cfg_rd_s { + uint64_t data:32; + uint64_t addr:32; + } s; + struct cvmx_pemx_cfg_rd_s cn61xx; + struct cvmx_pemx_cfg_rd_s cn63xx; + struct cvmx_pemx_cfg_rd_s cn63xxp1; + struct cvmx_pemx_cfg_rd_s cn66xx; + struct cvmx_pemx_cfg_rd_s cn68xx; + struct cvmx_pemx_cfg_rd_s cn68xxp1; +}; + +union cvmx_pemx_cfg_wr { + uint64_t u64; + struct cvmx_pemx_cfg_wr_s { + uint64_t data:32; + uint64_t addr:32; + } s; + struct cvmx_pemx_cfg_wr_s cn61xx; + struct cvmx_pemx_cfg_wr_s cn63xx; + struct cvmx_pemx_cfg_wr_s cn63xxp1; + struct cvmx_pemx_cfg_wr_s cn66xx; + struct cvmx_pemx_cfg_wr_s cn68xx; + struct cvmx_pemx_cfg_wr_s cn68xxp1; +}; + +union cvmx_pemx_cpl_lut_valid { + uint64_t u64; + struct cvmx_pemx_cpl_lut_valid_s { + uint64_t reserved_32_63:32; + uint64_t tag:32; + } s; + struct cvmx_pemx_cpl_lut_valid_s cn61xx; + struct cvmx_pemx_cpl_lut_valid_s cn63xx; + struct cvmx_pemx_cpl_lut_valid_s cn63xxp1; + struct cvmx_pemx_cpl_lut_valid_s cn66xx; + struct cvmx_pemx_cpl_lut_valid_s cn68xx; + struct cvmx_pemx_cpl_lut_valid_s cn68xxp1; +}; + +union cvmx_pemx_ctl_status { + uint64_t u64; + struct cvmx_pemx_ctl_status_s { + uint64_t reserved_48_63:16; + uint64_t auto_sd:1; + uint64_t dnum:5; + uint64_t pbus:8; + uint64_t reserved_32_33:2; + uint64_t cfg_rtry:16; + uint64_t reserved_12_15:4; + uint64_t pm_xtoff:1; + uint64_t pm_xpme:1; + uint64_t ob_p_cmd:1; + uint64_t reserved_7_8:2; + uint64_t nf_ecrc:1; + uint64_t dly_one:1; + uint64_t lnk_enb:1; + uint64_t ro_ctlp:1; + uint64_t fast_lm:1; + uint64_t inv_ecrc:1; + uint64_t inv_lcrc:1; + } s; + struct cvmx_pemx_ctl_status_s cn61xx; + struct cvmx_pemx_ctl_status_s cn63xx; + struct cvmx_pemx_ctl_status_s cn63xxp1; + struct cvmx_pemx_ctl_status_s cn66xx; + struct cvmx_pemx_ctl_status_s cn68xx; + struct cvmx_pemx_ctl_status_s cn68xxp1; +}; + +union cvmx_pemx_dbg_info { + uint64_t u64; + struct cvmx_pemx_dbg_info_s { + uint64_t reserved_31_63:33; + uint64_t ecrc_e:1; + uint64_t rawwpp:1; + uint64_t racpp:1; + uint64_t ramtlp:1; + uint64_t rarwdns:1; + uint64_t caar:1; + uint64_t racca:1; + uint64_t racur:1; + uint64_t rauc:1; + uint64_t rqo:1; + uint64_t fcuv:1; + uint64_t rpe:1; + uint64_t fcpvwt:1; + uint64_t dpeoosd:1; + uint64_t rtwdle:1; + uint64_t rdwdle:1; + uint64_t mre:1; + uint64_t rte:1; + uint64_t acto:1; + uint64_t rvdm:1; + uint64_t rumep:1; + uint64_t rptamrc:1; + uint64_t rpmerc:1; + uint64_t rfemrc:1; + uint64_t rnfemrc:1; + uint64_t rcemrc:1; + uint64_t rpoison:1; + uint64_t recrce:1; + uint64_t rtlplle:1; + uint64_t rtlpmal:1; + uint64_t spoison:1; + } s; + struct cvmx_pemx_dbg_info_s cn61xx; + struct cvmx_pemx_dbg_info_s cn63xx; + struct cvmx_pemx_dbg_info_s cn63xxp1; + struct cvmx_pemx_dbg_info_s cn66xx; + struct cvmx_pemx_dbg_info_s cn68xx; + struct cvmx_pemx_dbg_info_s cn68xxp1; +}; + +union cvmx_pemx_dbg_info_en { + uint64_t u64; + struct cvmx_pemx_dbg_info_en_s { + uint64_t reserved_31_63:33; + uint64_t ecrc_e:1; + uint64_t rawwpp:1; + uint64_t racpp:1; + uint64_t ramtlp:1; + uint64_t rarwdns:1; + uint64_t caar:1; + uint64_t racca:1; + uint64_t racur:1; + uint64_t rauc:1; + uint64_t rqo:1; + uint64_t fcuv:1; + uint64_t rpe:1; + uint64_t fcpvwt:1; + uint64_t dpeoosd:1; + uint64_t rtwdle:1; + uint64_t rdwdle:1; + uint64_t mre:1; + uint64_t rte:1; + uint64_t acto:1; + uint64_t rvdm:1; + uint64_t rumep:1; + uint64_t rptamrc:1; + uint64_t rpmerc:1; + uint64_t rfemrc:1; + uint64_t rnfemrc:1; + uint64_t rcemrc:1; + uint64_t rpoison:1; + uint64_t recrce:1; + uint64_t rtlplle:1; + uint64_t rtlpmal:1; + uint64_t spoison:1; + } s; + struct cvmx_pemx_dbg_info_en_s cn61xx; + struct cvmx_pemx_dbg_info_en_s cn63xx; + struct cvmx_pemx_dbg_info_en_s cn63xxp1; + struct cvmx_pemx_dbg_info_en_s cn66xx; + struct cvmx_pemx_dbg_info_en_s cn68xx; + struct cvmx_pemx_dbg_info_en_s cn68xxp1; +}; + +union cvmx_pemx_diag_status { + uint64_t u64; + struct cvmx_pemx_diag_status_s { + uint64_t reserved_4_63:60; + uint64_t pm_dst:1; + uint64_t pm_stat:1; + uint64_t pm_en:1; + uint64_t aux_en:1; + } s; + struct cvmx_pemx_diag_status_s cn61xx; + struct cvmx_pemx_diag_status_s cn63xx; + struct cvmx_pemx_diag_status_s cn63xxp1; + struct cvmx_pemx_diag_status_s cn66xx; + struct cvmx_pemx_diag_status_s cn68xx; + struct cvmx_pemx_diag_status_s cn68xxp1; +}; + +union cvmx_pemx_inb_read_credits { + uint64_t u64; + struct cvmx_pemx_inb_read_credits_s { + uint64_t reserved_6_63:58; + uint64_t num:6; + } s; + struct cvmx_pemx_inb_read_credits_s cn61xx; + struct cvmx_pemx_inb_read_credits_s cn66xx; + struct cvmx_pemx_inb_read_credits_s cn68xx; +}; + +union cvmx_pemx_int_enb { + uint64_t u64; + struct cvmx_pemx_int_enb_s { + uint64_t reserved_14_63:50; + uint64_t crs_dr:1; + uint64_t crs_er:1; + uint64_t rdlk:1; + uint64_t exc:1; + uint64_t un_bx:1; + uint64_t un_b2:1; + uint64_t un_b1:1; + uint64_t up_bx:1; + uint64_t up_b2:1; + uint64_t up_b1:1; + uint64_t pmem:1; + uint64_t pmei:1; + uint64_t se:1; + uint64_t aeri:1; + } s; + struct cvmx_pemx_int_enb_s cn61xx; + struct cvmx_pemx_int_enb_s cn63xx; + struct cvmx_pemx_int_enb_s cn63xxp1; + struct cvmx_pemx_int_enb_s cn66xx; + struct cvmx_pemx_int_enb_s cn68xx; + struct cvmx_pemx_int_enb_s cn68xxp1; +}; + +union cvmx_pemx_int_enb_int { + uint64_t u64; + struct cvmx_pemx_int_enb_int_s { + uint64_t reserved_14_63:50; + uint64_t crs_dr:1; + uint64_t crs_er:1; + uint64_t rdlk:1; + uint64_t exc:1; + uint64_t un_bx:1; + uint64_t un_b2:1; + uint64_t un_b1:1; + uint64_t up_bx:1; + uint64_t up_b2:1; + uint64_t up_b1:1; + uint64_t pmem:1; + uint64_t pmei:1; + uint64_t se:1; + uint64_t aeri:1; + } s; + struct cvmx_pemx_int_enb_int_s cn61xx; + struct cvmx_pemx_int_enb_int_s cn63xx; + struct cvmx_pemx_int_enb_int_s cn63xxp1; + struct cvmx_pemx_int_enb_int_s cn66xx; + struct cvmx_pemx_int_enb_int_s cn68xx; + struct cvmx_pemx_int_enb_int_s cn68xxp1; +}; + +union cvmx_pemx_int_sum { + uint64_t u64; + struct cvmx_pemx_int_sum_s { + uint64_t reserved_14_63:50; + uint64_t crs_dr:1; + uint64_t crs_er:1; + uint64_t rdlk:1; + uint64_t exc:1; + uint64_t un_bx:1; + uint64_t un_b2:1; + uint64_t un_b1:1; + uint64_t up_bx:1; + uint64_t up_b2:1; + uint64_t up_b1:1; + uint64_t pmem:1; + uint64_t pmei:1; + uint64_t se:1; + uint64_t aeri:1; + } s; + struct cvmx_pemx_int_sum_s cn61xx; + struct cvmx_pemx_int_sum_s cn63xx; + struct cvmx_pemx_int_sum_s cn63xxp1; + struct cvmx_pemx_int_sum_s cn66xx; + struct cvmx_pemx_int_sum_s cn68xx; + struct cvmx_pemx_int_sum_s cn68xxp1; +}; + +union cvmx_pemx_p2n_bar0_start { + uint64_t u64; + struct cvmx_pemx_p2n_bar0_start_s { + uint64_t addr:50; + uint64_t reserved_0_13:14; + } s; + struct cvmx_pemx_p2n_bar0_start_s cn61xx; + struct cvmx_pemx_p2n_bar0_start_s cn63xx; + struct cvmx_pemx_p2n_bar0_start_s cn63xxp1; + struct cvmx_pemx_p2n_bar0_start_s cn66xx; + struct cvmx_pemx_p2n_bar0_start_s cn68xx; + struct cvmx_pemx_p2n_bar0_start_s cn68xxp1; +}; + +union cvmx_pemx_p2n_bar1_start { + uint64_t u64; + struct cvmx_pemx_p2n_bar1_start_s { + uint64_t addr:38; + uint64_t reserved_0_25:26; + } s; + struct cvmx_pemx_p2n_bar1_start_s cn61xx; + struct cvmx_pemx_p2n_bar1_start_s cn63xx; + struct cvmx_pemx_p2n_bar1_start_s cn63xxp1; + struct cvmx_pemx_p2n_bar1_start_s cn66xx; + struct cvmx_pemx_p2n_bar1_start_s cn68xx; + struct cvmx_pemx_p2n_bar1_start_s cn68xxp1; +}; + +union cvmx_pemx_p2n_bar2_start { + uint64_t u64; + struct cvmx_pemx_p2n_bar2_start_s { + uint64_t addr:23; + uint64_t reserved_0_40:41; + } s; + struct cvmx_pemx_p2n_bar2_start_s cn61xx; + struct cvmx_pemx_p2n_bar2_start_s cn63xx; + struct cvmx_pemx_p2n_bar2_start_s cn63xxp1; + struct cvmx_pemx_p2n_bar2_start_s cn66xx; + struct cvmx_pemx_p2n_bar2_start_s cn68xx; + struct cvmx_pemx_p2n_bar2_start_s cn68xxp1; +}; + +union cvmx_pemx_p2p_barx_end { + uint64_t u64; + struct cvmx_pemx_p2p_barx_end_s { + uint64_t addr:52; + uint64_t reserved_0_11:12; + } s; + struct cvmx_pemx_p2p_barx_end_s cn63xx; + struct cvmx_pemx_p2p_barx_end_s cn63xxp1; + struct cvmx_pemx_p2p_barx_end_s cn66xx; + struct cvmx_pemx_p2p_barx_end_s cn68xx; + struct cvmx_pemx_p2p_barx_end_s cn68xxp1; +}; + +union cvmx_pemx_p2p_barx_start { + uint64_t u64; + struct cvmx_pemx_p2p_barx_start_s { + uint64_t addr:52; + uint64_t reserved_0_11:12; + } s; + struct cvmx_pemx_p2p_barx_start_s cn63xx; + struct cvmx_pemx_p2p_barx_start_s cn63xxp1; + struct cvmx_pemx_p2p_barx_start_s cn66xx; + struct cvmx_pemx_p2p_barx_start_s cn68xx; + struct cvmx_pemx_p2p_barx_start_s cn68xxp1; +}; + +union cvmx_pemx_tlp_credits { + uint64_t u64; + struct cvmx_pemx_tlp_credits_s { + uint64_t reserved_56_63:8; + uint64_t peai_ppf:8; + uint64_t pem_cpl:8; + uint64_t pem_np:8; + uint64_t pem_p:8; + uint64_t sli_cpl:8; + uint64_t sli_np:8; + uint64_t sli_p:8; + } s; + struct cvmx_pemx_tlp_credits_cn61xx { + uint64_t reserved_56_63:8; + uint64_t peai_ppf:8; + uint64_t reserved_24_47:24; + uint64_t sli_cpl:8; + uint64_t sli_np:8; + uint64_t sli_p:8; + } cn61xx; + struct cvmx_pemx_tlp_credits_s cn63xx; + struct cvmx_pemx_tlp_credits_s cn63xxp1; + struct cvmx_pemx_tlp_credits_s cn66xx; + struct cvmx_pemx_tlp_credits_s cn68xx; + struct cvmx_pemx_tlp_credits_s cn68xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h index 5ab8679d89af..4438d211988b 100644 --- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -25,13 +25,6 @@ * Contact Cavium Networks for more information ***********************license end**************************************/ -/** - * cvmx-pexp-defs.h - * - * Configuration and status register (CSR) definitions for - * OCTEON PEXP. - * - */ #ifndef __CVMX_PEXP_DEFS_H__ #define __CVMX_PEXP_DEFS_H__ @@ -139,7 +132,7 @@ #define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull)) #define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull)) #define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull)) -#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16) +#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16) #define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull)) #define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull)) #define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull)) @@ -152,7 +145,10 @@ #define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull)) #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull)) #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull)) +#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull)) +#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull)) #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull)) +#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull)) #define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull)) #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12) #define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull)) @@ -206,6 +202,7 @@ #define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull)) #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull)) #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull)) +#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull)) #define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull)) #define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull)) #define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull)) @@ -214,12 +211,14 @@ #define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull)) #define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull)) #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull)) -#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16) +#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16) #define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull)) #define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull)) #define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull)) #define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull)) #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull)) +#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull)) #define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull)) #endif diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h new file mode 100644 index 000000000000..7c6c901d3d28 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h @@ -0,0 +1,2172 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2011 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SLI_DEFS_H__ +#define __CVMX_SLI_DEFS_H__ + +#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull) +#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16) +#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull) +#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull) +#define CVMX_SLI_DBG_DATA (0x0000000000000310ull) +#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull) +#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16) +#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16) +#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16) +#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull) +#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16) +#define CVMX_SLI_INT_SUM (0x0000000000000330ull) +#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull) +#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull) +#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull) +#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull) +#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull) +#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull) +#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull) +#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull) +#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12) +#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull) +#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull) +#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull) +#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull) +#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull) +#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull) +#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull) +#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull) +#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull) +#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull) +#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull) +#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull) +#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull) +#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull) +#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull) +#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull) +#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull) +#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull) +#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull) +#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) +#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) +#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) +#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull) +#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull) +#define CVMX_SLI_PKT_CTL (0x0000000000001220ull) +#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull) +#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull) +#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull) +#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull) +#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull) +#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull) +#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull) +#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull) +#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull) +#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull) +#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) +#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull) +#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull) +#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull) +#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull) +#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull) +#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull) +#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull) +#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull) +#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull) +#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull) +#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull) +#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull) +#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull) +#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull) +#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16) +#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16) +#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull) +#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull) +#define CVMX_SLI_STATE1 (0x0000000000000620ull) +#define CVMX_SLI_STATE2 (0x0000000000000630ull) +#define CVMX_SLI_STATE3 (0x0000000000000640ull) +#define CVMX_SLI_TX_PIPE (0x0000000000001230ull) +#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull) +#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull) +#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull) +#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull) +#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull) +#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull) + +union cvmx_sli_bist_status { + uint64_t u64; + struct cvmx_sli_bist_status_s { + uint64_t reserved_32_63:32; + uint64_t ncb_req:1; + uint64_t n2p0_c:1; + uint64_t n2p0_o:1; + uint64_t n2p1_c:1; + uint64_t n2p1_o:1; + uint64_t cpl_p0:1; + uint64_t cpl_p1:1; + uint64_t reserved_19_24:6; + uint64_t p2n0_c0:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_n:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_p1:1; + uint64_t p2n1_c0:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_n:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_p1:1; + uint64_t reserved_6_8:3; + uint64_t dsi1_1:1; + uint64_t dsi1_0:1; + uint64_t dsi0_1:1; + uint64_t dsi0_0:1; + uint64_t msi:1; + uint64_t ncb_cmd:1; + } s; + struct cvmx_sli_bist_status_cn61xx { + uint64_t reserved_31_63:33; + uint64_t n2p0_c:1; + uint64_t n2p0_o:1; + uint64_t reserved_27_28:2; + uint64_t cpl_p0:1; + uint64_t cpl_p1:1; + uint64_t reserved_19_24:6; + uint64_t p2n0_c0:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_n:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_p1:1; + uint64_t p2n1_c0:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_n:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_p1:1; + uint64_t reserved_6_8:3; + uint64_t dsi1_1:1; + uint64_t dsi1_0:1; + uint64_t dsi0_1:1; + uint64_t dsi0_0:1; + uint64_t msi:1; + uint64_t ncb_cmd:1; + } cn61xx; + struct cvmx_sli_bist_status_cn63xx { + uint64_t reserved_31_63:33; + uint64_t n2p0_c:1; + uint64_t n2p0_o:1; + uint64_t n2p1_c:1; + uint64_t n2p1_o:1; + uint64_t cpl_p0:1; + uint64_t cpl_p1:1; + uint64_t reserved_19_24:6; + uint64_t p2n0_c0:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_n:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_p1:1; + uint64_t p2n1_c0:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_n:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_p1:1; + uint64_t reserved_6_8:3; + uint64_t dsi1_1:1; + uint64_t dsi1_0:1; + uint64_t dsi0_1:1; + uint64_t dsi0_0:1; + uint64_t msi:1; + uint64_t ncb_cmd:1; + } cn63xx; + struct cvmx_sli_bist_status_cn63xx cn63xxp1; + struct cvmx_sli_bist_status_cn61xx cn66xx; + struct cvmx_sli_bist_status_s cn68xx; + struct cvmx_sli_bist_status_s cn68xxp1; +}; + +union cvmx_sli_ctl_portx { + uint64_t u64; + struct cvmx_sli_ctl_portx_s { + uint64_t reserved_22_63:42; + uint64_t intd:1; + uint64_t intc:1; + uint64_t intb:1; + uint64_t inta:1; + uint64_t dis_port:1; + uint64_t waitl_com:1; + uint64_t intd_map:2; + uint64_t intc_map:2; + uint64_t intb_map:2; + uint64_t inta_map:2; + uint64_t ctlp_ro:1; + uint64_t reserved_6_6:1; + uint64_t ptlp_ro:1; + uint64_t reserved_1_4:4; + uint64_t wait_com:1; + } s; + struct cvmx_sli_ctl_portx_s cn61xx; + struct cvmx_sli_ctl_portx_s cn63xx; + struct cvmx_sli_ctl_portx_s cn63xxp1; + struct cvmx_sli_ctl_portx_s cn66xx; + struct cvmx_sli_ctl_portx_s cn68xx; + struct cvmx_sli_ctl_portx_s cn68xxp1; +}; + +union cvmx_sli_ctl_status { + uint64_t u64; + struct cvmx_sli_ctl_status_s { + uint64_t reserved_20_63:44; + uint64_t p1_ntags:6; + uint64_t p0_ntags:6; + uint64_t chip_rev:8; + } s; + struct cvmx_sli_ctl_status_cn61xx { + uint64_t reserved_14_63:50; + uint64_t p0_ntags:6; + uint64_t chip_rev:8; + } cn61xx; + struct cvmx_sli_ctl_status_s cn63xx; + struct cvmx_sli_ctl_status_s cn63xxp1; + struct cvmx_sli_ctl_status_cn61xx cn66xx; + struct cvmx_sli_ctl_status_s cn68xx; + struct cvmx_sli_ctl_status_s cn68xxp1; +}; + +union cvmx_sli_data_out_cnt { + uint64_t u64; + struct cvmx_sli_data_out_cnt_s { + uint64_t reserved_44_63:20; + uint64_t p1_ucnt:16; + uint64_t p1_fcnt:6; + uint64_t p0_ucnt:16; + uint64_t p0_fcnt:6; + } s; + struct cvmx_sli_data_out_cnt_s cn61xx; + struct cvmx_sli_data_out_cnt_s cn63xx; + struct cvmx_sli_data_out_cnt_s cn63xxp1; + struct cvmx_sli_data_out_cnt_s cn66xx; + struct cvmx_sli_data_out_cnt_s cn68xx; + struct cvmx_sli_data_out_cnt_s cn68xxp1; +}; + +union cvmx_sli_dbg_data { + uint64_t u64; + struct cvmx_sli_dbg_data_s { + uint64_t reserved_18_63:46; + uint64_t dsel_ext:1; + uint64_t data:17; + } s; + struct cvmx_sli_dbg_data_s cn61xx; + struct cvmx_sli_dbg_data_s cn63xx; + struct cvmx_sli_dbg_data_s cn63xxp1; + struct cvmx_sli_dbg_data_s cn66xx; + struct cvmx_sli_dbg_data_s cn68xx; + struct cvmx_sli_dbg_data_s cn68xxp1; +}; + +union cvmx_sli_dbg_select { + uint64_t u64; + struct cvmx_sli_dbg_select_s { + uint64_t reserved_33_63:31; + uint64_t adbg_sel:1; + uint64_t dbg_sel:32; + } s; + struct cvmx_sli_dbg_select_s cn61xx; + struct cvmx_sli_dbg_select_s cn63xx; + struct cvmx_sli_dbg_select_s cn63xxp1; + struct cvmx_sli_dbg_select_s cn66xx; + struct cvmx_sli_dbg_select_s cn68xx; + struct cvmx_sli_dbg_select_s cn68xxp1; +}; + +union cvmx_sli_dmax_cnt { + uint64_t u64; + struct cvmx_sli_dmax_cnt_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_sli_dmax_cnt_s cn61xx; + struct cvmx_sli_dmax_cnt_s cn63xx; + struct cvmx_sli_dmax_cnt_s cn63xxp1; + struct cvmx_sli_dmax_cnt_s cn66xx; + struct cvmx_sli_dmax_cnt_s cn68xx; + struct cvmx_sli_dmax_cnt_s cn68xxp1; +}; + +union cvmx_sli_dmax_int_level { + uint64_t u64; + struct cvmx_sli_dmax_int_level_s { + uint64_t time:32; + uint64_t cnt:32; + } s; + struct cvmx_sli_dmax_int_level_s cn61xx; + struct cvmx_sli_dmax_int_level_s cn63xx; + struct cvmx_sli_dmax_int_level_s cn63xxp1; + struct cvmx_sli_dmax_int_level_s cn66xx; + struct cvmx_sli_dmax_int_level_s cn68xx; + struct cvmx_sli_dmax_int_level_s cn68xxp1; +}; + +union cvmx_sli_dmax_tim { + uint64_t u64; + struct cvmx_sli_dmax_tim_s { + uint64_t reserved_32_63:32; + uint64_t tim:32; + } s; + struct cvmx_sli_dmax_tim_s cn61xx; + struct cvmx_sli_dmax_tim_s cn63xx; + struct cvmx_sli_dmax_tim_s cn63xxp1; + struct cvmx_sli_dmax_tim_s cn66xx; + struct cvmx_sli_dmax_tim_s cn68xx; + struct cvmx_sli_dmax_tim_s cn68xxp1; +}; + +union cvmx_sli_int_enb_ciu { + uint64_t u64; + struct cvmx_sli_int_enb_ciu_s { + uint64_t reserved_62_63:2; + uint64_t pipe_err:1; + uint64_t ill_pad:1; + uint64_t sprt3_err:1; + uint64_t sprt2_err:1; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_28_31:4; + uint64_t m3_un_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_up_b0:1; + uint64_t m2_un_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_up_b0:1; + uint64_t reserved_18_19:2; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } s; + struct cvmx_sli_int_enb_ciu_cn61xx { + uint64_t reserved_61_63:3; + uint64_t ill_pad:1; + uint64_t sprt3_err:1; + uint64_t sprt2_err:1; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_28_31:4; + uint64_t m3_un_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_up_b0:1; + uint64_t m2_un_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_up_b0:1; + uint64_t reserved_18_19:2; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn61xx; + struct cvmx_sli_int_enb_ciu_cn63xx { + uint64_t reserved_61_63:3; + uint64_t ill_pad:1; + uint64_t reserved_58_59:2; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_18_31:14; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn63xx; + struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1; + struct cvmx_sli_int_enb_ciu_cn61xx cn66xx; + struct cvmx_sli_int_enb_ciu_cn68xx { + uint64_t reserved_62_63:2; + uint64_t pipe_err:1; + uint64_t ill_pad:1; + uint64_t reserved_58_59:2; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t reserved_51_51:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_18_31:14; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn68xx; + struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1; +}; + +union cvmx_sli_int_enb_portx { + uint64_t u64; + struct cvmx_sli_int_enb_portx_s { + uint64_t reserved_62_63:2; + uint64_t pipe_err:1; + uint64_t ill_pad:1; + uint64_t sprt3_err:1; + uint64_t sprt2_err:1; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_28_31:4; + uint64_t m3_un_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_up_b0:1; + uint64_t m2_un_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_up_b0:1; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } s; + struct cvmx_sli_int_enb_portx_cn61xx { + uint64_t reserved_61_63:3; + uint64_t ill_pad:1; + uint64_t sprt3_err:1; + uint64_t sprt2_err:1; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_28_31:4; + uint64_t m3_un_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_up_b0:1; + uint64_t m2_un_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_up_b0:1; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn61xx; + struct cvmx_sli_int_enb_portx_cn63xx { + uint64_t reserved_61_63:3; + uint64_t ill_pad:1; + uint64_t reserved_58_59:2; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_20_31:12; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn63xx; + struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1; + struct cvmx_sli_int_enb_portx_cn61xx cn66xx; + struct cvmx_sli_int_enb_portx_cn68xx { + uint64_t reserved_62_63:2; + uint64_t pipe_err:1; + uint64_t ill_pad:1; + uint64_t reserved_58_59:2; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t reserved_51_51:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_20_31:12; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn68xx; + struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1; +}; + +union cvmx_sli_int_sum { + uint64_t u64; + struct cvmx_sli_int_sum_s { + uint64_t reserved_62_63:2; + uint64_t pipe_err:1; + uint64_t ill_pad:1; + uint64_t sprt3_err:1; + uint64_t sprt2_err:1; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_28_31:4; + uint64_t m3_un_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_up_b0:1; + uint64_t m2_un_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_up_b0:1; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } s; + struct cvmx_sli_int_sum_cn61xx { + uint64_t reserved_61_63:3; + uint64_t ill_pad:1; + uint64_t sprt3_err:1; + uint64_t sprt2_err:1; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_28_31:4; + uint64_t m3_un_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_up_b0:1; + uint64_t m2_un_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_up_b0:1; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn61xx; + struct cvmx_sli_int_sum_cn63xx { + uint64_t reserved_61_63:3; + uint64_t ill_pad:1; + uint64_t reserved_58_59:2; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_20_31:12; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn63xx; + struct cvmx_sli_int_sum_cn63xx cn63xxp1; + struct cvmx_sli_int_sum_cn61xx cn66xx; + struct cvmx_sli_int_sum_cn68xx { + uint64_t reserved_62_63:2; + uint64_t pipe_err:1; + uint64_t ill_pad:1; + uint64_t reserved_58_59:2; + uint64_t sprt1_err:1; + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t reserved_51_51:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_20_31:12; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; + } cn68xx; + struct cvmx_sli_int_sum_cn68xx cn68xxp1; +}; + +union cvmx_sli_last_win_rdata0 { + uint64_t u64; + struct cvmx_sli_last_win_rdata0_s { + uint64_t data:64; + } s; + struct cvmx_sli_last_win_rdata0_s cn61xx; + struct cvmx_sli_last_win_rdata0_s cn63xx; + struct cvmx_sli_last_win_rdata0_s cn63xxp1; + struct cvmx_sli_last_win_rdata0_s cn66xx; + struct cvmx_sli_last_win_rdata0_s cn68xx; + struct cvmx_sli_last_win_rdata0_s cn68xxp1; +}; + +union cvmx_sli_last_win_rdata1 { + uint64_t u64; + struct cvmx_sli_last_win_rdata1_s { + uint64_t data:64; + } s; + struct cvmx_sli_last_win_rdata1_s cn61xx; + struct cvmx_sli_last_win_rdata1_s cn63xx; + struct cvmx_sli_last_win_rdata1_s cn63xxp1; + struct cvmx_sli_last_win_rdata1_s cn66xx; + struct cvmx_sli_last_win_rdata1_s cn68xx; + struct cvmx_sli_last_win_rdata1_s cn68xxp1; +}; + +union cvmx_sli_last_win_rdata2 { + uint64_t u64; + struct cvmx_sli_last_win_rdata2_s { + uint64_t data:64; + } s; + struct cvmx_sli_last_win_rdata2_s cn61xx; + struct cvmx_sli_last_win_rdata2_s cn66xx; +}; + +union cvmx_sli_last_win_rdata3 { + uint64_t u64; + struct cvmx_sli_last_win_rdata3_s { + uint64_t data:64; + } s; + struct cvmx_sli_last_win_rdata3_s cn61xx; + struct cvmx_sli_last_win_rdata3_s cn66xx; +}; + +union cvmx_sli_mac_credit_cnt { + uint64_t u64; + struct cvmx_sli_mac_credit_cnt_s { + uint64_t reserved_54_63:10; + uint64_t p1_c_d:1; + uint64_t p1_n_d:1; + uint64_t p1_p_d:1; + uint64_t p0_c_d:1; + uint64_t p0_n_d:1; + uint64_t p0_p_d:1; + uint64_t p1_ccnt:8; + uint64_t p1_ncnt:8; + uint64_t p1_pcnt:8; + uint64_t p0_ccnt:8; + uint64_t p0_ncnt:8; + uint64_t p0_pcnt:8; + } s; + struct cvmx_sli_mac_credit_cnt_s cn61xx; + struct cvmx_sli_mac_credit_cnt_s cn63xx; + struct cvmx_sli_mac_credit_cnt_cn63xxp1 { + uint64_t reserved_48_63:16; + uint64_t p1_ccnt:8; + uint64_t p1_ncnt:8; + uint64_t p1_pcnt:8; + uint64_t p0_ccnt:8; + uint64_t p0_ncnt:8; + uint64_t p0_pcnt:8; + } cn63xxp1; + struct cvmx_sli_mac_credit_cnt_s cn66xx; + struct cvmx_sli_mac_credit_cnt_s cn68xx; + struct cvmx_sli_mac_credit_cnt_s cn68xxp1; +}; + +union cvmx_sli_mac_credit_cnt2 { + uint64_t u64; + struct cvmx_sli_mac_credit_cnt2_s { + uint64_t reserved_54_63:10; + uint64_t p3_c_d:1; + uint64_t p3_n_d:1; + uint64_t p3_p_d:1; + uint64_t p2_c_d:1; + uint64_t p2_n_d:1; + uint64_t p2_p_d:1; + uint64_t p3_ccnt:8; + uint64_t p3_ncnt:8; + uint64_t p3_pcnt:8; + uint64_t p2_ccnt:8; + uint64_t p2_ncnt:8; + uint64_t p2_pcnt:8; + } s; + struct cvmx_sli_mac_credit_cnt2_s cn61xx; + struct cvmx_sli_mac_credit_cnt2_s cn66xx; +}; + +union cvmx_sli_mac_number { + uint64_t u64; + struct cvmx_sli_mac_number_s { + uint64_t reserved_9_63:55; + uint64_t a_mode:1; + uint64_t num:8; + } s; + struct cvmx_sli_mac_number_s cn61xx; + struct cvmx_sli_mac_number_cn63xx { + uint64_t reserved_8_63:56; + uint64_t num:8; + } cn63xx; + struct cvmx_sli_mac_number_s cn66xx; + struct cvmx_sli_mac_number_cn63xx cn68xx; + struct cvmx_sli_mac_number_cn63xx cn68xxp1; +}; + +union cvmx_sli_mem_access_ctl { + uint64_t u64; + struct cvmx_sli_mem_access_ctl_s { + uint64_t reserved_14_63:50; + uint64_t max_word:4; + uint64_t timer:10; + } s; + struct cvmx_sli_mem_access_ctl_s cn61xx; + struct cvmx_sli_mem_access_ctl_s cn63xx; + struct cvmx_sli_mem_access_ctl_s cn63xxp1; + struct cvmx_sli_mem_access_ctl_s cn66xx; + struct cvmx_sli_mem_access_ctl_s cn68xx; + struct cvmx_sli_mem_access_ctl_s cn68xxp1; +}; + +union cvmx_sli_mem_access_subidx { + uint64_t u64; + struct cvmx_sli_mem_access_subidx_s { + uint64_t reserved_43_63:21; + uint64_t zero:1; + uint64_t port:3; + uint64_t nmerge:1; + uint64_t esr:2; + uint64_t esw:2; + uint64_t wtype:2; + uint64_t rtype:2; + uint64_t reserved_0_29:30; + } s; + struct cvmx_sli_mem_access_subidx_cn61xx { + uint64_t reserved_43_63:21; + uint64_t zero:1; + uint64_t port:3; + uint64_t nmerge:1; + uint64_t esr:2; + uint64_t esw:2; + uint64_t wtype:2; + uint64_t rtype:2; + uint64_t ba:30; + } cn61xx; + struct cvmx_sli_mem_access_subidx_cn61xx cn63xx; + struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1; + struct cvmx_sli_mem_access_subidx_cn61xx cn66xx; + struct cvmx_sli_mem_access_subidx_cn68xx { + uint64_t reserved_43_63:21; + uint64_t zero:1; + uint64_t port:3; + uint64_t nmerge:1; + uint64_t esr:2; + uint64_t esw:2; + uint64_t wtype:2; + uint64_t rtype:2; + uint64_t ba:28; + uint64_t reserved_0_1:2; + } cn68xx; + struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1; +}; + +union cvmx_sli_msi_enb0 { + uint64_t u64; + struct cvmx_sli_msi_enb0_s { + uint64_t enb:64; + } s; + struct cvmx_sli_msi_enb0_s cn61xx; + struct cvmx_sli_msi_enb0_s cn63xx; + struct cvmx_sli_msi_enb0_s cn63xxp1; + struct cvmx_sli_msi_enb0_s cn66xx; + struct cvmx_sli_msi_enb0_s cn68xx; + struct cvmx_sli_msi_enb0_s cn68xxp1; +}; + +union cvmx_sli_msi_enb1 { + uint64_t u64; + struct cvmx_sli_msi_enb1_s { + uint64_t enb:64; + } s; + struct cvmx_sli_msi_enb1_s cn61xx; + struct cvmx_sli_msi_enb1_s cn63xx; + struct cvmx_sli_msi_enb1_s cn63xxp1; + struct cvmx_sli_msi_enb1_s cn66xx; + struct cvmx_sli_msi_enb1_s cn68xx; + struct cvmx_sli_msi_enb1_s cn68xxp1; +}; + +union cvmx_sli_msi_enb2 { + uint64_t u64; + struct cvmx_sli_msi_enb2_s { + uint64_t enb:64; + } s; + struct cvmx_sli_msi_enb2_s cn61xx; + struct cvmx_sli_msi_enb2_s cn63xx; + struct cvmx_sli_msi_enb2_s cn63xxp1; + struct cvmx_sli_msi_enb2_s cn66xx; + struct cvmx_sli_msi_enb2_s cn68xx; + struct cvmx_sli_msi_enb2_s cn68xxp1; +}; + +union cvmx_sli_msi_enb3 { + uint64_t u64; + struct cvmx_sli_msi_enb3_s { + uint64_t enb:64; + } s; + struct cvmx_sli_msi_enb3_s cn61xx; + struct cvmx_sli_msi_enb3_s cn63xx; + struct cvmx_sli_msi_enb3_s cn63xxp1; + struct cvmx_sli_msi_enb3_s cn66xx; + struct cvmx_sli_msi_enb3_s cn68xx; + struct cvmx_sli_msi_enb3_s cn68xxp1; +}; + +union cvmx_sli_msi_rcv0 { + uint64_t u64; + struct cvmx_sli_msi_rcv0_s { + uint64_t intr:64; + } s; + struct cvmx_sli_msi_rcv0_s cn61xx; + struct cvmx_sli_msi_rcv0_s cn63xx; + struct cvmx_sli_msi_rcv0_s cn63xxp1; + struct cvmx_sli_msi_rcv0_s cn66xx; + struct cvmx_sli_msi_rcv0_s cn68xx; + struct cvmx_sli_msi_rcv0_s cn68xxp1; +}; + +union cvmx_sli_msi_rcv1 { + uint64_t u64; + struct cvmx_sli_msi_rcv1_s { + uint64_t intr:64; + } s; + struct cvmx_sli_msi_rcv1_s cn61xx; + struct cvmx_sli_msi_rcv1_s cn63xx; + struct cvmx_sli_msi_rcv1_s cn63xxp1; + struct cvmx_sli_msi_rcv1_s cn66xx; + struct cvmx_sli_msi_rcv1_s cn68xx; + struct cvmx_sli_msi_rcv1_s cn68xxp1; +}; + +union cvmx_sli_msi_rcv2 { + uint64_t u64; + struct cvmx_sli_msi_rcv2_s { + uint64_t intr:64; + } s; + struct cvmx_sli_msi_rcv2_s cn61xx; + struct cvmx_sli_msi_rcv2_s cn63xx; + struct cvmx_sli_msi_rcv2_s cn63xxp1; + struct cvmx_sli_msi_rcv2_s cn66xx; + struct cvmx_sli_msi_rcv2_s cn68xx; + struct cvmx_sli_msi_rcv2_s cn68xxp1; +}; + +union cvmx_sli_msi_rcv3 { + uint64_t u64; + struct cvmx_sli_msi_rcv3_s { + uint64_t intr:64; + } s; + struct cvmx_sli_msi_rcv3_s cn61xx; + struct cvmx_sli_msi_rcv3_s cn63xx; + struct cvmx_sli_msi_rcv3_s cn63xxp1; + struct cvmx_sli_msi_rcv3_s cn66xx; + struct cvmx_sli_msi_rcv3_s cn68xx; + struct cvmx_sli_msi_rcv3_s cn68xxp1; +}; + +union cvmx_sli_msi_rd_map { + uint64_t u64; + struct cvmx_sli_msi_rd_map_s { + uint64_t reserved_16_63:48; + uint64_t rd_int:8; + uint64_t msi_int:8; + } s; + struct cvmx_sli_msi_rd_map_s cn61xx; + struct cvmx_sli_msi_rd_map_s cn63xx; + struct cvmx_sli_msi_rd_map_s cn63xxp1; + struct cvmx_sli_msi_rd_map_s cn66xx; + struct cvmx_sli_msi_rd_map_s cn68xx; + struct cvmx_sli_msi_rd_map_s cn68xxp1; +}; + +union cvmx_sli_msi_w1c_enb0 { + uint64_t u64; + struct cvmx_sli_msi_w1c_enb0_s { + uint64_t clr:64; + } s; + struct cvmx_sli_msi_w1c_enb0_s cn61xx; + struct cvmx_sli_msi_w1c_enb0_s cn63xx; + struct cvmx_sli_msi_w1c_enb0_s cn63xxp1; + struct cvmx_sli_msi_w1c_enb0_s cn66xx; + struct cvmx_sli_msi_w1c_enb0_s cn68xx; + struct cvmx_sli_msi_w1c_enb0_s cn68xxp1; +}; + +union cvmx_sli_msi_w1c_enb1 { + uint64_t u64; + struct cvmx_sli_msi_w1c_enb1_s { + uint64_t clr:64; + } s; + struct cvmx_sli_msi_w1c_enb1_s cn61xx; + struct cvmx_sli_msi_w1c_enb1_s cn63xx; + struct cvmx_sli_msi_w1c_enb1_s cn63xxp1; + struct cvmx_sli_msi_w1c_enb1_s cn66xx; + struct cvmx_sli_msi_w1c_enb1_s cn68xx; + struct cvmx_sli_msi_w1c_enb1_s cn68xxp1; +}; + +union cvmx_sli_msi_w1c_enb2 { + uint64_t u64; + struct cvmx_sli_msi_w1c_enb2_s { + uint64_t clr:64; + } s; + struct cvmx_sli_msi_w1c_enb2_s cn61xx; + struct cvmx_sli_msi_w1c_enb2_s cn63xx; + struct cvmx_sli_msi_w1c_enb2_s cn63xxp1; + struct cvmx_sli_msi_w1c_enb2_s cn66xx; + struct cvmx_sli_msi_w1c_enb2_s cn68xx; + struct cvmx_sli_msi_w1c_enb2_s cn68xxp1; +}; + +union cvmx_sli_msi_w1c_enb3 { + uint64_t u64; + struct cvmx_sli_msi_w1c_enb3_s { + uint64_t clr:64; + } s; + struct cvmx_sli_msi_w1c_enb3_s cn61xx; + struct cvmx_sli_msi_w1c_enb3_s cn63xx; + struct cvmx_sli_msi_w1c_enb3_s cn63xxp1; + struct cvmx_sli_msi_w1c_enb3_s cn66xx; + struct cvmx_sli_msi_w1c_enb3_s cn68xx; + struct cvmx_sli_msi_w1c_enb3_s cn68xxp1; +}; + +union cvmx_sli_msi_w1s_enb0 { + uint64_t u64; + struct cvmx_sli_msi_w1s_enb0_s { + uint64_t set:64; + } s; + struct cvmx_sli_msi_w1s_enb0_s cn61xx; + struct cvmx_sli_msi_w1s_enb0_s cn63xx; + struct cvmx_sli_msi_w1s_enb0_s cn63xxp1; + struct cvmx_sli_msi_w1s_enb0_s cn66xx; + struct cvmx_sli_msi_w1s_enb0_s cn68xx; + struct cvmx_sli_msi_w1s_enb0_s cn68xxp1; +}; + +union cvmx_sli_msi_w1s_enb1 { + uint64_t u64; + struct cvmx_sli_msi_w1s_enb1_s { + uint64_t set:64; + } s; + struct cvmx_sli_msi_w1s_enb1_s cn61xx; + struct cvmx_sli_msi_w1s_enb1_s cn63xx; + struct cvmx_sli_msi_w1s_enb1_s cn63xxp1; + struct cvmx_sli_msi_w1s_enb1_s cn66xx; + struct cvmx_sli_msi_w1s_enb1_s cn68xx; + struct cvmx_sli_msi_w1s_enb1_s cn68xxp1; +}; + +union cvmx_sli_msi_w1s_enb2 { + uint64_t u64; + struct cvmx_sli_msi_w1s_enb2_s { + uint64_t set:64; + } s; + struct cvmx_sli_msi_w1s_enb2_s cn61xx; + struct cvmx_sli_msi_w1s_enb2_s cn63xx; + struct cvmx_sli_msi_w1s_enb2_s cn63xxp1; + struct cvmx_sli_msi_w1s_enb2_s cn66xx; + struct cvmx_sli_msi_w1s_enb2_s cn68xx; + struct cvmx_sli_msi_w1s_enb2_s cn68xxp1; +}; + +union cvmx_sli_msi_w1s_enb3 { + uint64_t u64; + struct cvmx_sli_msi_w1s_enb3_s { + uint64_t set:64; + } s; + struct cvmx_sli_msi_w1s_enb3_s cn61xx; + struct cvmx_sli_msi_w1s_enb3_s cn63xx; + struct cvmx_sli_msi_w1s_enb3_s cn63xxp1; + struct cvmx_sli_msi_w1s_enb3_s cn66xx; + struct cvmx_sli_msi_w1s_enb3_s cn68xx; + struct cvmx_sli_msi_w1s_enb3_s cn68xxp1; +}; + +union cvmx_sli_msi_wr_map { + uint64_t u64; + struct cvmx_sli_msi_wr_map_s { + uint64_t reserved_16_63:48; + uint64_t ciu_int:8; + uint64_t msi_int:8; + } s; + struct cvmx_sli_msi_wr_map_s cn61xx; + struct cvmx_sli_msi_wr_map_s cn63xx; + struct cvmx_sli_msi_wr_map_s cn63xxp1; + struct cvmx_sli_msi_wr_map_s cn66xx; + struct cvmx_sli_msi_wr_map_s cn68xx; + struct cvmx_sli_msi_wr_map_s cn68xxp1; +}; + +union cvmx_sli_pcie_msi_rcv { + uint64_t u64; + struct cvmx_sli_pcie_msi_rcv_s { + uint64_t reserved_8_63:56; + uint64_t intr:8; + } s; + struct cvmx_sli_pcie_msi_rcv_s cn61xx; + struct cvmx_sli_pcie_msi_rcv_s cn63xx; + struct cvmx_sli_pcie_msi_rcv_s cn63xxp1; + struct cvmx_sli_pcie_msi_rcv_s cn66xx; + struct cvmx_sli_pcie_msi_rcv_s cn68xx; + struct cvmx_sli_pcie_msi_rcv_s cn68xxp1; +}; + +union cvmx_sli_pcie_msi_rcv_b1 { + uint64_t u64; + struct cvmx_sli_pcie_msi_rcv_b1_s { + uint64_t reserved_16_63:48; + uint64_t intr:8; + uint64_t reserved_0_7:8; + } s; + struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx; + struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx; + struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1; + struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx; + struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx; + struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1; +}; + +union cvmx_sli_pcie_msi_rcv_b2 { + uint64_t u64; + struct cvmx_sli_pcie_msi_rcv_b2_s { + uint64_t reserved_24_63:40; + uint64_t intr:8; + uint64_t reserved_0_15:16; + } s; + struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx; + struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx; + struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1; + struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx; + struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx; + struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1; +}; + +union cvmx_sli_pcie_msi_rcv_b3 { + uint64_t u64; + struct cvmx_sli_pcie_msi_rcv_b3_s { + uint64_t reserved_32_63:32; + uint64_t intr:8; + uint64_t reserved_0_23:24; + } s; + struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx; + struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx; + struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1; + struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx; + struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx; + struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1; +}; + +union cvmx_sli_pktx_cnts { + uint64_t u64; + struct cvmx_sli_pktx_cnts_s { + uint64_t reserved_54_63:10; + uint64_t timer:22; + uint64_t cnt:32; + } s; + struct cvmx_sli_pktx_cnts_s cn61xx; + struct cvmx_sli_pktx_cnts_s cn63xx; + struct cvmx_sli_pktx_cnts_s cn63xxp1; + struct cvmx_sli_pktx_cnts_s cn66xx; + struct cvmx_sli_pktx_cnts_s cn68xx; + struct cvmx_sli_pktx_cnts_s cn68xxp1; +}; + +union cvmx_sli_pktx_in_bp { + uint64_t u64; + struct cvmx_sli_pktx_in_bp_s { + uint64_t wmark:32; + uint64_t cnt:32; + } s; + struct cvmx_sli_pktx_in_bp_s cn61xx; + struct cvmx_sli_pktx_in_bp_s cn63xx; + struct cvmx_sli_pktx_in_bp_s cn63xxp1; + struct cvmx_sli_pktx_in_bp_s cn66xx; +}; + +union cvmx_sli_pktx_instr_baddr { + uint64_t u64; + struct cvmx_sli_pktx_instr_baddr_s { + uint64_t addr:61; + uint64_t reserved_0_2:3; + } s; + struct cvmx_sli_pktx_instr_baddr_s cn61xx; + struct cvmx_sli_pktx_instr_baddr_s cn63xx; + struct cvmx_sli_pktx_instr_baddr_s cn63xxp1; + struct cvmx_sli_pktx_instr_baddr_s cn66xx; + struct cvmx_sli_pktx_instr_baddr_s cn68xx; + struct cvmx_sli_pktx_instr_baddr_s cn68xxp1; +}; + +union cvmx_sli_pktx_instr_baoff_dbell { + uint64_t u64; + struct cvmx_sli_pktx_instr_baoff_dbell_s { + uint64_t aoff:32; + uint64_t dbell:32; + } s; + struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx; + struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx; + struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1; + struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx; + struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx; + struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1; +}; + +union cvmx_sli_pktx_instr_fifo_rsize { + uint64_t u64; + struct cvmx_sli_pktx_instr_fifo_rsize_s { + uint64_t max:9; + uint64_t rrp:9; + uint64_t wrp:9; + uint64_t fcnt:5; + uint64_t rsize:32; + } s; + struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx; + struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx; + struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1; + struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx; + struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx; + struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1; +}; + +union cvmx_sli_pktx_instr_header { + uint64_t u64; + struct cvmx_sli_pktx_instr_header_s { + uint64_t reserved_44_63:20; + uint64_t pbp:1; + uint64_t reserved_38_42:5; + uint64_t rparmode:2; + uint64_t reserved_35_35:1; + uint64_t rskp_len:7; + uint64_t rngrpext:2; + uint64_t rnqos:1; + uint64_t rngrp:1; + uint64_t rntt:1; + uint64_t rntag:1; + uint64_t use_ihdr:1; + uint64_t reserved_16_20:5; + uint64_t par_mode:2; + uint64_t reserved_13_13:1; + uint64_t skp_len:7; + uint64_t ngrpext:2; + uint64_t nqos:1; + uint64_t ngrp:1; + uint64_t ntt:1; + uint64_t ntag:1; + } s; + struct cvmx_sli_pktx_instr_header_cn61xx { + uint64_t reserved_44_63:20; + uint64_t pbp:1; + uint64_t reserved_38_42:5; + uint64_t rparmode:2; + uint64_t reserved_35_35:1; + uint64_t rskp_len:7; + uint64_t reserved_26_27:2; + uint64_t rnqos:1; + uint64_t rngrp:1; + uint64_t rntt:1; + uint64_t rntag:1; + uint64_t use_ihdr:1; + uint64_t reserved_16_20:5; + uint64_t par_mode:2; + uint64_t reserved_13_13:1; + uint64_t skp_len:7; + uint64_t reserved_4_5:2; + uint64_t nqos:1; + uint64_t ngrp:1; + uint64_t ntt:1; + uint64_t ntag:1; + } cn61xx; + struct cvmx_sli_pktx_instr_header_cn61xx cn63xx; + struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1; + struct cvmx_sli_pktx_instr_header_cn61xx cn66xx; + struct cvmx_sli_pktx_instr_header_s cn68xx; + struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1; +}; + +union cvmx_sli_pktx_out_size { + uint64_t u64; + struct cvmx_sli_pktx_out_size_s { + uint64_t reserved_23_63:41; + uint64_t isize:7; + uint64_t bsize:16; + } s; + struct cvmx_sli_pktx_out_size_s cn61xx; + struct cvmx_sli_pktx_out_size_s cn63xx; + struct cvmx_sli_pktx_out_size_s cn63xxp1; + struct cvmx_sli_pktx_out_size_s cn66xx; + struct cvmx_sli_pktx_out_size_s cn68xx; + struct cvmx_sli_pktx_out_size_s cn68xxp1; +}; + +union cvmx_sli_pktx_slist_baddr { + uint64_t u64; + struct cvmx_sli_pktx_slist_baddr_s { + uint64_t addr:60; + uint64_t reserved_0_3:4; + } s; + struct cvmx_sli_pktx_slist_baddr_s cn61xx; + struct cvmx_sli_pktx_slist_baddr_s cn63xx; + struct cvmx_sli_pktx_slist_baddr_s cn63xxp1; + struct cvmx_sli_pktx_slist_baddr_s cn66xx; + struct cvmx_sli_pktx_slist_baddr_s cn68xx; + struct cvmx_sli_pktx_slist_baddr_s cn68xxp1; +}; + +union cvmx_sli_pktx_slist_baoff_dbell { + uint64_t u64; + struct cvmx_sli_pktx_slist_baoff_dbell_s { + uint64_t aoff:32; + uint64_t dbell:32; + } s; + struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx; + struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx; + struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1; + struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx; + struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx; + struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1; +}; + +union cvmx_sli_pktx_slist_fifo_rsize { + uint64_t u64; + struct cvmx_sli_pktx_slist_fifo_rsize_s { + uint64_t reserved_32_63:32; + uint64_t rsize:32; + } s; + struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx; + struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx; + struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1; + struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx; + struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx; + struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1; +}; + +union cvmx_sli_pkt_cnt_int { + uint64_t u64; + struct cvmx_sli_pkt_cnt_int_s { + uint64_t reserved_32_63:32; + uint64_t port:32; + } s; + struct cvmx_sli_pkt_cnt_int_s cn61xx; + struct cvmx_sli_pkt_cnt_int_s cn63xx; + struct cvmx_sli_pkt_cnt_int_s cn63xxp1; + struct cvmx_sli_pkt_cnt_int_s cn66xx; + struct cvmx_sli_pkt_cnt_int_s cn68xx; + struct cvmx_sli_pkt_cnt_int_s cn68xxp1; +}; + +union cvmx_sli_pkt_cnt_int_enb { + uint64_t u64; + struct cvmx_sli_pkt_cnt_int_enb_s { + uint64_t reserved_32_63:32; + uint64_t port:32; + } s; + struct cvmx_sli_pkt_cnt_int_enb_s cn61xx; + struct cvmx_sli_pkt_cnt_int_enb_s cn63xx; + struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1; + struct cvmx_sli_pkt_cnt_int_enb_s cn66xx; + struct cvmx_sli_pkt_cnt_int_enb_s cn68xx; + struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1; +}; + +union cvmx_sli_pkt_ctl { + uint64_t u64; + struct cvmx_sli_pkt_ctl_s { + uint64_t reserved_5_63:59; + uint64_t ring_en:1; + uint64_t pkt_bp:4; + } s; + struct cvmx_sli_pkt_ctl_s cn61xx; + struct cvmx_sli_pkt_ctl_s cn63xx; + struct cvmx_sli_pkt_ctl_s cn63xxp1; + struct cvmx_sli_pkt_ctl_s cn66xx; + struct cvmx_sli_pkt_ctl_s cn68xx; + struct cvmx_sli_pkt_ctl_s cn68xxp1; +}; + +union cvmx_sli_pkt_data_out_es { + uint64_t u64; + struct cvmx_sli_pkt_data_out_es_s { + uint64_t es:64; + } s; + struct cvmx_sli_pkt_data_out_es_s cn61xx; + struct cvmx_sli_pkt_data_out_es_s cn63xx; + struct cvmx_sli_pkt_data_out_es_s cn63xxp1; + struct cvmx_sli_pkt_data_out_es_s cn66xx; + struct cvmx_sli_pkt_data_out_es_s cn68xx; + struct cvmx_sli_pkt_data_out_es_s cn68xxp1; +}; + +union cvmx_sli_pkt_data_out_ns { + uint64_t u64; + struct cvmx_sli_pkt_data_out_ns_s { + uint64_t reserved_32_63:32; + uint64_t nsr:32; + } s; + struct cvmx_sli_pkt_data_out_ns_s cn61xx; + struct cvmx_sli_pkt_data_out_ns_s cn63xx; + struct cvmx_sli_pkt_data_out_ns_s cn63xxp1; + struct cvmx_sli_pkt_data_out_ns_s cn66xx; + struct cvmx_sli_pkt_data_out_ns_s cn68xx; + struct cvmx_sli_pkt_data_out_ns_s cn68xxp1; +}; + +union cvmx_sli_pkt_data_out_ror { + uint64_t u64; + struct cvmx_sli_pkt_data_out_ror_s { + uint64_t reserved_32_63:32; + uint64_t ror:32; + } s; + struct cvmx_sli_pkt_data_out_ror_s cn61xx; + struct cvmx_sli_pkt_data_out_ror_s cn63xx; + struct cvmx_sli_pkt_data_out_ror_s cn63xxp1; + struct cvmx_sli_pkt_data_out_ror_s cn66xx; + struct cvmx_sli_pkt_data_out_ror_s cn68xx; + struct cvmx_sli_pkt_data_out_ror_s cn68xxp1; +}; + +union cvmx_sli_pkt_dpaddr { + uint64_t u64; + struct cvmx_sli_pkt_dpaddr_s { + uint64_t reserved_32_63:32; + uint64_t dptr:32; + } s; + struct cvmx_sli_pkt_dpaddr_s cn61xx; + struct cvmx_sli_pkt_dpaddr_s cn63xx; + struct cvmx_sli_pkt_dpaddr_s cn63xxp1; + struct cvmx_sli_pkt_dpaddr_s cn66xx; + struct cvmx_sli_pkt_dpaddr_s cn68xx; + struct cvmx_sli_pkt_dpaddr_s cn68xxp1; +}; + +union cvmx_sli_pkt_in_bp { + uint64_t u64; + struct cvmx_sli_pkt_in_bp_s { + uint64_t reserved_32_63:32; + uint64_t bp:32; + } s; + struct cvmx_sli_pkt_in_bp_s cn61xx; + struct cvmx_sli_pkt_in_bp_s cn63xx; + struct cvmx_sli_pkt_in_bp_s cn63xxp1; + struct cvmx_sli_pkt_in_bp_s cn66xx; +}; + +union cvmx_sli_pkt_in_donex_cnts { + uint64_t u64; + struct cvmx_sli_pkt_in_donex_cnts_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_sli_pkt_in_donex_cnts_s cn61xx; + struct cvmx_sli_pkt_in_donex_cnts_s cn63xx; + struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1; + struct cvmx_sli_pkt_in_donex_cnts_s cn66xx; + struct cvmx_sli_pkt_in_donex_cnts_s cn68xx; + struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1; +}; + +union cvmx_sli_pkt_in_instr_counts { + uint64_t u64; + struct cvmx_sli_pkt_in_instr_counts_s { + uint64_t wr_cnt:32; + uint64_t rd_cnt:32; + } s; + struct cvmx_sli_pkt_in_instr_counts_s cn61xx; + struct cvmx_sli_pkt_in_instr_counts_s cn63xx; + struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1; + struct cvmx_sli_pkt_in_instr_counts_s cn66xx; + struct cvmx_sli_pkt_in_instr_counts_s cn68xx; + struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1; +}; + +union cvmx_sli_pkt_in_pcie_port { + uint64_t u64; + struct cvmx_sli_pkt_in_pcie_port_s { + uint64_t pp:64; + } s; + struct cvmx_sli_pkt_in_pcie_port_s cn61xx; + struct cvmx_sli_pkt_in_pcie_port_s cn63xx; + struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1; + struct cvmx_sli_pkt_in_pcie_port_s cn66xx; + struct cvmx_sli_pkt_in_pcie_port_s cn68xx; + struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1; +}; + +union cvmx_sli_pkt_input_control { + uint64_t u64; + struct cvmx_sli_pkt_input_control_s { + uint64_t prd_erst:1; + uint64_t prd_rds:7; + uint64_t gii_erst:1; + uint64_t gii_rds:7; + uint64_t reserved_41_47:7; + uint64_t prc_idle:1; + uint64_t reserved_24_39:16; + uint64_t pin_rst:1; + uint64_t pkt_rr:1; + uint64_t pbp_dhi:13; + uint64_t d_nsr:1; + uint64_t d_esr:2; + uint64_t d_ror:1; + uint64_t use_csr:1; + uint64_t nsr:1; + uint64_t esr:2; + uint64_t ror:1; + } s; + struct cvmx_sli_pkt_input_control_s cn61xx; + struct cvmx_sli_pkt_input_control_cn63xx { + uint64_t reserved_23_63:41; + uint64_t pkt_rr:1; + uint64_t pbp_dhi:13; + uint64_t d_nsr:1; + uint64_t d_esr:2; + uint64_t d_ror:1; + uint64_t use_csr:1; + uint64_t nsr:1; + uint64_t esr:2; + uint64_t ror:1; + } cn63xx; + struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1; + struct cvmx_sli_pkt_input_control_s cn66xx; + struct cvmx_sli_pkt_input_control_s cn68xx; + struct cvmx_sli_pkt_input_control_s cn68xxp1; +}; + +union cvmx_sli_pkt_instr_enb { + uint64_t u64; + struct cvmx_sli_pkt_instr_enb_s { + uint64_t reserved_32_63:32; + uint64_t enb:32; + } s; + struct cvmx_sli_pkt_instr_enb_s cn61xx; + struct cvmx_sli_pkt_instr_enb_s cn63xx; + struct cvmx_sli_pkt_instr_enb_s cn63xxp1; + struct cvmx_sli_pkt_instr_enb_s cn66xx; + struct cvmx_sli_pkt_instr_enb_s cn68xx; + struct cvmx_sli_pkt_instr_enb_s cn68xxp1; +}; + +union cvmx_sli_pkt_instr_rd_size { + uint64_t u64; + struct cvmx_sli_pkt_instr_rd_size_s { + uint64_t rdsize:64; + } s; + struct cvmx_sli_pkt_instr_rd_size_s cn61xx; + struct cvmx_sli_pkt_instr_rd_size_s cn63xx; + struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1; + struct cvmx_sli_pkt_instr_rd_size_s cn66xx; + struct cvmx_sli_pkt_instr_rd_size_s cn68xx; + struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1; +}; + +union cvmx_sli_pkt_instr_size { + uint64_t u64; + struct cvmx_sli_pkt_instr_size_s { + uint64_t reserved_32_63:32; + uint64_t is_64b:32; + } s; + struct cvmx_sli_pkt_instr_size_s cn61xx; + struct cvmx_sli_pkt_instr_size_s cn63xx; + struct cvmx_sli_pkt_instr_size_s cn63xxp1; + struct cvmx_sli_pkt_instr_size_s cn66xx; + struct cvmx_sli_pkt_instr_size_s cn68xx; + struct cvmx_sli_pkt_instr_size_s cn68xxp1; +}; + +union cvmx_sli_pkt_int_levels { + uint64_t u64; + struct cvmx_sli_pkt_int_levels_s { + uint64_t reserved_54_63:10; + uint64_t time:22; + uint64_t cnt:32; + } s; + struct cvmx_sli_pkt_int_levels_s cn61xx; + struct cvmx_sli_pkt_int_levels_s cn63xx; + struct cvmx_sli_pkt_int_levels_s cn63xxp1; + struct cvmx_sli_pkt_int_levels_s cn66xx; + struct cvmx_sli_pkt_int_levels_s cn68xx; + struct cvmx_sli_pkt_int_levels_s cn68xxp1; +}; + +union cvmx_sli_pkt_iptr { + uint64_t u64; + struct cvmx_sli_pkt_iptr_s { + uint64_t reserved_32_63:32; + uint64_t iptr:32; + } s; + struct cvmx_sli_pkt_iptr_s cn61xx; + struct cvmx_sli_pkt_iptr_s cn63xx; + struct cvmx_sli_pkt_iptr_s cn63xxp1; + struct cvmx_sli_pkt_iptr_s cn66xx; + struct cvmx_sli_pkt_iptr_s cn68xx; + struct cvmx_sli_pkt_iptr_s cn68xxp1; +}; + +union cvmx_sli_pkt_out_bmode { + uint64_t u64; + struct cvmx_sli_pkt_out_bmode_s { + uint64_t reserved_32_63:32; + uint64_t bmode:32; + } s; + struct cvmx_sli_pkt_out_bmode_s cn61xx; + struct cvmx_sli_pkt_out_bmode_s cn63xx; + struct cvmx_sli_pkt_out_bmode_s cn63xxp1; + struct cvmx_sli_pkt_out_bmode_s cn66xx; + struct cvmx_sli_pkt_out_bmode_s cn68xx; + struct cvmx_sli_pkt_out_bmode_s cn68xxp1; +}; + +union cvmx_sli_pkt_out_bp_en { + uint64_t u64; + struct cvmx_sli_pkt_out_bp_en_s { + uint64_t reserved_32_63:32; + uint64_t bp_en:32; + } s; + struct cvmx_sli_pkt_out_bp_en_s cn68xx; + struct cvmx_sli_pkt_out_bp_en_s cn68xxp1; +}; + +union cvmx_sli_pkt_out_enb { + uint64_t u64; + struct cvmx_sli_pkt_out_enb_s { + uint64_t reserved_32_63:32; + uint64_t enb:32; + } s; + struct cvmx_sli_pkt_out_enb_s cn61xx; + struct cvmx_sli_pkt_out_enb_s cn63xx; + struct cvmx_sli_pkt_out_enb_s cn63xxp1; + struct cvmx_sli_pkt_out_enb_s cn66xx; + struct cvmx_sli_pkt_out_enb_s cn68xx; + struct cvmx_sli_pkt_out_enb_s cn68xxp1; +}; + +union cvmx_sli_pkt_output_wmark { + uint64_t u64; + struct cvmx_sli_pkt_output_wmark_s { + uint64_t reserved_32_63:32; + uint64_t wmark:32; + } s; + struct cvmx_sli_pkt_output_wmark_s cn61xx; + struct cvmx_sli_pkt_output_wmark_s cn63xx; + struct cvmx_sli_pkt_output_wmark_s cn63xxp1; + struct cvmx_sli_pkt_output_wmark_s cn66xx; + struct cvmx_sli_pkt_output_wmark_s cn68xx; + struct cvmx_sli_pkt_output_wmark_s cn68xxp1; +}; + +union cvmx_sli_pkt_pcie_port { + uint64_t u64; + struct cvmx_sli_pkt_pcie_port_s { + uint64_t pp:64; + } s; + struct cvmx_sli_pkt_pcie_port_s cn61xx; + struct cvmx_sli_pkt_pcie_port_s cn63xx; + struct cvmx_sli_pkt_pcie_port_s cn63xxp1; + struct cvmx_sli_pkt_pcie_port_s cn66xx; + struct cvmx_sli_pkt_pcie_port_s cn68xx; + struct cvmx_sli_pkt_pcie_port_s cn68xxp1; +}; + +union cvmx_sli_pkt_port_in_rst { + uint64_t u64; + struct cvmx_sli_pkt_port_in_rst_s { + uint64_t in_rst:32; + uint64_t out_rst:32; + } s; + struct cvmx_sli_pkt_port_in_rst_s cn61xx; + struct cvmx_sli_pkt_port_in_rst_s cn63xx; + struct cvmx_sli_pkt_port_in_rst_s cn63xxp1; + struct cvmx_sli_pkt_port_in_rst_s cn66xx; + struct cvmx_sli_pkt_port_in_rst_s cn68xx; + struct cvmx_sli_pkt_port_in_rst_s cn68xxp1; +}; + +union cvmx_sli_pkt_slist_es { + uint64_t u64; + struct cvmx_sli_pkt_slist_es_s { + uint64_t es:64; + } s; + struct cvmx_sli_pkt_slist_es_s cn61xx; + struct cvmx_sli_pkt_slist_es_s cn63xx; + struct cvmx_sli_pkt_slist_es_s cn63xxp1; + struct cvmx_sli_pkt_slist_es_s cn66xx; + struct cvmx_sli_pkt_slist_es_s cn68xx; + struct cvmx_sli_pkt_slist_es_s cn68xxp1; +}; + +union cvmx_sli_pkt_slist_ns { + uint64_t u64; + struct cvmx_sli_pkt_slist_ns_s { + uint64_t reserved_32_63:32; + uint64_t nsr:32; + } s; + struct cvmx_sli_pkt_slist_ns_s cn61xx; + struct cvmx_sli_pkt_slist_ns_s cn63xx; + struct cvmx_sli_pkt_slist_ns_s cn63xxp1; + struct cvmx_sli_pkt_slist_ns_s cn66xx; + struct cvmx_sli_pkt_slist_ns_s cn68xx; + struct cvmx_sli_pkt_slist_ns_s cn68xxp1; +}; + +union cvmx_sli_pkt_slist_ror { + uint64_t u64; + struct cvmx_sli_pkt_slist_ror_s { + uint64_t reserved_32_63:32; + uint64_t ror:32; + } s; + struct cvmx_sli_pkt_slist_ror_s cn61xx; + struct cvmx_sli_pkt_slist_ror_s cn63xx; + struct cvmx_sli_pkt_slist_ror_s cn63xxp1; + struct cvmx_sli_pkt_slist_ror_s cn66xx; + struct cvmx_sli_pkt_slist_ror_s cn68xx; + struct cvmx_sli_pkt_slist_ror_s cn68xxp1; +}; + +union cvmx_sli_pkt_time_int { + uint64_t u64; + struct cvmx_sli_pkt_time_int_s { + uint64_t reserved_32_63:32; + uint64_t port:32; + } s; + struct cvmx_sli_pkt_time_int_s cn61xx; + struct cvmx_sli_pkt_time_int_s cn63xx; + struct cvmx_sli_pkt_time_int_s cn63xxp1; + struct cvmx_sli_pkt_time_int_s cn66xx; + struct cvmx_sli_pkt_time_int_s cn68xx; + struct cvmx_sli_pkt_time_int_s cn68xxp1; +}; + +union cvmx_sli_pkt_time_int_enb { + uint64_t u64; + struct cvmx_sli_pkt_time_int_enb_s { + uint64_t reserved_32_63:32; + uint64_t port:32; + } s; + struct cvmx_sli_pkt_time_int_enb_s cn61xx; + struct cvmx_sli_pkt_time_int_enb_s cn63xx; + struct cvmx_sli_pkt_time_int_enb_s cn63xxp1; + struct cvmx_sli_pkt_time_int_enb_s cn66xx; + struct cvmx_sli_pkt_time_int_enb_s cn68xx; + struct cvmx_sli_pkt_time_int_enb_s cn68xxp1; +}; + +union cvmx_sli_portx_pkind { + uint64_t u64; + struct cvmx_sli_portx_pkind_s { + uint64_t reserved_25_63:39; + uint64_t rpk_enb:1; + uint64_t reserved_22_23:2; + uint64_t pkindr:6; + uint64_t reserved_14_15:2; + uint64_t bpkind:6; + uint64_t reserved_6_7:2; + uint64_t pkind:6; + } s; + struct cvmx_sli_portx_pkind_s cn68xx; + struct cvmx_sli_portx_pkind_cn68xxp1 { + uint64_t reserved_14_63:50; + uint64_t bpkind:6; + uint64_t reserved_6_7:2; + uint64_t pkind:6; + } cn68xxp1; +}; + +union cvmx_sli_s2m_portx_ctl { + uint64_t u64; + struct cvmx_sli_s2m_portx_ctl_s { + uint64_t reserved_5_63:59; + uint64_t wind_d:1; + uint64_t bar0_d:1; + uint64_t mrrs:3; + } s; + struct cvmx_sli_s2m_portx_ctl_s cn61xx; + struct cvmx_sli_s2m_portx_ctl_s cn63xx; + struct cvmx_sli_s2m_portx_ctl_s cn63xxp1; + struct cvmx_sli_s2m_portx_ctl_s cn66xx; + struct cvmx_sli_s2m_portx_ctl_s cn68xx; + struct cvmx_sli_s2m_portx_ctl_s cn68xxp1; +}; + +union cvmx_sli_scratch_1 { + uint64_t u64; + struct cvmx_sli_scratch_1_s { + uint64_t data:64; + } s; + struct cvmx_sli_scratch_1_s cn61xx; + struct cvmx_sli_scratch_1_s cn63xx; + struct cvmx_sli_scratch_1_s cn63xxp1; + struct cvmx_sli_scratch_1_s cn66xx; + struct cvmx_sli_scratch_1_s cn68xx; + struct cvmx_sli_scratch_1_s cn68xxp1; +}; + +union cvmx_sli_scratch_2 { + uint64_t u64; + struct cvmx_sli_scratch_2_s { + uint64_t data:64; + } s; + struct cvmx_sli_scratch_2_s cn61xx; + struct cvmx_sli_scratch_2_s cn63xx; + struct cvmx_sli_scratch_2_s cn63xxp1; + struct cvmx_sli_scratch_2_s cn66xx; + struct cvmx_sli_scratch_2_s cn68xx; + struct cvmx_sli_scratch_2_s cn68xxp1; +}; + +union cvmx_sli_state1 { + uint64_t u64; + struct cvmx_sli_state1_s { + uint64_t cpl1:12; + uint64_t cpl0:12; + uint64_t arb:1; + uint64_t csr:39; + } s; + struct cvmx_sli_state1_s cn61xx; + struct cvmx_sli_state1_s cn63xx; + struct cvmx_sli_state1_s cn63xxp1; + struct cvmx_sli_state1_s cn66xx; + struct cvmx_sli_state1_s cn68xx; + struct cvmx_sli_state1_s cn68xxp1; +}; + +union cvmx_sli_state2 { + uint64_t u64; + struct cvmx_sli_state2_s { + uint64_t reserved_56_63:8; + uint64_t nnp1:8; + uint64_t reserved_47_47:1; + uint64_t rac:1; + uint64_t csm1:15; + uint64_t csm0:15; + uint64_t nnp0:8; + uint64_t nnd:8; + } s; + struct cvmx_sli_state2_s cn61xx; + struct cvmx_sli_state2_s cn63xx; + struct cvmx_sli_state2_s cn63xxp1; + struct cvmx_sli_state2_s cn66xx; + struct cvmx_sli_state2_s cn68xx; + struct cvmx_sli_state2_s cn68xxp1; +}; + +union cvmx_sli_state3 { + uint64_t u64; + struct cvmx_sli_state3_s { + uint64_t reserved_56_63:8; + uint64_t psm1:15; + uint64_t psm0:15; + uint64_t nsm1:13; + uint64_t nsm0:13; + } s; + struct cvmx_sli_state3_s cn61xx; + struct cvmx_sli_state3_s cn63xx; + struct cvmx_sli_state3_s cn63xxp1; + struct cvmx_sli_state3_s cn66xx; + struct cvmx_sli_state3_s cn68xx; + struct cvmx_sli_state3_s cn68xxp1; +}; + +union cvmx_sli_tx_pipe { + uint64_t u64; + struct cvmx_sli_tx_pipe_s { + uint64_t reserved_24_63:40; + uint64_t nump:8; + uint64_t reserved_7_15:9; + uint64_t base:7; + } s; + struct cvmx_sli_tx_pipe_s cn68xx; + struct cvmx_sli_tx_pipe_s cn68xxp1; +}; + +union cvmx_sli_win_rd_addr { + uint64_t u64; + struct cvmx_sli_win_rd_addr_s { + uint64_t reserved_51_63:13; + uint64_t ld_cmd:2; + uint64_t iobit:1; + uint64_t rd_addr:48; + } s; + struct cvmx_sli_win_rd_addr_s cn61xx; + struct cvmx_sli_win_rd_addr_s cn63xx; + struct cvmx_sli_win_rd_addr_s cn63xxp1; + struct cvmx_sli_win_rd_addr_s cn66xx; + struct cvmx_sli_win_rd_addr_s cn68xx; + struct cvmx_sli_win_rd_addr_s cn68xxp1; +}; + +union cvmx_sli_win_rd_data { + uint64_t u64; + struct cvmx_sli_win_rd_data_s { + uint64_t rd_data:64; + } s; + struct cvmx_sli_win_rd_data_s cn61xx; + struct cvmx_sli_win_rd_data_s cn63xx; + struct cvmx_sli_win_rd_data_s cn63xxp1; + struct cvmx_sli_win_rd_data_s cn66xx; + struct cvmx_sli_win_rd_data_s cn68xx; + struct cvmx_sli_win_rd_data_s cn68xxp1; +}; + +union cvmx_sli_win_wr_addr { + uint64_t u64; + struct cvmx_sli_win_wr_addr_s { + uint64_t reserved_49_63:15; + uint64_t iobit:1; + uint64_t wr_addr:45; + uint64_t reserved_0_2:3; + } s; + struct cvmx_sli_win_wr_addr_s cn61xx; + struct cvmx_sli_win_wr_addr_s cn63xx; + struct cvmx_sli_win_wr_addr_s cn63xxp1; + struct cvmx_sli_win_wr_addr_s cn66xx; + struct cvmx_sli_win_wr_addr_s cn68xx; + struct cvmx_sli_win_wr_addr_s cn68xxp1; +}; + +union cvmx_sli_win_wr_data { + uint64_t u64; + struct cvmx_sli_win_wr_data_s { + uint64_t wr_data:64; + } s; + struct cvmx_sli_win_wr_data_s cn61xx; + struct cvmx_sli_win_wr_data_s cn63xx; + struct cvmx_sli_win_wr_data_s cn63xxp1; + struct cvmx_sli_win_wr_data_s cn66xx; + struct cvmx_sli_win_wr_data_s cn68xx; + struct cvmx_sli_win_wr_data_s cn68xxp1; +}; + +union cvmx_sli_win_wr_mask { + uint64_t u64; + struct cvmx_sli_win_wr_mask_s { + uint64_t reserved_8_63:56; + uint64_t wr_mask:8; + } s; + struct cvmx_sli_win_wr_mask_s cn61xx; + struct cvmx_sli_win_wr_mask_s cn63xx; + struct cvmx_sli_win_wr_mask_s cn63xxp1; + struct cvmx_sli_win_wr_mask_s cn66xx; + struct cvmx_sli_win_wr_mask_s cn68xx; + struct cvmx_sli_win_wr_mask_s cn68xxp1; +}; + +union cvmx_sli_window_ctl { + uint64_t u64; + struct cvmx_sli_window_ctl_s { + uint64_t reserved_32_63:32; + uint64_t time:32; + } s; + struct cvmx_sli_window_ctl_s cn61xx; + struct cvmx_sli_window_ctl_s cn63xx; + struct cvmx_sli_window_ctl_s cn63xxp1; + struct cvmx_sli_window_ctl_s cn66xx; + struct cvmx_sli_window_ctl_s cn68xx; + struct cvmx_sli_window_ctl_s cn68xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h new file mode 100644 index 000000000000..7be7e9ed7465 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h @@ -0,0 +1,1036 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2011 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SRIOX_DEFS_H__ +#define __CVMX_SRIOX_DEFS_H__ + +#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull) + +union cvmx_sriox_acc_ctrl { + uint64_t u64; + struct cvmx_sriox_acc_ctrl_s { + uint64_t reserved_7_63:57; + uint64_t deny_adr2:1; + uint64_t deny_adr1:1; + uint64_t deny_adr0:1; + uint64_t reserved_3_3:1; + uint64_t deny_bar2:1; + uint64_t deny_bar1:1; + uint64_t deny_bar0:1; + } s; + struct cvmx_sriox_acc_ctrl_cn63xx { + uint64_t reserved_3_63:61; + uint64_t deny_bar2:1; + uint64_t deny_bar1:1; + uint64_t deny_bar0:1; + } cn63xx; + struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1; + struct cvmx_sriox_acc_ctrl_s cn66xx; +}; + +union cvmx_sriox_asmbly_id { + uint64_t u64; + struct cvmx_sriox_asmbly_id_s { + uint64_t reserved_32_63:32; + uint64_t assy_id:16; + uint64_t assy_ven:16; + } s; + struct cvmx_sriox_asmbly_id_s cn63xx; + struct cvmx_sriox_asmbly_id_s cn63xxp1; + struct cvmx_sriox_asmbly_id_s cn66xx; +}; + +union cvmx_sriox_asmbly_info { + uint64_t u64; + struct cvmx_sriox_asmbly_info_s { + uint64_t reserved_32_63:32; + uint64_t assy_rev:16; + uint64_t reserved_0_15:16; + } s; + struct cvmx_sriox_asmbly_info_s cn63xx; + struct cvmx_sriox_asmbly_info_s cn63xxp1; + struct cvmx_sriox_asmbly_info_s cn66xx; +}; + +union cvmx_sriox_bell_resp_ctrl { + uint64_t u64; + struct cvmx_sriox_bell_resp_ctrl_s { + uint64_t reserved_6_63:58; + uint64_t rp1_sid:1; + uint64_t rp0_sid:2; + uint64_t rp1_pid:1; + uint64_t rp0_pid:2; + } s; + struct cvmx_sriox_bell_resp_ctrl_s cn63xx; + struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; + struct cvmx_sriox_bell_resp_ctrl_s cn66xx; +}; + +union cvmx_sriox_bist_status { + uint64_t u64; + struct cvmx_sriox_bist_status_s { + uint64_t reserved_45_63:19; + uint64_t lram:1; + uint64_t mram:2; + uint64_t cram:2; + uint64_t bell:2; + uint64_t otag:2; + uint64_t itag:1; + uint64_t ofree:1; + uint64_t rtn:2; + uint64_t obulk:4; + uint64_t optrs:4; + uint64_t oarb2:2; + uint64_t rxbuf2:2; + uint64_t oarb:2; + uint64_t ispf:1; + uint64_t ospf:1; + uint64_t txbuf:2; + uint64_t rxbuf:2; + uint64_t imsg:5; + uint64_t omsg:7; + } s; + struct cvmx_sriox_bist_status_cn63xx { + uint64_t reserved_44_63:20; + uint64_t mram:2; + uint64_t cram:2; + uint64_t bell:2; + uint64_t otag:2; + uint64_t itag:1; + uint64_t ofree:1; + uint64_t rtn:2; + uint64_t obulk:4; + uint64_t optrs:4; + uint64_t oarb2:2; + uint64_t rxbuf2:2; + uint64_t oarb:2; + uint64_t ispf:1; + uint64_t ospf:1; + uint64_t txbuf:2; + uint64_t rxbuf:2; + uint64_t imsg:5; + uint64_t omsg:7; + } cn63xx; + struct cvmx_sriox_bist_status_cn63xxp1 { + uint64_t reserved_44_63:20; + uint64_t mram:2; + uint64_t cram:2; + uint64_t bell:2; + uint64_t otag:2; + uint64_t itag:1; + uint64_t ofree:1; + uint64_t rtn:2; + uint64_t obulk:4; + uint64_t optrs:4; + uint64_t reserved_20_23:4; + uint64_t oarb:2; + uint64_t ispf:1; + uint64_t ospf:1; + uint64_t txbuf:2; + uint64_t rxbuf:2; + uint64_t imsg:5; + uint64_t omsg:7; + } cn63xxp1; + struct cvmx_sriox_bist_status_s cn66xx; +}; + +union cvmx_sriox_imsg_ctrl { + uint64_t u64; + struct cvmx_sriox_imsg_ctrl_s { + uint64_t reserved_32_63:32; + uint64_t to_mode:1; + uint64_t reserved_30_30:1; + uint64_t rsp_thr:6; + uint64_t reserved_22_23:2; + uint64_t rp1_sid:1; + uint64_t rp0_sid:2; + uint64_t rp1_pid:1; + uint64_t rp0_pid:2; + uint64_t reserved_15_15:1; + uint64_t prt_sel:3; + uint64_t lttr:4; + uint64_t prio:4; + uint64_t mbox:4; + } s; + struct cvmx_sriox_imsg_ctrl_s cn63xx; + struct cvmx_sriox_imsg_ctrl_s cn63xxp1; + struct cvmx_sriox_imsg_ctrl_s cn66xx; +}; + +union cvmx_sriox_imsg_inst_hdrx { + uint64_t u64; + struct cvmx_sriox_imsg_inst_hdrx_s { + uint64_t r:1; + uint64_t reserved_58_62:5; + uint64_t pm:2; + uint64_t reserved_55_55:1; + uint64_t sl:7; + uint64_t reserved_46_47:2; + uint64_t nqos:1; + uint64_t ngrp:1; + uint64_t ntt:1; + uint64_t ntag:1; + uint64_t reserved_35_41:7; + uint64_t rs:1; + uint64_t tt:2; + uint64_t tag:32; + } s; + struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; + struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; + struct cvmx_sriox_imsg_inst_hdrx_s cn66xx; +}; + +union cvmx_sriox_imsg_qos_grpx { + uint64_t u64; + struct cvmx_sriox_imsg_qos_grpx_s { + uint64_t reserved_63_63:1; + uint64_t qos7:3; + uint64_t grp7:4; + uint64_t reserved_55_55:1; + uint64_t qos6:3; + uint64_t grp6:4; + uint64_t reserved_47_47:1; + uint64_t qos5:3; + uint64_t grp5:4; + uint64_t reserved_39_39:1; + uint64_t qos4:3; + uint64_t grp4:4; + uint64_t reserved_31_31:1; + uint64_t qos3:3; + uint64_t grp3:4; + uint64_t reserved_23_23:1; + uint64_t qos2:3; + uint64_t grp2:4; + uint64_t reserved_15_15:1; + uint64_t qos1:3; + uint64_t grp1:4; + uint64_t reserved_7_7:1; + uint64_t qos0:3; + uint64_t grp0:4; + } s; + struct cvmx_sriox_imsg_qos_grpx_s cn63xx; + struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; + struct cvmx_sriox_imsg_qos_grpx_s cn66xx; +}; + +union cvmx_sriox_imsg_statusx { + uint64_t u64; + struct cvmx_sriox_imsg_statusx_s { + uint64_t val1:1; + uint64_t err1:1; + uint64_t toe1:1; + uint64_t toc1:1; + uint64_t prt1:1; + uint64_t reserved_58_58:1; + uint64_t tt1:1; + uint64_t dis1:1; + uint64_t seg1:4; + uint64_t mbox1:2; + uint64_t lttr1:2; + uint64_t sid1:16; + uint64_t val0:1; + uint64_t err0:1; + uint64_t toe0:1; + uint64_t toc0:1; + uint64_t prt0:1; + uint64_t reserved_26_26:1; + uint64_t tt0:1; + uint64_t dis0:1; + uint64_t seg0:4; + uint64_t mbox0:2; + uint64_t lttr0:2; + uint64_t sid0:16; + } s; + struct cvmx_sriox_imsg_statusx_s cn63xx; + struct cvmx_sriox_imsg_statusx_s cn63xxp1; + struct cvmx_sriox_imsg_statusx_s cn66xx; +}; + +union cvmx_sriox_imsg_vport_thr { + uint64_t u64; + struct cvmx_sriox_imsg_vport_thr_s { + uint64_t reserved_54_63:10; + uint64_t max_tot:6; + uint64_t reserved_46_47:2; + uint64_t max_s1:6; + uint64_t reserved_38_39:2; + uint64_t max_s0:6; + uint64_t sp_vport:1; + uint64_t reserved_20_30:11; + uint64_t buf_thr:4; + uint64_t reserved_14_15:2; + uint64_t max_p1:6; + uint64_t reserved_6_7:2; + uint64_t max_p0:6; + } s; + struct cvmx_sriox_imsg_vport_thr_s cn63xx; + struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; + struct cvmx_sriox_imsg_vport_thr_s cn66xx; +}; + +union cvmx_sriox_imsg_vport_thr2 { + uint64_t u64; + struct cvmx_sriox_imsg_vport_thr2_s { + uint64_t reserved_46_63:18; + uint64_t max_s3:6; + uint64_t reserved_38_39:2; + uint64_t max_s2:6; + uint64_t reserved_0_31:32; + } s; + struct cvmx_sriox_imsg_vport_thr2_s cn66xx; +}; + +union cvmx_sriox_int2_enable { + uint64_t u64; + struct cvmx_sriox_int2_enable_s { + uint64_t reserved_1_63:63; + uint64_t pko_rst:1; + } s; + struct cvmx_sriox_int2_enable_s cn63xx; + struct cvmx_sriox_int2_enable_s cn66xx; +}; + +union cvmx_sriox_int2_reg { + uint64_t u64; + struct cvmx_sriox_int2_reg_s { + uint64_t reserved_32_63:32; + uint64_t int_sum:1; + uint64_t reserved_1_30:30; + uint64_t pko_rst:1; + } s; + struct cvmx_sriox_int2_reg_s cn63xx; + struct cvmx_sriox_int2_reg_s cn66xx; +}; + +union cvmx_sriox_int_enable { + uint64_t u64; + struct cvmx_sriox_int_enable_s { + uint64_t reserved_27_63:37; + uint64_t zero_pkt:1; + uint64_t ttl_tout:1; + uint64_t fail:1; + uint64_t degrade:1; + uint64_t mac_buf:1; + uint64_t f_error:1; + uint64_t rtry_err:1; + uint64_t pko_err:1; + uint64_t omsg_err:1; + uint64_t omsg1:1; + uint64_t omsg0:1; + uint64_t link_up:1; + uint64_t link_dwn:1; + uint64_t phy_erb:1; + uint64_t log_erb:1; + uint64_t soft_rx:1; + uint64_t soft_tx:1; + uint64_t mce_rx:1; + uint64_t mce_tx:1; + uint64_t wr_done:1; + uint64_t sli_err:1; + uint64_t deny_wr:1; + uint64_t bar_err:1; + uint64_t maint_op:1; + uint64_t rxbell:1; + uint64_t bell_err:1; + uint64_t txbell:1; + } s; + struct cvmx_sriox_int_enable_s cn63xx; + struct cvmx_sriox_int_enable_cn63xxp1 { + uint64_t reserved_22_63:42; + uint64_t f_error:1; + uint64_t rtry_err:1; + uint64_t pko_err:1; + uint64_t omsg_err:1; + uint64_t omsg1:1; + uint64_t omsg0:1; + uint64_t link_up:1; + uint64_t link_dwn:1; + uint64_t phy_erb:1; + uint64_t log_erb:1; + uint64_t soft_rx:1; + uint64_t soft_tx:1; + uint64_t mce_rx:1; + uint64_t mce_tx:1; + uint64_t wr_done:1; + uint64_t sli_err:1; + uint64_t deny_wr:1; + uint64_t bar_err:1; + uint64_t maint_op:1; + uint64_t rxbell:1; + uint64_t bell_err:1; + uint64_t txbell:1; + } cn63xxp1; + struct cvmx_sriox_int_enable_s cn66xx; +}; + +union cvmx_sriox_int_info0 { + uint64_t u64; + struct cvmx_sriox_int_info0_s { + uint64_t cmd:4; + uint64_t type:4; + uint64_t tag:8; + uint64_t reserved_42_47:6; + uint64_t length:10; + uint64_t status:3; + uint64_t reserved_16_28:13; + uint64_t be0:8; + uint64_t be1:8; + } s; + struct cvmx_sriox_int_info0_s cn63xx; + struct cvmx_sriox_int_info0_s cn63xxp1; + struct cvmx_sriox_int_info0_s cn66xx; +}; + +union cvmx_sriox_int_info1 { + uint64_t u64; + struct cvmx_sriox_int_info1_s { + uint64_t info1:64; + } s; + struct cvmx_sriox_int_info1_s cn63xx; + struct cvmx_sriox_int_info1_s cn63xxp1; + struct cvmx_sriox_int_info1_s cn66xx; +}; + +union cvmx_sriox_int_info2 { + uint64_t u64; + struct cvmx_sriox_int_info2_s { + uint64_t prio:2; + uint64_t tt:1; + uint64_t sis:1; + uint64_t ssize:4; + uint64_t did:16; + uint64_t xmbox:4; + uint64_t mbox:2; + uint64_t letter:2; + uint64_t rsrvd:30; + uint64_t lns:1; + uint64_t intr:1; + } s; + struct cvmx_sriox_int_info2_s cn63xx; + struct cvmx_sriox_int_info2_s cn63xxp1; + struct cvmx_sriox_int_info2_s cn66xx; +}; + +union cvmx_sriox_int_info3 { + uint64_t u64; + struct cvmx_sriox_int_info3_s { + uint64_t prio:2; + uint64_t tt:2; + uint64_t type:4; + uint64_t other:48; + uint64_t reserved_0_7:8; + } s; + struct cvmx_sriox_int_info3_s cn63xx; + struct cvmx_sriox_int_info3_s cn63xxp1; + struct cvmx_sriox_int_info3_s cn66xx; +}; + +union cvmx_sriox_int_reg { + uint64_t u64; + struct cvmx_sriox_int_reg_s { + uint64_t reserved_32_63:32; + uint64_t int2_sum:1; + uint64_t reserved_27_30:4; + uint64_t zero_pkt:1; + uint64_t ttl_tout:1; + uint64_t fail:1; + uint64_t degrad:1; + uint64_t mac_buf:1; + uint64_t f_error:1; + uint64_t rtry_err:1; + uint64_t pko_err:1; + uint64_t omsg_err:1; + uint64_t omsg1:1; + uint64_t omsg0:1; + uint64_t link_up:1; + uint64_t link_dwn:1; + uint64_t phy_erb:1; + uint64_t log_erb:1; + uint64_t soft_rx:1; + uint64_t soft_tx:1; + uint64_t mce_rx:1; + uint64_t mce_tx:1; + uint64_t wr_done:1; + uint64_t sli_err:1; + uint64_t deny_wr:1; + uint64_t bar_err:1; + uint64_t maint_op:1; + uint64_t rxbell:1; + uint64_t bell_err:1; + uint64_t txbell:1; + } s; + struct cvmx_sriox_int_reg_s cn63xx; + struct cvmx_sriox_int_reg_cn63xxp1 { + uint64_t reserved_22_63:42; + uint64_t f_error:1; + uint64_t rtry_err:1; + uint64_t pko_err:1; + uint64_t omsg_err:1; + uint64_t omsg1:1; + uint64_t omsg0:1; + uint64_t link_up:1; + uint64_t link_dwn:1; + uint64_t phy_erb:1; + uint64_t log_erb:1; + uint64_t soft_rx:1; + uint64_t soft_tx:1; + uint64_t mce_rx:1; + uint64_t mce_tx:1; + uint64_t wr_done:1; + uint64_t sli_err:1; + uint64_t deny_wr:1; + uint64_t bar_err:1; + uint64_t maint_op:1; + uint64_t rxbell:1; + uint64_t bell_err:1; + uint64_t txbell:1; + } cn63xxp1; + struct cvmx_sriox_int_reg_s cn66xx; +}; + +union cvmx_sriox_ip_feature { + uint64_t u64; + struct cvmx_sriox_ip_feature_s { + uint64_t ops:32; + uint64_t reserved_15_31:17; + uint64_t no_vmin:1; + uint64_t a66:1; + uint64_t a50:1; + uint64_t reserved_11_11:1; + uint64_t tx_flow:1; + uint64_t pt_width:2; + uint64_t tx_pol:4; + uint64_t rx_pol:4; + } s; + struct cvmx_sriox_ip_feature_cn63xx { + uint64_t ops:32; + uint64_t reserved_14_31:18; + uint64_t a66:1; + uint64_t a50:1; + uint64_t reserved_11_11:1; + uint64_t tx_flow:1; + uint64_t pt_width:2; + uint64_t tx_pol:4; + uint64_t rx_pol:4; + } cn63xx; + struct cvmx_sriox_ip_feature_cn63xx cn63xxp1; + struct cvmx_sriox_ip_feature_s cn66xx; +}; + +union cvmx_sriox_mac_buffers { + uint64_t u64; + struct cvmx_sriox_mac_buffers_s { + uint64_t reserved_56_63:8; + uint64_t tx_enb:8; + uint64_t reserved_44_47:4; + uint64_t tx_inuse:4; + uint64_t tx_stat:8; + uint64_t reserved_24_31:8; + uint64_t rx_enb:8; + uint64_t reserved_12_15:4; + uint64_t rx_inuse:4; + uint64_t rx_stat:8; + } s; + struct cvmx_sriox_mac_buffers_s cn63xx; + struct cvmx_sriox_mac_buffers_s cn66xx; +}; + +union cvmx_sriox_maint_op { + uint64_t u64; + struct cvmx_sriox_maint_op_s { + uint64_t wr_data:32; + uint64_t reserved_27_31:5; + uint64_t fail:1; + uint64_t pending:1; + uint64_t op:1; + uint64_t addr:24; + } s; + struct cvmx_sriox_maint_op_s cn63xx; + struct cvmx_sriox_maint_op_s cn63xxp1; + struct cvmx_sriox_maint_op_s cn66xx; +}; + +union cvmx_sriox_maint_rd_data { + uint64_t u64; + struct cvmx_sriox_maint_rd_data_s { + uint64_t reserved_33_63:31; + uint64_t valid:1; + uint64_t rd_data:32; + } s; + struct cvmx_sriox_maint_rd_data_s cn63xx; + struct cvmx_sriox_maint_rd_data_s cn63xxp1; + struct cvmx_sriox_maint_rd_data_s cn66xx; +}; + +union cvmx_sriox_mce_tx_ctl { + uint64_t u64; + struct cvmx_sriox_mce_tx_ctl_s { + uint64_t reserved_1_63:63; + uint64_t mce:1; + } s; + struct cvmx_sriox_mce_tx_ctl_s cn63xx; + struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; + struct cvmx_sriox_mce_tx_ctl_s cn66xx; +}; + +union cvmx_sriox_mem_op_ctrl { + uint64_t u64; + struct cvmx_sriox_mem_op_ctrl_s { + uint64_t reserved_10_63:54; + uint64_t rr_ro:1; + uint64_t w_ro:1; + uint64_t reserved_6_7:2; + uint64_t rp1_sid:1; + uint64_t rp0_sid:2; + uint64_t rp1_pid:1; + uint64_t rp0_pid:2; + } s; + struct cvmx_sriox_mem_op_ctrl_s cn63xx; + struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; + struct cvmx_sriox_mem_op_ctrl_s cn66xx; +}; + +union cvmx_sriox_omsg_ctrlx { + uint64_t u64; + struct cvmx_sriox_omsg_ctrlx_s { + uint64_t testmode:1; + uint64_t reserved_37_62:26; + uint64_t silo_max:5; + uint64_t rtry_thr:16; + uint64_t rtry_en:1; + uint64_t reserved_11_14:4; + uint64_t idm_tt:1; + uint64_t idm_sis:1; + uint64_t idm_did:1; + uint64_t lttr_sp:4; + uint64_t lttr_mp:4; + } s; + struct cvmx_sriox_omsg_ctrlx_s cn63xx; + struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { + uint64_t testmode:1; + uint64_t reserved_32_62:31; + uint64_t rtry_thr:16; + uint64_t rtry_en:1; + uint64_t reserved_11_14:4; + uint64_t idm_tt:1; + uint64_t idm_sis:1; + uint64_t idm_did:1; + uint64_t lttr_sp:4; + uint64_t lttr_mp:4; + } cn63xxp1; + struct cvmx_sriox_omsg_ctrlx_s cn66xx; +}; + +union cvmx_sriox_omsg_done_countsx { + uint64_t u64; + struct cvmx_sriox_omsg_done_countsx_s { + uint64_t reserved_32_63:32; + uint64_t bad:16; + uint64_t good:16; + } s; + struct cvmx_sriox_omsg_done_countsx_s cn63xx; + struct cvmx_sriox_omsg_done_countsx_s cn66xx; +}; + +union cvmx_sriox_omsg_fmp_mrx { + uint64_t u64; + struct cvmx_sriox_omsg_fmp_mrx_s { + uint64_t reserved_15_63:49; + uint64_t ctlr_sp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_nmp:1; + uint64_t id_sp:1; + uint64_t id_fmp:1; + uint64_t id_nmp:1; + uint64_t id_psd:1; + uint64_t mbox_sp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_nmp:1; + uint64_t mbox_psd:1; + uint64_t all_sp:1; + uint64_t all_fmp:1; + uint64_t all_nmp:1; + uint64_t all_psd:1; + } s; + struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; + struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; + struct cvmx_sriox_omsg_fmp_mrx_s cn66xx; +}; + +union cvmx_sriox_omsg_nmp_mrx { + uint64_t u64; + struct cvmx_sriox_omsg_nmp_mrx_s { + uint64_t reserved_15_63:49; + uint64_t ctlr_sp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_nmp:1; + uint64_t id_sp:1; + uint64_t id_fmp:1; + uint64_t id_nmp:1; + uint64_t reserved_8_8:1; + uint64_t mbox_sp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_nmp:1; + uint64_t reserved_4_4:1; + uint64_t all_sp:1; + uint64_t all_fmp:1; + uint64_t all_nmp:1; + uint64_t reserved_0_0:1; + } s; + struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; + struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; + struct cvmx_sriox_omsg_nmp_mrx_s cn66xx; +}; + +union cvmx_sriox_omsg_portx { + uint64_t u64; + struct cvmx_sriox_omsg_portx_s { + uint64_t reserved_32_63:32; + uint64_t enable:1; + uint64_t reserved_3_30:28; + uint64_t port:3; + } s; + struct cvmx_sriox_omsg_portx_cn63xx { + uint64_t reserved_32_63:32; + uint64_t enable:1; + uint64_t reserved_2_30:29; + uint64_t port:2; + } cn63xx; + struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1; + struct cvmx_sriox_omsg_portx_s cn66xx; +}; + +union cvmx_sriox_omsg_silo_thr { + uint64_t u64; + struct cvmx_sriox_omsg_silo_thr_s { + uint64_t reserved_5_63:59; + uint64_t tot_silo:5; + } s; + struct cvmx_sriox_omsg_silo_thr_s cn63xx; + struct cvmx_sriox_omsg_silo_thr_s cn66xx; +}; + +union cvmx_sriox_omsg_sp_mrx { + uint64_t u64; + struct cvmx_sriox_omsg_sp_mrx_s { + uint64_t reserved_16_63:48; + uint64_t xmbox_sp:1; + uint64_t ctlr_sp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_nmp:1; + uint64_t id_sp:1; + uint64_t id_fmp:1; + uint64_t id_nmp:1; + uint64_t id_psd:1; + uint64_t mbox_sp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_nmp:1; + uint64_t mbox_psd:1; + uint64_t all_sp:1; + uint64_t all_fmp:1; + uint64_t all_nmp:1; + uint64_t all_psd:1; + } s; + struct cvmx_sriox_omsg_sp_mrx_s cn63xx; + struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; + struct cvmx_sriox_omsg_sp_mrx_s cn66xx; +}; + +union cvmx_sriox_priox_in_use { + uint64_t u64; + struct cvmx_sriox_priox_in_use_s { + uint64_t reserved_32_63:32; + uint64_t end_cnt:16; + uint64_t start_cnt:16; + } s; + struct cvmx_sriox_priox_in_use_s cn63xx; + struct cvmx_sriox_priox_in_use_s cn66xx; +}; + +union cvmx_sriox_rx_bell { + uint64_t u64; + struct cvmx_sriox_rx_bell_s { + uint64_t reserved_48_63:16; + uint64_t data:16; + uint64_t src_id:16; + uint64_t count:8; + uint64_t reserved_5_7:3; + uint64_t dest_id:1; + uint64_t id16:1; + uint64_t reserved_2_2:1; + uint64_t priority:2; + } s; + struct cvmx_sriox_rx_bell_s cn63xx; + struct cvmx_sriox_rx_bell_s cn63xxp1; + struct cvmx_sriox_rx_bell_s cn66xx; +}; + +union cvmx_sriox_rx_bell_seq { + uint64_t u64; + struct cvmx_sriox_rx_bell_seq_s { + uint64_t reserved_40_63:24; + uint64_t count:8; + uint64_t seq:32; + } s; + struct cvmx_sriox_rx_bell_seq_s cn63xx; + struct cvmx_sriox_rx_bell_seq_s cn63xxp1; + struct cvmx_sriox_rx_bell_seq_s cn66xx; +}; + +union cvmx_sriox_rx_status { + uint64_t u64; + struct cvmx_sriox_rx_status_s { + uint64_t rtn_pr3:8; + uint64_t rtn_pr2:8; + uint64_t rtn_pr1:8; + uint64_t reserved_28_39:12; + uint64_t mbox:4; + uint64_t comp:8; + uint64_t reserved_13_15:3; + uint64_t n_post:5; + uint64_t post:8; + } s; + struct cvmx_sriox_rx_status_s cn63xx; + struct cvmx_sriox_rx_status_s cn63xxp1; + struct cvmx_sriox_rx_status_s cn66xx; +}; + +union cvmx_sriox_s2m_typex { + uint64_t u64; + struct cvmx_sriox_s2m_typex_s { + uint64_t reserved_19_63:45; + uint64_t wr_op:3; + uint64_t reserved_15_15:1; + uint64_t rd_op:3; + uint64_t wr_prior:2; + uint64_t rd_prior:2; + uint64_t reserved_6_7:2; + uint64_t src_id:1; + uint64_t id16:1; + uint64_t reserved_2_3:2; + uint64_t iaow_sel:2; + } s; + struct cvmx_sriox_s2m_typex_s cn63xx; + struct cvmx_sriox_s2m_typex_s cn63xxp1; + struct cvmx_sriox_s2m_typex_s cn66xx; +}; + +union cvmx_sriox_seq { + uint64_t u64; + struct cvmx_sriox_seq_s { + uint64_t reserved_32_63:32; + uint64_t seq:32; + } s; + struct cvmx_sriox_seq_s cn63xx; + struct cvmx_sriox_seq_s cn63xxp1; + struct cvmx_sriox_seq_s cn66xx; +}; + +union cvmx_sriox_status_reg { + uint64_t u64; + struct cvmx_sriox_status_reg_s { + uint64_t reserved_2_63:62; + uint64_t access:1; + uint64_t srio:1; + } s; + struct cvmx_sriox_status_reg_s cn63xx; + struct cvmx_sriox_status_reg_s cn63xxp1; + struct cvmx_sriox_status_reg_s cn66xx; +}; + +union cvmx_sriox_tag_ctrl { + uint64_t u64; + struct cvmx_sriox_tag_ctrl_s { + uint64_t reserved_17_63:47; + uint64_t o_clr:1; + uint64_t reserved_13_15:3; + uint64_t otag:5; + uint64_t reserved_5_7:3; + uint64_t itag:5; + } s; + struct cvmx_sriox_tag_ctrl_s cn63xx; + struct cvmx_sriox_tag_ctrl_s cn63xxp1; + struct cvmx_sriox_tag_ctrl_s cn66xx; +}; + +union cvmx_sriox_tlp_credits { + uint64_t u64; + struct cvmx_sriox_tlp_credits_s { + uint64_t reserved_28_63:36; + uint64_t mbox:4; + uint64_t comp:8; + uint64_t reserved_13_15:3; + uint64_t n_post:5; + uint64_t post:8; + } s; + struct cvmx_sriox_tlp_credits_s cn63xx; + struct cvmx_sriox_tlp_credits_s cn63xxp1; + struct cvmx_sriox_tlp_credits_s cn66xx; +}; + +union cvmx_sriox_tx_bell { + uint64_t u64; + struct cvmx_sriox_tx_bell_s { + uint64_t reserved_48_63:16; + uint64_t data:16; + uint64_t dest_id:16; + uint64_t reserved_9_15:7; + uint64_t pending:1; + uint64_t reserved_5_7:3; + uint64_t src_id:1; + uint64_t id16:1; + uint64_t reserved_2_2:1; + uint64_t priority:2; + } s; + struct cvmx_sriox_tx_bell_s cn63xx; + struct cvmx_sriox_tx_bell_s cn63xxp1; + struct cvmx_sriox_tx_bell_s cn66xx; +}; + +union cvmx_sriox_tx_bell_info { + uint64_t u64; + struct cvmx_sriox_tx_bell_info_s { + uint64_t reserved_48_63:16; + uint64_t data:16; + uint64_t dest_id:16; + uint64_t reserved_8_15:8; + uint64_t timeout:1; + uint64_t error:1; + uint64_t retry:1; + uint64_t src_id:1; + uint64_t id16:1; + uint64_t reserved_2_2:1; + uint64_t priority:2; + } s; + struct cvmx_sriox_tx_bell_info_s cn63xx; + struct cvmx_sriox_tx_bell_info_s cn63xxp1; + struct cvmx_sriox_tx_bell_info_s cn66xx; +}; + +union cvmx_sriox_tx_ctrl { + uint64_t u64; + struct cvmx_sriox_tx_ctrl_s { + uint64_t reserved_53_63:11; + uint64_t tag_th2:5; + uint64_t reserved_45_47:3; + uint64_t tag_th1:5; + uint64_t reserved_37_39:3; + uint64_t tag_th0:5; + uint64_t reserved_20_31:12; + uint64_t tx_th2:4; + uint64_t reserved_12_15:4; + uint64_t tx_th1:4; + uint64_t reserved_4_7:4; + uint64_t tx_th0:4; + } s; + struct cvmx_sriox_tx_ctrl_s cn63xx; + struct cvmx_sriox_tx_ctrl_s cn63xxp1; + struct cvmx_sriox_tx_ctrl_s cn66xx; +}; + +union cvmx_sriox_tx_emphasis { + uint64_t u64; + struct cvmx_sriox_tx_emphasis_s { + uint64_t reserved_4_63:60; + uint64_t emph:4; + } s; + struct cvmx_sriox_tx_emphasis_s cn63xx; + struct cvmx_sriox_tx_emphasis_s cn66xx; +}; + +union cvmx_sriox_tx_status { + uint64_t u64; + struct cvmx_sriox_tx_status_s { + uint64_t reserved_32_63:32; + uint64_t s2m_pr3:8; + uint64_t s2m_pr2:8; + uint64_t s2m_pr1:8; + uint64_t s2m_pr0:8; + } s; + struct cvmx_sriox_tx_status_s cn63xx; + struct cvmx_sriox_tx_status_s cn63xxp1; + struct cvmx_sriox_tx_status_s cn66xx; +}; + +union cvmx_sriox_wr_done_counts { + uint64_t u64; + struct cvmx_sriox_wr_done_counts_s { + uint64_t reserved_32_63:32; + uint64_t bad:16; + uint64_t good:16; + } s; + struct cvmx_sriox_wr_done_counts_s cn63xx; + struct cvmx_sriox_wr_done_counts_s cn66xx; +}; + +#endif From 26afc5e399a4ab33a04216a37cd996ee224976a0 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:47:04 +0000 Subject: [PATCH 073/119] MIPS: Octeon: Update feature test functions for new chips and features. cvmx.h was rearranged to fix include file ordering problems, but there is no change other than moving some definitions around. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2984/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/octeon/cvmx.h | 42 +++---- arch/mips/include/asm/octeon/octeon-feature.h | 114 ++++++++++++++++-- 2 files changed, 126 insertions(+), 30 deletions(-) diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h index 7e1286706d46..740be97a3251 100644 --- a/arch/mips/include/asm/octeon/cvmx.h +++ b/arch/mips/include/asm/octeon/cvmx.h @@ -31,6 +31,27 @@ #include #include +enum cvmx_mips_space { + CVMX_MIPS_SPACE_XKSEG = 3LL, + CVMX_MIPS_SPACE_XKPHYS = 2LL, + CVMX_MIPS_SPACE_XSSEG = 1LL, + CVMX_MIPS_SPACE_XUSEG = 0LL +}; + +/* These macros for use when using 32 bit pointers. */ +#define CVMX_MIPS32_SPACE_KSEG0 1l +#define CVMX_ADD_SEG32(segment, add) \ + (((int32_t)segment << 31) | (int32_t)(add)) + +#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS + +/* These macros simplify the process of creating common IO addresses */ +#define CVMX_ADD_SEG(segment, add) \ + ((((uint64_t)segment) << 62) | (add)) +#ifndef CVMX_ADD_IO_SEG +#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) +#endif + #include "cvmx-asm.h" #include "cvmx-packet.h" #include "cvmx-sysinfo.h" @@ -129,27 +150,6 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit, return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit; } -enum cvmx_mips_space { - CVMX_MIPS_SPACE_XKSEG = 3LL, - CVMX_MIPS_SPACE_XKPHYS = 2LL, - CVMX_MIPS_SPACE_XSSEG = 1LL, - CVMX_MIPS_SPACE_XUSEG = 0LL -}; - -/* These macros for use when using 32 bit pointers. */ -#define CVMX_MIPS32_SPACE_KSEG0 1l -#define CVMX_ADD_SEG32(segment, add) \ - (((int32_t)segment << 31) | (int32_t)(add)) - -#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS - -/* These macros simplify the process of creating common IO addresses */ -#define CVMX_ADD_SEG(segment, add) \ - ((((uint64_t)segment) << 62) | (add)) -#ifndef CVMX_ADD_IO_SEG -#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) -#endif - /** * Convert a memory pointer (void*) into a hardware compatible * memory address (uint64_t). Octeon hardware widgets don't diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h index cba6fbed9f43..8008da2f8779 100644 --- a/arch/mips/include/asm/octeon/octeon-feature.h +++ b/arch/mips/include/asm/octeon/octeon-feature.h @@ -31,8 +31,14 @@ #ifndef __OCTEON_FEATURE_H__ #define __OCTEON_FEATURE_H__ +#include +#include enum octeon_feature { + /* CN68XX uses port kinds for packet interface */ + OCTEON_FEATURE_PKND, + /* CN68XX has different fields in word0 - word2 */ + OCTEON_FEATURE_CN68XX_WQE, /* * Octeon models in the CN5XXX family and higher support * atomic add instructions to memory (saa/saad). @@ -42,8 +48,13 @@ enum octeon_feature { OCTEON_FEATURE_ZIP, /* Does this Octeon support crypto acceleration using COP2? */ OCTEON_FEATURE_CRYPTO, + OCTEON_FEATURE_DORM_CRYPTO, /* Does this Octeon support PCI express? */ OCTEON_FEATURE_PCIE, + /* Does this Octeon support SRIOs */ + OCTEON_FEATURE_SRIO, + /* Does this Octeon support Interlaken */ + OCTEON_FEATURE_ILK, /* Some Octeon models support internal memory for storing * cryptographic keys */ OCTEON_FEATURE_KEY_MEMORY, @@ -64,6 +75,15 @@ enum octeon_feature { /* Octeon MDIO block supports clause 45 transactions for 10 * Gig support */ OCTEON_FEATURE_MDIO_CLAUSE_45, + /* + * CN52XX and CN56XX used a block named NPEI for PCIe + * access. Newer chips replaced this with SLI+DPI. + */ + OCTEON_FEATURE_NPEI, + OCTEON_FEATURE_HFA, + OCTEON_FEATURE_DFM, + OCTEON_FEATURE_CIU2, + OCTEON_MAX_FEATURE }; static inline int cvmx_fuse_read(int fuse); @@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature) return !cvmx_fuse_read(121); case OCTEON_FEATURE_CRYPTO: - return !cvmx_fuse_read(90); + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + union cvmx_mio_fus_dat2 fus_2; + fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); + if (fus_2.s.nocrypto || fus_2.s.nomul) { + return 0; + } else if (!fus_2.s.dorm_crypto) { + return 1; + } else { + union cvmx_rnm_ctl_status st; + st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS); + return st.s.eer_val; + } + } else { + return !cvmx_fuse_read(90); + } + + case OCTEON_FEATURE_DORM_CRYPTO: + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + union cvmx_mio_fus_dat2 fus_2; + fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); + return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto; + } else { + return 0; + } case OCTEON_FEATURE_PCIE: - case OCTEON_FEATURE_MGMT_PORT: - case OCTEON_FEATURE_RAID: return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + + case OCTEON_FEATURE_SRIO: + return OCTEON_IS_MODEL(OCTEON_CN63XX) + || OCTEON_IS_MODEL(OCTEON_CN66XX); + + case OCTEON_FEATURE_ILK: + return (OCTEON_IS_MODEL(OCTEON_CN68XX)); case OCTEON_FEATURE_KEY_MEMORY: + return OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + case OCTEON_FEATURE_LED_CONTROLLER: return OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX); + case OCTEON_FEATURE_TRA: return !(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)); + case OCTEON_FEATURE_MGMT_PORT: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + + case OCTEON_FEATURE_RAID: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + case OCTEON_FEATURE_USB: return !(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)); + case OCTEON_FEATURE_NO_WPTR: return (OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) - && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) - && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX)) + && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) + && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); + case OCTEON_FEATURE_DFA: if (!OCTEON_IS_MODEL(OCTEON_CN38XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) @@ -127,14 +195,42 @@ static inline int octeon_has_feature(enum octeon_feature feature) return 0; else if (OCTEON_IS_MODEL(OCTEON_CN3020)) return 0; - else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) - return 1; else return !cvmx_fuse_read(120); + + case OCTEON_FEATURE_HFA: + if (!OCTEON_IS_MODEL(OCTEON_CN6XXX)) + return 0; + else + return !cvmx_fuse_read(90); + + case OCTEON_FEATURE_DFM: + if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) + || OCTEON_IS_MODEL(OCTEON_CN66XX))) + return 0; + else + return !cvmx_fuse_read(90); + case OCTEON_FEATURE_MDIO_CLAUSE_45: return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)); + + case OCTEON_FEATURE_NPEI: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX); + + case OCTEON_FEATURE_PKND: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + + case OCTEON_FEATURE_CN68XX_WQE: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + + case OCTEON_FEATURE_CIU2: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + + default: + break; } return 0; } From 714c1f5c1aab1cc185018f02bcc854c41ff8e6c8 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:47:04 +0000 Subject: [PATCH 074/119] MIPS: Octeon: Update DMA mapping operations for OCTEON II processors. OCTEON II has a new dma to phys mapping method for PCIe. Define OCTEON_DMA_BAR_TYPE_PCIE2 to denote this case, and handle it. OCTEON II also needs a swiotlb if the OHCI USB driver is enabled, so allocate this too. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2983/ Signed-off-by: Ralf Baechle --- arch/mips/cavium-octeon/dma-octeon.c | 23 +++++++++++++++++++++-- arch/mips/include/asm/octeon/pci-octeon.h | 3 ++- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index ea4febaa4bb1..b6bb92c16a47 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -61,6 +61,16 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr) return daddr; } +static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + return octeon_hole_phys_to_dma(paddr); +} + +static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + return octeon_hole_dma_to_phys(daddr); +} + static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr) { if (paddr >= 0x410000000ull && paddr < 0x420000000ull) @@ -262,11 +272,11 @@ void __init plat_swiotlb_setup(void) for (i = 0 ; i < boot_mem_map.nr_map; i++) { struct boot_mem_map_entry *e = &boot_mem_map.map[i]; - if (e->type != BOOT_MEM_RAM) + if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM) continue; /* These addresses map low for PCI. */ - if (e->addr > 0x410000000ull) + if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX)) continue; addr_size += e->size; @@ -295,6 +305,11 @@ void __init plat_swiotlb_setup(void) */ swiotlbsize = 64 * (1<<20); } +#endif +#ifdef CONFIG_USB_OCTEON_OHCI + /* OCTEON II ohci is only 32-bit. */ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul) + swiotlbsize = 64 * (1<<20); #endif swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT; swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE); @@ -330,6 +345,10 @@ struct dma_map_ops *octeon_pci_dma_map_ops; void __init octeon_pci_dma_init(void) { switch (octeon_dma_bar_type) { + case OCTEON_DMA_BAR_TYPE_PCIE2: + _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma; + _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys; + break; case OCTEON_DMA_BAR_TYPE_PCIE: _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma; _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys; diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h index fba2ba200f58..c66734bd3382 100644 --- a/arch/mips/include/asm/octeon/pci-octeon.h +++ b/arch/mips/include/asm/octeon/pci-octeon.h @@ -56,7 +56,8 @@ enum octeon_dma_bar_type { OCTEON_DMA_BAR_TYPE_INVALID, OCTEON_DMA_BAR_TYPE_SMALL, OCTEON_DMA_BAR_TYPE_BIG, - OCTEON_DMA_BAR_TYPE_PCIE + OCTEON_DMA_BAR_TYPE_PCIE, + OCTEON_DMA_BAR_TYPE_PCIE2 }; /* From e84de0c61905030a0fe66b7210b6f1bb7c3e1eab Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Tue, 22 Nov 2011 14:38:02 +0000 Subject: [PATCH 075/119] MIPS: GIO bus support for SGI IP22/28 SGI IP22/IP28 machines have GIO busses for adding graphics and other extension cards. This patch adds support for GIO driver/device handling and converts the newport console driver to a GIO driver. [ralf@linux-mips.org: Fixed build error caused by the modules.h -> export.h changes.] Signed-off-by: Thomas Bogendoerfer Acked-by: Florian Tobias Schandinat To: linux-fbdev@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2886/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/gio_device.h | 56 ++++ arch/mips/sgi-ip22/Makefile | 2 +- arch/mips/sgi-ip22/ip22-gio.c | 428 ++++++++++++++++++++++++++++ arch/mips/sgi-ip22/ip22-mc.c | 10 +- arch/mips/sgi-ip22/ip22-setup.c | 21 -- drivers/video/console/newport_con.c | 63 ++-- 6 files changed, 534 insertions(+), 46 deletions(-) create mode 100644 arch/mips/include/asm/gio_device.h create mode 100644 arch/mips/sgi-ip22/ip22-gio.c diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h new file mode 100644 index 000000000000..5437c84664bf --- /dev/null +++ b/arch/mips/include/asm/gio_device.h @@ -0,0 +1,56 @@ +#include +#include + +struct gio_device_id { + __u8 id; +}; + +struct gio_device { + struct device dev; + struct resource resource; + unsigned int irq; + unsigned int slotno; + + const char *name; + struct gio_device_id id; + unsigned id32:1; + unsigned gio64:1; +}; +#define to_gio_device(d) container_of(d, struct gio_device, dev) + +struct gio_driver { + const char *name; + struct module *owner; + const struct gio_device_id *id_table; + + int (*probe)(struct gio_device *, const struct gio_device_id *); + void (*remove)(struct gio_device *); + int (*suspend)(struct gio_device *, pm_message_t); + int (*resume)(struct gio_device *); + void (*shutdown)(struct gio_device *); + + struct device_driver driver; +}; +#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver) + +extern const struct gio_device_id *gio_match_device(const struct gio_device_id *, + const struct gio_device *); +extern struct gio_device *gio_dev_get(struct gio_device *); +extern void gio_dev_put(struct gio_device *); + +extern int gio_device_register(struct gio_device *); +extern void gio_device_unregister(struct gio_device *); +extern void gio_release_dev(struct device *); + +static inline void gio_device_free(struct gio_device *dev) +{ + gio_release_dev(&dev->dev); +} + +extern int gio_register_driver(struct gio_driver *); +extern void gio_unregister_driver(struct gio_driver *); + +#define gio_get_drvdata(_dev) drv_get_drvdata(&(_dev)->dev) +#define gio_set_drvdata(_dev, data) drv_set_drvdata(&(_dev)->dev, (data)) + +extern void gio_set_master(struct gio_device *); diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile index cc538493cae1..411cda9ee030 100644 --- a/arch/mips/sgi-ip22/Makefile +++ b/arch/mips/sgi-ip22/Makefile @@ -4,7 +4,7 @@ # obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \ - ip22-platform.o ip22-reset.o ip22-setup.o + ip22-platform.o ip22-reset.o ip22-setup.o ip22-gio.o obj-$(CONFIG_SGI_IP22) += ip22-berr.o obj-$(CONFIG_SGI_IP28) += ip28-berr.o diff --git a/arch/mips/sgi-ip22/ip22-gio.c b/arch/mips/sgi-ip22/ip22-gio.c new file mode 100644 index 000000000000..f5ebc092aed5 --- /dev/null +++ b/arch/mips/sgi-ip22/ip22-gio.c @@ -0,0 +1,428 @@ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +static struct bus_type gio_bus_type; + +static struct { + const char *name; + __u8 id; +} gio_name_table[] = { + { .name = "SGI Impact", .id = 0x10 }, + { .name = "Phobos G160", .id = 0x35 }, + /* fake IDs */ + { .name = "SGI Newport", .id = 0x7e }, + { .name = "SGI GR2/GR3", .id = 0x7f }, +}; + +static struct device gio_bus = { + .init_name = "gio", +}; + +/** + * gio_match_device - Tell if an of_device structure has a matching + * gio_match structure + * @ids: array of of device match structures to search in + * @dev: the of device structure to match against + * + * Used by a driver to check whether an of_device present in the + * system is in its list of supported devices. + */ +const struct gio_device_id *gio_match_device(const struct gio_device_id *match, + const struct gio_device *dev) +{ + const struct gio_device_id *ids; + + for (ids = match; ids->id != 0xff; ids++) + if (ids->id == dev->id.id) + return ids; + + return NULL; +} +EXPORT_SYMBOL_GPL(gio_match_device); + +struct gio_device *gio_dev_get(struct gio_device *dev) +{ + struct device *tmp; + + if (!dev) + return NULL; + tmp = get_device(&dev->dev); + if (tmp) + return to_gio_device(tmp); + else + return NULL; +} +EXPORT_SYMBOL_GPL(gio_dev_get); + +void gio_dev_put(struct gio_device *dev) +{ + if (dev) + put_device(&dev->dev); +} +EXPORT_SYMBOL_GPL(gio_dev_put); + +/** + * gio_release_dev - free an gio device structure when all users of it are finished. + * @dev: device that's been disconnected + * + * Will be called only by the device core when all users of this gio device are + * done. + */ +void gio_release_dev(struct device *dev) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + kfree(giodev); +} +EXPORT_SYMBOL_GPL(gio_release_dev); + +int gio_device_register(struct gio_device *giodev) +{ + giodev->dev.bus = &gio_bus_type; + giodev->dev.parent = &gio_bus; + return device_register(&giodev->dev); +} +EXPORT_SYMBOL_GPL(gio_device_register); + +void gio_device_unregister(struct gio_device *giodev) +{ + device_unregister(&giodev->dev); +} +EXPORT_SYMBOL_GPL(gio_device_unregister); + +static int gio_bus_match(struct device *dev, struct device_driver *drv) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *gio_drv = to_gio_driver(drv); + + return gio_match_device(gio_drv->id_table, gio_dev) != NULL; +} + +static int gio_device_probe(struct device *dev) +{ + int error = -ENODEV; + struct gio_driver *drv; + struct gio_device *gio_dev; + const struct gio_device_id *match; + + drv = to_gio_driver(dev->driver); + gio_dev = to_gio_device(dev); + + if (!drv->probe) + return error; + + gio_dev_get(gio_dev); + + match = gio_match_device(drv->id_table, gio_dev); + if (match) + error = drv->probe(gio_dev, match); + if (error) + gio_dev_put(gio_dev); + + return error; +} + +static int gio_device_remove(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + + if (dev->driver && drv->remove) + drv->remove(gio_dev); + return 0; +} + +static int gio_device_suspend(struct device *dev, pm_message_t state) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + int error = 0; + + if (dev->driver && drv->suspend) + error = drv->suspend(gio_dev, state); + return error; +} + +static int gio_device_resume(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + int error = 0; + + if (dev->driver && drv->resume) + error = drv->resume(gio_dev); + return error; +} + +static void gio_device_shutdown(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + + if (dev->driver && drv->shutdown) + drv->shutdown(gio_dev); +} + +static ssize_t modalias_show(struct device *dev, struct device_attribute *a, + char *buf) +{ + struct gio_device *gio_dev = to_gio_device(dev); + int len = snprintf(buf, PAGE_SIZE, "gio:%x\n", gio_dev->id.id); + + return (len >= PAGE_SIZE) ? (PAGE_SIZE - 1) : len; +} + +static ssize_t name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + return sprintf(buf, "%s", giodev->name); +} + +static ssize_t id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + return sprintf(buf, "%x", giodev->id.id); +} + +static struct device_attribute gio_dev_attrs[] = { + __ATTR_RO(modalias), + __ATTR_RO(name), + __ATTR_RO(id), + __ATTR_NULL, +}; + +static int gio_device_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct gio_device *gio_dev = to_gio_device(dev); + + add_uevent_var(env, "MODALIAS=gio:%x", gio_dev->id.id); + return 0; +} + +int gio_register_driver(struct gio_driver *drv) +{ + /* initialize common driver fields */ + if (!drv->driver.name) + drv->driver.name = drv->name; + if (!drv->driver.owner) + drv->driver.owner = drv->owner; + drv->driver.bus = &gio_bus_type; + + /* register with core */ + return driver_register(&drv->driver); +} +EXPORT_SYMBOL_GPL(gio_register_driver); + +void gio_unregister_driver(struct gio_driver *drv) +{ + driver_unregister(&drv->driver); +} +EXPORT_SYMBOL_GPL(gio_unregister_driver); + +void gio_set_master(struct gio_device *dev) +{ + u32 tmp = sgimc->giopar; + + switch (dev->slotno) { + case 0: + tmp |= SGIMC_GIOPAR_MASTERGFX; + break; + case 1: + tmp |= SGIMC_GIOPAR_MASTEREXP0; + break; + case 2: + tmp |= SGIMC_GIOPAR_MASTEREXP1; + break; + } + sgimc->giopar = tmp; +} +EXPORT_SYMBOL_GPL(gio_set_master); + +void ip22_gio_set_64bit(int slotno) +{ + u32 tmp = sgimc->giopar; + + switch (slotno) { + case 0: + tmp |= SGIMC_GIOPAR_GFX64; + break; + case 1: + tmp |= SGIMC_GIOPAR_EXP064; + break; + case 2: + tmp |= SGIMC_GIOPAR_EXP164; + break; + } + sgimc->giopar = tmp; +} + +static int ip22_gio_id(unsigned long addr, u32 *res) +{ + u8 tmp8; + u8 tmp16; + u32 tmp32; + u8 *ptr8; + u16 *ptr16; + u32 *ptr32; + + ptr32 = (void *)CKSEG1ADDR(addr); + if (!get_dbe(tmp32, ptr32)) { + /* + * We got no DBE, but this doesn't mean anything. + * If GIO is pipelined (which can't be disabled + * for GFX slot) we don't get a DBE, but we see + * the transfer size as data. So we do an 8bit + * and a 16bit access and check whether the common + * data matches + */ + ptr8 = (void *)CKSEG1ADDR(addr + 3); + get_dbe(tmp8, ptr8); + ptr16 = (void *)CKSEG1ADDR(addr + 2); + get_dbe(tmp16, ptr16); + if (tmp8 == (tmp16 & 0xff) && + tmp8 == (tmp32 & 0xff) && + tmp16 == (tmp32 & 0xffff)) { + *res = tmp32; + return 1; + } + } + return 0; /* nothing here */ +} + +#define HQ2_MYSTERY_OFFS 0x6A07C +#define NEWPORT_USTATUS_OFFS 0xF133C + +static int ip22_is_gr2(unsigned long addr) +{ + u32 tmp; + u32 *ptr; + + /* HQ2 only allows 32bit accesses */ + ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS); + if (!get_dbe(tmp, ptr)) { + if (tmp == 0xdeadbeef) + return 1; + } + return 0; +} + + +static void ip22_check_gio(int slotno, unsigned long addr) +{ + const char *name = "Unknown"; + struct gio_device *gio_dev; + u32 tmp; + __u8 id; + int i; + + /* first look for GR2/GR3 by checking mystery register */ + if (ip22_is_gr2(addr)) + tmp = 0x7f; + else { + if (!ip22_gio_id(addr, &tmp)) { + /* + * no GIO signature at start address of slot, but + * Newport doesn't have one, so let's check usea + * status register + */ + if (ip22_gio_id(addr + NEWPORT_USTATUS_OFFS, &tmp)) + tmp = 0x7e; + else + tmp = 0; + } + } + if (tmp) { + id = GIO_ID(tmp); + if (tmp & GIO_32BIT_ID) { + if (tmp & GIO_64BIT_IFACE) + ip22_gio_set_64bit(slotno); + } + for (i = 0; i < ARRAY_SIZE(gio_name_table); i++) { + if (id == gio_name_table[i].id) { + name = gio_name_table[i].name; + break; + } + } + printk(KERN_INFO "GIO: slot %d : %s (id %x)\n", + slotno, name, id); + gio_dev = kzalloc(sizeof *gio_dev, GFP_KERNEL); + gio_dev->name = name; + gio_dev->slotno = slotno; + gio_dev->id.id = id; + gio_dev->resource.start = addr; + gio_dev->resource.end = addr + 0x3fffff; + gio_dev->resource.flags = IORESOURCE_MEM; + dev_set_name(&gio_dev->dev, "%d", slotno); + gio_device_register(gio_dev); + } else + printk(KERN_INFO "GIO: slot %d : Empty\n", slotno); +} + +static struct bus_type gio_bus_type = { + .name = "gio", + .dev_attrs = gio_dev_attrs, + .match = gio_bus_match, + .probe = gio_device_probe, + .remove = gio_device_remove, + .suspend = gio_device_suspend, + .resume = gio_device_resume, + .shutdown = gio_device_shutdown, + .uevent = gio_device_uevent, +}; + +static struct resource gio_bus_resource = { + .start = GIO_SLOT_GFX_BASE, + .end = GIO_SLOT_GFX_BASE + 0x9fffff, + .name = "GIO Bus", + .flags = IORESOURCE_MEM, +}; + +int __init ip22_gio_init(void) +{ + unsigned int pbdma __maybe_unused; + int ret; + + ret = device_register(&gio_bus); + if (ret) + return ret; + + ret = bus_register(&gio_bus_type); + if (!ret) { + request_resource(&iomem_resource, &gio_bus_resource); + printk(KERN_INFO "GIO: Probing bus...\n"); + + if (ip22_is_fullhouse() || + !get_dbe(pbdma, (unsigned int *)&hpc3c1->pbdma[1])) { + /* Indigo2 and ChallengeS */ + ip22_check_gio(0, GIO_SLOT_GFX_BASE); + ip22_check_gio(1, GIO_SLOT_EXP0_BASE); + } else { + /* Indy */ + ip22_check_gio(0, GIO_SLOT_GFX_BASE); + ip22_check_gio(1, GIO_SLOT_EXP0_BASE); + ip22_check_gio(2, GIO_SLOT_EXP1_BASE); + } + } else + device_unregister(&gio_bus); + + return ret; +} + +subsys_initcall(ip22_gio_init); diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c index d22262ee6853..75ada8a9713b 100644 --- a/arch/mips/sgi-ip22/ip22-mc.c +++ b/arch/mips/sgi-ip22/ip22-mc.c @@ -139,11 +139,11 @@ void __init sgimc_init(void) * zero. */ /* don't touch parity settings for IP28 */ -#ifndef CONFIG_SGI_IP28 tmp = sgimc->cpuctrl0; - tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | - SGIMC_CCTRL0_R4KNOCHKPARR); +#ifndef CONFIG_SGI_IP28 + tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM; #endif + tmp |= SGIMC_CCTRL0_R4KNOCHKPARR; sgimc->cpuctrl0 = tmp; /* Step 3: Setup the MC write buffer depth, this is controlled @@ -178,7 +178,8 @@ void __init sgimc_init(void) */ /* First the basic invariants across all GIO64 implementations. */ - tmp = SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ + tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */ + tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */ if (ip22_is_fullhouse()) { @@ -193,7 +194,6 @@ void __init sgimc_init(void) tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */ tmp |= SGIMC_GIOPAR_PLINEEXP1; tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */ - tmp |= SGIMC_GIOPAR_GFX64; /* GFX at 64 bits */ } } else { /* Guiness specific settings. */ diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 5e6621349471..c7bdfe43df5b 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -26,9 +26,6 @@ #include #include -unsigned long sgi_gfxaddr; -EXPORT_SYMBOL_GPL(sgi_gfxaddr); - extern void ip22_be_init(void) __init; void __init plat_mem_setup(void) @@ -78,22 +75,4 @@ void __init plat_mem_setup(void) prom_flags |= PROM_FLAG_USE_AS_CONSOLE; add_preferred_console("arc", 0, NULL); } - -#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE) - { - ULONG *gfxinfo; - ULONG * (*__vec)(void) = (void *) (long) - *((_PULONG *)(long)((PROMBLOCK)->pvector + 0x20)); - - gfxinfo = __vec(); - sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000 - && gfxinfo[1] <= 0xc0000000) - ? gfxinfo[1] - 0xa0000000 : 0); - - /* newport addresses? */ - if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) { - conswitchp = &newport_con; - } - } -#endif } diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c index 93317b5b8740..a122d9287d16 100644 --- a/drivers/video/console/newport_con.c +++ b/drivers/video/console/newport_con.c @@ -25,14 +25,13 @@ #include #include #include +#include + #include