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perf, x86: Add support for AMD family 15h core counters

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This patch adds support for AMD family 15h core counters. There are
major changes compared to family 10h. First, there is a new perfctr
msr range for up to 6 counters. Northbridge counters are separate
now. This patch only adds support for core counters. Second, certain
events may only be scheduled on certain counters. For this we need to
extend the event scheduling and constraints.

We use cpu feature flags to calculate family 15h msr address offsets.
This way we later can implement a faster ALTERNATIVE() version for
this.

Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <20110215135210.GB5874@erda.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Robert Richter
2011-02-02 17:36:12 +01:00
committed by Ingo Molnar
parent 73d6e52206
commit 4979d2729a
3 changed files with 186 additions and 3 deletions
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12
arch/x86/kernel/cpu/perf_event.c
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@@ -321,14 +321,22 @@ again:
return new_raw_count;
}
/* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */
static inline int x86_pmu_addr_offset(int index)
{
if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
return index << 1;
return index;
}
static inline unsigned int x86_pmu_config_addr(int index)
{
return x86_pmu.eventsel + index;
return x86_pmu.eventsel + x86_pmu_addr_offset(index);
}
static inline unsigned int x86_pmu_event_addr(int index)
{
return x86_pmu.perfctr + index;
return x86_pmu.perfctr + x86_pmu_addr_offset(index);
}
static atomic_t active_events;