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[MIPS] Fix "no space between function name and open parenthesis" warnings.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2007-10-11 23:46:15 +01:00
parent 10cc352907
commit 49a89efbbb
104 changed files with 842 additions and 842 deletions
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12
include/asm-mips/asmmacro.h
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@@ -56,27 +56,27 @@
* Temporary until all gas have MT ASE support * Temporary until all gas have MT ASE support
*/ */
.macro DMT reg=0 .macro DMT reg=0
.word (0x41600bc1 | (\reg << 16)) .word 0x41600bc1 | (\reg << 16)
.endm .endm
.macro EMT reg=0 .macro EMT reg=0
.word (0x41600be1 | (\reg << 16)) .word 0x41600be1 | (\reg << 16)
.endm .endm
.macro DVPE reg=0 .macro DVPE reg=0
.word (0x41600001 | (\reg << 16)) .word 0x41600001 | (\reg << 16)
.endm .endm
.macro EVPE reg=0 .macro EVPE reg=0
.word (0x41600021 | (\reg << 16)) .word 0x41600021 | (\reg << 16)
.endm .endm
.macro MFTR rt=0, rd=0, u=0, sel=0 .macro MFTR rt=0, rd=0, u=0, sel=0
.word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
.endm .endm
.macro MTTR rt=0, rd=0, u=0, sel=0 .macro MTTR rt=0, rd=0, u=0, sel=0
.word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
.endm .endm
#endif /* _ASM_ASMMACRO_H */ #endif /* _ASM_ASMMACRO_H */

4
include/asm-mips/bitops.h
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@@ -19,14 +19,14 @@
#include <asm/sgidefs.h> #include <asm/sgidefs.h>
#include <asm/war.h> #include <asm/war.h>
#if (_MIPS_SZLONG == 32) #if _MIPS_SZLONG == 32
#define SZLONG_LOG 5 #define SZLONG_LOG 5
#define SZLONG_MASK 31UL #define SZLONG_MASK 31UL
#define __LL "ll " #define __LL "ll "
#define __SC "sc " #define __SC "sc "
#define __INS "ins " #define __INS "ins "
#define __EXT "ext " #define __EXT "ext "
#elif (_MIPS_SZLONG == 64) #elif _MIPS_SZLONG == 64
#define SZLONG_LOG 6 #define SZLONG_LOG 6
#define SZLONG_MASK 63UL #define SZLONG_MASK 63UL
#define __LL "lld " #define __LL "lld "

24
include/asm-mips/mach-pnx8550/kernel-entry-init.h
View File

@@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated:
icache_invd_loop: icache_invd_loop:
/* 9 == register t1 */ /* 9 == register t1 */
.word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
(0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */ (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
.word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
(1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */ (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
@@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated:
dcache_wbinvd_loop: dcache_wbinvd_loop:
/* 9 == register t1 */ /* 9 == register t1 */
.word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
(0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */ (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
.word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
(1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */ (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
.word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
(2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */ (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
.word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
(3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */ (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */