big-endian support for via-velocity
* kill bitfields * annotate * add missing conversions * fix a couple of brainos in zerocopy stuff (fortunately, it's ifdef'ed out) Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Al Viro
David S. Miller
@@ -70,40 +70,27 @@
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* Bits in the RSR0 register
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*/
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#define RSR_DETAG 0x0080
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#define RSR_SNTAG 0x0040
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#define RSR_RXER 0x0020
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#define RSR_RL 0x0010
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#define RSR_CE 0x0008
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#define RSR_FAE 0x0004
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#define RSR_CRC 0x0002
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#define RSR_VIDM 0x0001
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#define RSR_DETAG cpu_to_le16(0x0080)
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#define RSR_SNTAG cpu_to_le16(0x0040)
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#define RSR_RXER cpu_to_le16(0x0020)
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#define RSR_RL cpu_to_le16(0x0010)
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#define RSR_CE cpu_to_le16(0x0008)
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#define RSR_FAE cpu_to_le16(0x0004)
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#define RSR_CRC cpu_to_le16(0x0002)
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#define RSR_VIDM cpu_to_le16(0x0001)
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/*
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* Bits in the RSR1 register
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*/
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#define RSR_RXOK 0x8000 // rx OK
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#define RSR_PFT 0x4000 // Perfect filtering address match
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#define RSR_MAR 0x2000 // MAC accept multicast address packet
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#define RSR_BAR 0x1000 // MAC accept broadcast address packet
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#define RSR_PHY 0x0800 // MAC accept physical address packet
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#define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator
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#define RSR_STP 0x0200 // start of packet
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#define RSR_EDP 0x0100 // end of packet
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/*
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* Bits in the RSR1 register
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*/
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#define RSR1_RXOK 0x80 // rx OK
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#define RSR1_PFT 0x40 // Perfect filtering address match
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#define RSR1_MAR 0x20 // MAC accept multicast address packet
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#define RSR1_BAR 0x10 // MAC accept broadcast address packet
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#define RSR1_PHY 0x08 // MAC accept physical address packet
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#define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator
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#define RSR1_STP 0x02 // start of packet
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#define RSR1_EDP 0x01 // end of packet
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#define RSR_RXOK cpu_to_le16(0x8000) // rx OK
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#define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match
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#define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet
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#define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet
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#define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet
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#define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator
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#define RSR_STP cpu_to_le16(0x0200) // start of packet
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#define RSR_EDP cpu_to_le16(0x0100) // end of packet
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/*
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* Bits in the CSM register
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@@ -120,33 +107,21 @@
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* Bits in the TSR0 register
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*/
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#define TSR0_ABT 0x0080 // Tx abort because of excessive collision
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#define TSR0_OWT 0x0040 // Jumbo frame Tx abort
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#define TSR0_OWC 0x0020 // Out of window collision
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#define TSR0_COLS 0x0010 // experience collision in this transmit event
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#define TSR0_NCR3 0x0008 // collision retry counter[3]
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#define TSR0_NCR2 0x0004 // collision retry counter[2]
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#define TSR0_NCR1 0x0002 // collision retry counter[1]
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#define TSR0_NCR0 0x0001 // collision retry counter[0]
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#define TSR0_TERR 0x8000 //
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#define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode
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#define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode
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#define TSR0_LNKFL 0x1000 // packet serviced during link down
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#define TSR0_SHDN 0x0400 // shutdown case
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#define TSR0_CRS 0x0200 // carrier sense lost
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#define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat)
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/*
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* Bits in the TSR1 register
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*/
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#define TSR1_TERR 0x80 //
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#define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode
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#define TSR1_GMII 0x20 // current transaction is serviced by GMII mode
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#define TSR1_LNKFL 0x10 // packet serviced during link down
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#define TSR1_SHDN 0x04 // shutdown case
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#define TSR1_CRS 0x02 // carrier sense lost
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#define TSR1_CDH 0x01 // AQE test fail (CD heartbeat)
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#define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision
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#define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort
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#define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision
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#define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event
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#define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3]
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#define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2]
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#define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1]
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#define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0]
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#define TSR0_TERR cpu_to_le16(0x8000) //
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#define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode
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#define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode
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#define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down
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#define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case
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#define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost
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#define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat)
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//
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// Bits in the TCR0 register
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@@ -197,25 +172,26 @@
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*/
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struct rdesc0 {
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u16 RSR; /* Receive status */
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u16 len:14; /* Received packet length */
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u16 reserved:1;
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u16 owner:1; /* Who owns this buffer ? */
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__le16 RSR; /* Receive status */
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__le16 len; /* bits 0--13; bit 15 - owner */
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};
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struct rdesc1 {
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u16 PQTAG;
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__le16 PQTAG;
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u8 CSM;
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u8 IPKT;
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};
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enum {
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RX_INTEN = __constant_cpu_to_le16(0x8000)
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};
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struct rx_desc {
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struct rdesc0 rdesc0;
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struct rdesc1 rdesc1;
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u32 pa_low; /* Low 32 bit PCI address */
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u16 pa_high; /* Next 16 bit PCI address (48 total) */
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u16 len:15; /* Frame size */
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u16 inten:1; /* Enable interrupt */
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__le32 pa_low; /* Low 32 bit PCI address */
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__le16 pa_high; /* Next 16 bit PCI address (48 total) */
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__le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */
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} __attribute__ ((__packed__));
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/*
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@@ -223,32 +199,24 @@ struct rx_desc {
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*/
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struct tdesc0 {
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u16 TSR; /* Transmit status register */
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u16 pktsize:14; /* Size of frame */
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u16 reserved:1;
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u16 owner:1; /* Who owns the buffer */
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__le16 TSR; /* Transmit status register */
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__le16 len; /* bits 0--13 - size of frame, bit 15 - owner */
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};
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struct pqinf { /* Priority queue info */
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u16 VID:12;
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u16 CFI:1;
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u16 priority:3;
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struct tdesc1 {
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__le16 vlan;
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u8 TCR;
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u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
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} __attribute__ ((__packed__));
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struct tdesc1 {
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struct pqinf pqinf;
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u8 TCR;
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u8 TCPLS:2;
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u8 reserved:2;
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u8 CMDZ:4;
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} __attribute__ ((__packed__));
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enum {
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TD_QUEUE = __constant_cpu_to_le16(0x8000)
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};
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struct td_buf {
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u32 pa_low;
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u16 pa_high;
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u16 bufsize:14;
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u16 reserved:1;
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u16 queue:1;
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__le32 pa_low;
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__le16 pa_high;
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__le16 size; /* bits 0--13 - size, bit 15 - queue */
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} __attribute__ ((__packed__));
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struct tx_desc {
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@@ -276,7 +244,7 @@ struct velocity_td_info {
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enum velocity_owner {
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OWNED_BY_HOST = 0,
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OWNED_BY_NIC = 1
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OWNED_BY_NIC = __constant_cpu_to_le16(0x8000)
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};
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@@ -1012,45 +980,45 @@ struct mac_regs {
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volatile u8 RCR;
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volatile u8 TCR;
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volatile u32 CR0Set; /* 0x08 */
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volatile u32 CR0Clr; /* 0x0C */
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volatile __le32 CR0Set; /* 0x08 */
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volatile __le32 CR0Clr; /* 0x0C */
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volatile u8 MARCAM[8]; /* 0x10 */
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volatile u32 DecBaseHi; /* 0x18 */
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volatile u16 DbfBaseHi; /* 0x1C */
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volatile u16 reserved_1E;
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volatile __le32 DecBaseHi; /* 0x18 */
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volatile __le16 DbfBaseHi; /* 0x1C */
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volatile __le16 reserved_1E;
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volatile u16 ISRCTL; /* 0x20 */
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volatile __le16 ISRCTL; /* 0x20 */
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volatile u8 TXESR;
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volatile u8 RXESR;
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volatile u32 ISR; /* 0x24 */
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volatile u32 IMR;
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volatile __le32 ISR; /* 0x24 */
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volatile __le32 IMR;
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volatile u32 TDStatusPort; /* 0x2C */
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volatile __le32 TDStatusPort; /* 0x2C */
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volatile u16 TDCSRSet; /* 0x30 */
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volatile __le16 TDCSRSet; /* 0x30 */
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volatile u8 RDCSRSet;
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volatile u8 reserved_33;
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volatile u16 TDCSRClr;
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volatile __le16 TDCSRClr;
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volatile u8 RDCSRClr;
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volatile u8 reserved_37;
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volatile u32 RDBaseLo; /* 0x38 */
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volatile u16 RDIdx; /* 0x3C */
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volatile u16 reserved_3E;
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volatile __le32 RDBaseLo; /* 0x38 */
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volatile __le16 RDIdx; /* 0x3C */
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volatile __le16 reserved_3E;
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volatile u32 TDBaseLo[4]; /* 0x40 */
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volatile __le32 TDBaseLo[4]; /* 0x40 */
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volatile u16 RDCSize; /* 0x50 */
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volatile u16 TDCSize; /* 0x52 */
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volatile u16 TDIdx[4]; /* 0x54 */
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volatile u16 tx_pause_timer; /* 0x5C */
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volatile u16 RBRDU; /* 0x5E */
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volatile __le16 RDCSize; /* 0x50 */
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volatile __le16 TDCSize; /* 0x52 */
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volatile __le16 TDIdx[4]; /* 0x54 */
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volatile __le16 tx_pause_timer; /* 0x5C */
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volatile __le16 RBRDU; /* 0x5E */
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volatile u32 FIFOTest0; /* 0x60 */
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volatile u32 FIFOTest1; /* 0x64 */
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volatile __le32 FIFOTest0; /* 0x60 */
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volatile __le32 FIFOTest1; /* 0x64 */
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volatile u8 CAMADDR; /* 0x68 */
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volatile u8 CAMCR; /* 0x69 */
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@@ -1063,18 +1031,18 @@ struct mac_regs {
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volatile u8 PHYSR1;
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volatile u8 MIICR;
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volatile u8 MIIADR;
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volatile u16 MIIDATA;
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volatile __le16 MIIDATA;
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volatile u16 SoftTimer0; /* 0x74 */
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volatile u16 SoftTimer1;
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volatile __le16 SoftTimer0; /* 0x74 */
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volatile __le16 SoftTimer1;
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volatile u8 CFGA; /* 0x78 */
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volatile u8 CFGB;
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volatile u8 CFGC;
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volatile u8 CFGD;
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volatile u16 DCFG; /* 0x7C */
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volatile u16 MCFG;
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volatile __le16 DCFG; /* 0x7C */
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volatile __le16 MCFG;
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volatile u8 TBIST; /* 0x80 */
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volatile u8 RBIST;
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@@ -1086,9 +1054,9 @@ struct mac_regs {
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volatile u8 rev_id;
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volatile u8 PORSTS;
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volatile u32 MIBData; /* 0x88 */
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volatile __le32 MIBData; /* 0x88 */
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volatile u16 EEWrData;
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volatile __le16 EEWrData;
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volatile u8 reserved_8E;
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volatile u8 BPMDWr;
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@@ -1098,7 +1066,7 @@ struct mac_regs {
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volatile u8 EECHKSUM; /* 0x92 */
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volatile u8 EECSR;
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volatile u16 EERdData; /* 0x94 */
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volatile __le16 EERdData; /* 0x94 */
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volatile u8 EADDR;
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volatile u8 EMBCMD;
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@@ -1112,22 +1080,22 @@ struct mac_regs {
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volatile u8 DEBUG;
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volatile u8 CHIPGCR;
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volatile u16 WOLCRSet; /* 0xA0 */
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volatile __le16 WOLCRSet; /* 0xA0 */
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volatile u8 PWCFGSet;
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volatile u8 WOLCFGSet;
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volatile u16 WOLCRClr; /* 0xA4 */
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volatile __le16 WOLCRClr; /* 0xA4 */
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volatile u8 PWCFGCLR;
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volatile u8 WOLCFGClr;
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volatile u16 WOLSRSet; /* 0xA8 */
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volatile u16 reserved_AA;
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volatile __le16 WOLSRSet; /* 0xA8 */
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volatile __le16 reserved_AA;
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volatile u16 WOLSRClr; /* 0xAC */
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volatile u16 reserved_AE;
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volatile __le16 WOLSRClr; /* 0xAC */
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volatile __le16 reserved_AE;
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volatile u16 PatternCRC[8]; /* 0xB0 */
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volatile u32 ByteMask[4][4]; /* 0xC0 */
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volatile __le16 PatternCRC[8]; /* 0xB0 */
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volatile __le32 ByteMask[4][4]; /* 0xC0 */
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} __attribute__ ((__packed__));
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@@ -1238,12 +1206,12 @@ typedef u8 MCAM_ADDR[ETH_ALEN];
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struct arp_packet {
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u8 dest_mac[ETH_ALEN];
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u8 src_mac[ETH_ALEN];
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u16 type;
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u16 ar_hrd;
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u16 ar_pro;
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__be16 type;
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__be16 ar_hrd;
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__be16 ar_pro;
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u8 ar_hln;
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u8 ar_pln;
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u16 ar_op;
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__be16 ar_op;
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u8 ar_sha[ETH_ALEN];
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u8 ar_sip[4];
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u8 ar_tha[ETH_ALEN];
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@@ -1253,7 +1221,7 @@ struct arp_packet {
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struct _magic_packet {
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u8 dest_mac[6];
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u8 src_mac[6];
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u16 type;
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__be16 type;
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u8 MAC[16][6];
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u8 password[6];
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} __attribute__ ((__packed__));
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