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drm/radeon/kms: fix divide by 0 in clocks code

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If the chip isn't initialised properly this can happen.
also fix return value in combios clocks function.

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
2009-12-01 09:13:40 +10:00
parent 7dde8a1965
commit 4b30b87042
2 changed files with 9 additions and 1 deletions
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8
drivers/gpu/drm/radeon/radeon_clocks.c
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@@ -44,6 +44,10 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
ref_div = ref_div =
RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
if (ref_div == 0)
return 0;
sclk = fb_div / ref_div; sclk = fb_div / ref_div;
post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
@@ -70,6 +74,10 @@ static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
ref_div = ref_div =
RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
if (ref_div == 0)
return 0;
mclk = fb_div / ref_div; mclk = fb_div / ref_div;
post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;

2
drivers/gpu/drm/radeon/radeon_combios.c
View File

@@ -495,7 +495,7 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
uint16_t sclk, mclk; uint16_t sclk, mclk;
if (rdev->bios == NULL) if (rdev->bios == NULL)
return NULL; return false;
pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
if (pll_info) { if (pll_info) {