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ARM: S5PC100: Modify SCLK_AUDIO{0,1,2} clock as sysclks

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This patch modify SCLK_AUDIO{0,1,2} to be initial as sysclks
on boot-time.

Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
Acked-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Seungwhan Youn
2010-10-14 10:35:23 +09:00
committed by Kukjin Kim
parent 068b432d74
commit 4cfd9c2530
1 changed files with 39 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

72
arch/arm/mach-s5pc100/clock.c
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@@ -848,6 +848,18 @@ struct clksrc_sources clk_src_group3 = {
.nr_sources = ARRAY_SIZE(clk_src_group3_list), .nr_sources = ARRAY_SIZE(clk_src_group3_list),
}; };
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
.id = 0,
.ctrlbit = (1 << 8),
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clk_src_group3,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
};
static struct clk *clk_src_group4_list[] = { static struct clk *clk_src_group4_list[] = {
[0] = &clk_mout_epll.clk, [0] = &clk_mout_epll.clk,
[1] = &clk_div_mpll.clk, [1] = &clk_div_mpll.clk,
@@ -862,6 +874,18 @@ struct clksrc_sources clk_src_group4 = {
.nr_sources = ARRAY_SIZE(clk_src_group4_list), .nr_sources = ARRAY_SIZE(clk_src_group4_list),
}; };
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
.id = 1,
.ctrlbit = (1 << 9),
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clk_src_group4,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
};
static struct clk *clk_src_group5_list[] = { static struct clk *clk_src_group5_list[] = {
[0] = &clk_mout_epll.clk, [0] = &clk_mout_epll.clk,
[1] = &clk_div_mpll.clk, [1] = &clk_div_mpll.clk,
@@ -875,6 +899,18 @@ struct clksrc_sources clk_src_group5 = {
.nr_sources = ARRAY_SIZE(clk_src_group5_list), .nr_sources = ARRAY_SIZE(clk_src_group5_list),
}; };
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
.id = 2,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clk_src_group5,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
};
static struct clk *clk_src_group6_list[] = { static struct clk *clk_src_group6_list[] = {
[0] = &s5p_clk_27m, [0] = &s5p_clk_27m,
[1] = &clk_vclk54m, [1] = &clk_vclk54m,
@@ -999,39 +1035,6 @@ static struct clksrc_clk clksrcs[] = {
}, },
.sources = &clk_src_group6, .sources = &clk_src_group6,
.reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
}, {
.clk = {
.name = "sclk_audio",
.id = 0,
.ctrlbit = (1 << 8),
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clk_src_group3,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_audio",
.id = 1,
.ctrlbit = (1 << 9),
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clk_src_group4,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_audio",
.id = 2,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clk_src_group5,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
}, { }, {
.clk = { .clk = {
.name = "sclk_lcd", .name = "sclk_lcd",
@@ -1179,6 +1182,9 @@ static struct clksrc_clk *sysclks[] = {
&clk_div_pclkd1, &clk_div_pclkd1,
&clk_div_cam, &clk_div_cam,
&clk_div_hdmi, &clk_div_hdmi,
&clk_sclk_audio0,
&clk_sclk_audio1,
&clk_sclk_audio2,
}; };
void __init_or_cpufreq s5pc100_setup_clocks(void) void __init_or_cpufreq s5pc100_setup_clocks(void)