[SPARC64]: Fix bogus flush instruction usage.
Some of the trap code was still assuming that alternate global %g6 was hard coded with current_thread_info(). Let's just consistently flush at KERNBASE when we need a pipeline synchronization. That's locked into the TLB and will always work. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller
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4753eb2ac7
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4da808c352
@ -259,7 +259,8 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
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ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
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or %l0, %l1, %l0
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stxa %l0, [%l7] ASI_DMMU
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flush %g6
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sethi %hi(KERNBASE), %l7
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flush %l7
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rdpr %wstate, %l1
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rdpr %otherwin, %l2
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srl %l1, 3, %l1
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