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[PATCH] smsc-ircc2: whitespace fixes

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IRDA: smsc-ircc2 - whitespace fixes.

Signed-off-by: Dmitry Torokhov <dtor@mail.ru>
Cc: Jean Tourrilhes <jt@hpl.hp.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Dmitry Torokhov
2005-09-06 15:19:17 -07:00
committed by Linus Torvalds
parent 4407c2b6b2
commit 527b6af413
2 changed files with 217 additions and 217 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/irda/smsc-ircc2.c
View File

@@ -1502,7 +1502,7 @@ static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
if (boguscount++ > 100) if (boguscount++ > 100)
break; break;
iir = inb(iobase + UART_IIR) & UART_IIR_ID; iir = inb(iobase + UART_IIR) & UART_IIR_ID;
} }
/*spin_unlock(&self->lock);*/ /*spin_unlock(&self->lock);*/
return IRQ_HANDLED; return IRQ_HANDLED;
@@ -2061,7 +2061,7 @@ static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfg
outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
sirbase = inb(cfgbase+1) << 2; sirbase = inb(cfgbase+1) << 2;
/* FIR iobase */ /* FIR iobase */
outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
firbase = inb(cfgbase+1) << 3; firbase = inb(cfgbase+1) << 3;

28
drivers/net/irda/smsc-ircc2.h
View File

@@ -112,10 +112,10 @@
#define IRCC_CFGA_COM 0x00 #define IRCC_CFGA_COM 0x00
#define IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK 0x87 #define IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK 0x87
#define IRCC_CFGA_IRDA_SIR_A 0x08 #define IRCC_CFGA_IRDA_SIR_A 0x08
#define IRCC_CFGA_ASK_SIR 0x10 #define IRCC_CFGA_ASK_SIR 0x10
#define IRCC_CFGA_IRDA_SIR_B 0x18 #define IRCC_CFGA_IRDA_SIR_B 0x18
#define IRCC_CFGA_IRDA_HDLC 0x20 #define IRCC_CFGA_IRDA_HDLC 0x20
#define IRCC_CFGA_IRDA_4PPM 0x28 #define IRCC_CFGA_IRDA_4PPM 0x28
#define IRCC_CFGA_CONSUMER 0x30 #define IRCC_CFGA_CONSUMER 0x30
#define IRCC_CFGA_RAW_IR 0x38 #define IRCC_CFGA_RAW_IR 0x38
@@ -130,7 +130,7 @@
#define IRCC_CFGB_LPBCK_TX_CRC 0x10 #define IRCC_CFGB_LPBCK_TX_CRC 0x10
#define IRCC_CFGB_NOWAIT 0x08 #define IRCC_CFGB_NOWAIT 0x08
#define IRCC_CFGB_STRING_MOVE 0x04 #define IRCC_CFGB_STRING_MOVE 0x04
#define IRCC_CFGB_DMA_BURST 0x02 #define IRCC_CFGB_DMA_BURST 0x02
#define IRCC_CFGB_DMA_ENABLE 0x01 #define IRCC_CFGB_DMA_ENABLE 0x01
#define IRCC_CFGB_MUX_COM 0x00 #define IRCC_CFGB_MUX_COM 0x00
@@ -141,11 +141,11 @@
/* Register block 3 - Identification Registers! */ /* Register block 3 - Identification Registers! */
#define IRCC_ID_HIGH 0x00 /* 0x10 */ #define IRCC_ID_HIGH 0x00 /* 0x10 */
#define IRCC_ID_LOW 0x01 /* 0xB8 */ #define IRCC_ID_LOW 0x01 /* 0xB8 */
#define IRCC_CHIP_ID 0x02 /* 0xF1 */ #define IRCC_CHIP_ID 0x02 /* 0xF1 */
#define IRCC_VERSION 0x03 /* 0x01 */ #define IRCC_VERSION 0x03 /* 0x01 */
#define IRCC_INTERFACE 0x04 /* low 4 = DMA, high 4 = IRQ */ #define IRCC_INTERFACE 0x04 /* low 4 = DMA, high 4 = IRQ */
#define IRCC_INTERFACE_DMA_MASK 0x0F /* low 4 = DMA, high 4 = IRQ */ #define IRCC_INTERFACE_DMA_MASK 0x0F /* low 4 = DMA, high 4 = IRQ */
#define IRCC_INTERFACE_IRQ_MASK 0xF0 /* low 4 = DMA, high 4 = IRQ */ #define IRCC_INTERFACE_IRQ_MASK 0xF0 /* low 4 = DMA, high 4 = IRQ */
/* Register block 4 - IrDA */ /* Register block 4 - IrDA */
#define IRCC_CONTROL 0x00 #define IRCC_CONTROL 0x00
@@ -163,10 +163,10 @@
/* Register block 5 - IrDA */ /* Register block 5 - IrDA */
#define IRCC_ATC 0x00 #define IRCC_ATC 0x00
#define IRCC_ATC_nPROGREADY 0x80 #define IRCC_ATC_nPROGREADY 0x80
#define IRCC_ATC_SPEED 0x40 #define IRCC_ATC_SPEED 0x40
#define IRCC_ATC_ENABLE 0x20 #define IRCC_ATC_ENABLE 0x20
#define IRCC_ATC_MASK 0xE0 #define IRCC_ATC_MASK 0xE0
#define IRCC_IRHALFDUPLEX_TIMEOUT 0x01 #define IRCC_IRHALFDUPLEX_TIMEOUT 0x01
@@ -178,8 +178,8 @@
*/ */
#define SMSC_IRCC2_MAX_SIR_SPEED 115200 #define SMSC_IRCC2_MAX_SIR_SPEED 115200
#define SMSC_IRCC2_FIR_CHIP_IO_EXTENT 8 #define SMSC_IRCC2_FIR_CHIP_IO_EXTENT 8
#define SMSC_IRCC2_SIR_CHIP_IO_EXTENT 8 #define SMSC_IRCC2_SIR_CHIP_IO_EXTENT 8
#define SMSC_IRCC2_FIFO_SIZE 16 #define SMSC_IRCC2_FIFO_SIZE 16
#define SMSC_IRCC2_FIFO_THRESHOLD 64 #define SMSC_IRCC2_FIFO_THRESHOLD 64
/* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */ /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */