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tg3: Prevent a PCIe tx glitch

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This patch prevents a PCIe tx glitch by allowing the transmitter to go
to a low power state.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
2009-11-02 14:25:06 +00:00
committed by David S. Miller
parent 3f0e3ad723
commit 52cdf8526f
2 changed files with 49 additions and 1 deletions
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26
drivers/net/tg3.h
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@@ -1953,10 +1953,34 @@
#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
/* Currently this is fixed. */
#define TG3_PHY_PCIE_ADDR 0x00
#define TG3_PHY_MII_ADDR 0x01
/* Tigon3 specific PHY MII registers. */
/*** Tigon3 specific PHY PCIE registers. ***/
#define TG3_PCIEPHY_BLOCK_ADDR 0x1f
#define TG3_PCIEPHY_XGXS_BLK1 0x0801
#define TG3_PCIEPHY_TXB_BLK 0x0861
#define TG3_PCIEPHY_BLOCK_SHIFT 4
/* TG3_PCIEPHY_TXB_BLK */
#define TG3_PCIEPHY_TX0CTRL1 0x15
#define TG3_PCIEPHY_TX0CTRL1_TXOCM 0x0003
#define TG3_PCIEPHY_TX0CTRL1_RDCTL 0x0008
#define TG3_PCIEPHY_TX0CTRL1_TXCMV 0x0030
#define TG3_PCIEPHY_TX0CTRL1_TKSEL 0x0040
#define TG3_PCIEPHY_TX0CTRL1_NB_EN 0x0400
/* TG3_PCIEPHY_XGXS_BLK1 */
#define TG3_PCIEPHY_PWRMGMT4 0x1a
#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000
/*** Tigon3 specific PHY MII registers. ***/
#define TG3_BMCR_SPEED1000 0x0040
#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */