[MIPS] Make csum_partial more readable
Use standard o32 register name instead of T0, T1, etc, like memcpy.S. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
committed by
Ralf Baechle
Ralf Baechle
parent
14b36af46a
commit
52ffe760ea
@@ -12,19 +12,23 @@
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#include <asm/regdef.h>
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#include <asm/regdef.h>
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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#define T0 ta0
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/*
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#define T1 ta1
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* As we are sharing code base with the mips32 tree (which use the o32 ABI
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#define T2 ta2
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* register definitions). We need to redefine the register definitions from
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#define T3 ta3
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* the n64 ABI register naming to the o32 ABI register naming.
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#define T4 t0
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*/
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#define T7 t3
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#undef t0
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#else
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#undef t1
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#define T0 t0
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#undef t2
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#define T1 t1
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#undef t3
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#define T2 t2
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#define t0 $8
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#define T3 t3
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#define t1 $9
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#define T4 t4
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#define t2 $10
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#define T7 t7
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#endif
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#endif
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#define ADDC(sum,reg) \
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#define ADDC(sum,reg) \
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@@ -64,37 +68,37 @@
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/* unknown src alignment and < 8 bytes to go */
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/* unknown src alignment and < 8 bytes to go */
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small_csumcpy:
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small_csumcpy:
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move a1, T2
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move a1, t2
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andi T0, a1, 4
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andi t0, a1, 4
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beqz T0, 1f
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beqz t0, 1f
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andi T0, a1, 2
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andi t0, a1, 2
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/* Still a full word to go */
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/* Still a full word to go */
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ulw T1, (src)
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ulw t1, (src)
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PTR_ADDIU src, 4
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PTR_ADDIU src, 4
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ADDC(sum, T1)
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ADDC(sum, t1)
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1: move T1, zero
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1: move t1, zero
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beqz T0, 1f
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beqz t0, 1f
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andi T0, a1, 1
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andi t0, a1, 1
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/* Still a halfword to go */
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/* Still a halfword to go */
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ulhu T1, (src)
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ulhu t1, (src)
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PTR_ADDIU src, 2
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PTR_ADDIU src, 2
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1: beqz T0, 1f
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1: beqz t0, 1f
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sll T1, T1, 16
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sll t1, t1, 16
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lbu T2, (src)
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lbu t2, (src)
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nop
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nop
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#ifdef __MIPSEB__
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#ifdef __MIPSEB__
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sll T2, T2, 8
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sll t2, t2, 8
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#endif
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#endif
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or T1, T2
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or t1, t2
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1: ADDC(sum, T1)
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1: ADDC(sum, t1)
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/* fold checksum */
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/* fold checksum */
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sll v1, sum, 16
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sll v1, sum, 16
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@@ -104,7 +108,7 @@ small_csumcpy:
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addu sum, v1
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addu sum, v1
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/* odd buffer alignment? */
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/* odd buffer alignment? */
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beqz T7, 1f
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beqz t7, 1f
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nop
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nop
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sll v1, sum, 8
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sll v1, sum, 8
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srl sum, sum, 8
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srl sum, sum, 8
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@@ -122,25 +126,25 @@ small_csumcpy:
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.align 5
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.align 5
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LEAF(csum_partial)
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LEAF(csum_partial)
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move sum, zero
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move sum, zero
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move T7, zero
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move t7, zero
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sltiu t8, a1, 0x8
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sltiu t8, a1, 0x8
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bnez t8, small_csumcpy /* < 8 bytes to copy */
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bnez t8, small_csumcpy /* < 8 bytes to copy */
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move T2, a1
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move t2, a1
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beqz a1, out
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beqz a1, out
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andi T7, src, 0x1 /* odd buffer? */
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andi t7, src, 0x1 /* odd buffer? */
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hword_align:
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hword_align:
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beqz T7, word_align
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beqz t7, word_align
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andi t8, src, 0x2
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andi t8, src, 0x2
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lbu T0, (src)
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lbu t0, (src)
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LONG_SUBU a1, a1, 0x1
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LONG_SUBU a1, a1, 0x1
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#ifdef __MIPSEL__
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#ifdef __MIPSEL__
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sll T0, T0, 8
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sll t0, t0, 8
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#endif
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#endif
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ADDC(sum, T0)
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ADDC(sum, t0)
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PTR_ADDU src, src, 0x1
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PTR_ADDU src, src, 0x1
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andi t8, src, 0x2
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andi t8, src, 0x2
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@@ -148,9 +152,9 @@ word_align:
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beqz t8, dword_align
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beqz t8, dword_align
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sltiu t8, a1, 56
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sltiu t8, a1, 56
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lhu T0, (src)
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lhu t0, (src)
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LONG_SUBU a1, a1, 0x2
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LONG_SUBU a1, a1, 0x2
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ADDC(sum, T0)
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ADDC(sum, t0)
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sltiu t8, a1, 56
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sltiu t8, a1, 56
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PTR_ADDU src, src, 0x2
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PTR_ADDU src, src, 0x2
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@@ -162,9 +166,9 @@ dword_align:
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beqz t8, qword_align
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beqz t8, qword_align
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andi t8, src, 0x8
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andi t8, src, 0x8
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lw T0, 0x00(src)
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lw t0, 0x00(src)
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LONG_SUBU a1, a1, 0x4
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LONG_SUBU a1, a1, 0x4
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ADDC(sum, T0)
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ADDC(sum, t0)
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PTR_ADDU src, src, 0x4
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PTR_ADDU src, src, 0x4
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andi t8, src, 0x8
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andi t8, src, 0x8
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@@ -172,11 +176,11 @@ qword_align:
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beqz t8, oword_align
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beqz t8, oword_align
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andi t8, src, 0x10
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andi t8, src, 0x10
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lw T0, 0x00(src)
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lw t0, 0x00(src)
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lw T1, 0x04(src)
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lw t1, 0x04(src)
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LONG_SUBU a1, a1, 0x8
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LONG_SUBU a1, a1, 0x8
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ADDC(sum, T0)
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ADDC(sum, t0)
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ADDC(sum, T1)
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ADDC(sum, t1)
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PTR_ADDU src, src, 0x8
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PTR_ADDU src, src, 0x8
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andi t8, src, 0x10
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andi t8, src, 0x10
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@@ -184,46 +188,46 @@ oword_align:
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beqz t8, begin_movement
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beqz t8, begin_movement
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LONG_SRL t8, a1, 0x7
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LONG_SRL t8, a1, 0x7
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lw T3, 0x08(src)
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lw t3, 0x08(src)
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lw T4, 0x0c(src)
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lw t4, 0x0c(src)
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lw T0, 0x00(src)
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lw t0, 0x00(src)
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lw T1, 0x04(src)
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lw t1, 0x04(src)
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ADDC(sum, T3)
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ADDC(sum, t3)
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ADDC(sum, T4)
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ADDC(sum, t4)
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ADDC(sum, T0)
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ADDC(sum, t0)
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ADDC(sum, T1)
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ADDC(sum, t1)
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LONG_SUBU a1, a1, 0x10
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LONG_SUBU a1, a1, 0x10
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PTR_ADDU src, src, 0x10
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PTR_ADDU src, src, 0x10
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LONG_SRL t8, a1, 0x7
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LONG_SRL t8, a1, 0x7
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begin_movement:
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begin_movement:
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beqz t8, 1f
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beqz t8, 1f
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andi T2, a1, 0x40
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andi t2, a1, 0x40
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move_128bytes:
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move_128bytes:
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CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4)
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CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
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CSUM_BIGCHUNK(src, 0x20, sum, T0, T1, T3, T4)
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CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
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CSUM_BIGCHUNK(src, 0x40, sum, T0, T1, T3, T4)
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CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
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CSUM_BIGCHUNK(src, 0x60, sum, T0, T1, T3, T4)
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CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
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LONG_SUBU t8, t8, 0x01
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LONG_SUBU t8, t8, 0x01
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bnez t8, move_128bytes
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bnez t8, move_128bytes
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PTR_ADDU src, src, 0x80
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PTR_ADDU src, src, 0x80
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1:
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1:
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beqz T2, 1f
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beqz t2, 1f
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andi T2, a1, 0x20
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andi t2, a1, 0x20
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move_64bytes:
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move_64bytes:
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CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4)
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CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
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CSUM_BIGCHUNK(src, 0x20, sum, T0, T1, T3, T4)
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CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
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PTR_ADDU src, src, 0x40
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PTR_ADDU src, src, 0x40
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1:
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1:
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beqz T2, do_end_words
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beqz t2, do_end_words
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andi t8, a1, 0x1c
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andi t8, a1, 0x1c
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move_32bytes:
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move_32bytes:
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CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4)
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CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
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andi t8, a1, 0x1c
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andi t8, a1, 0x1c
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PTR_ADDU src, src, 0x20
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PTR_ADDU src, src, 0x20
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@@ -232,22 +236,22 @@ do_end_words:
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LONG_SRL t8, t8, 0x2
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LONG_SRL t8, t8, 0x2
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end_words:
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end_words:
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lw T0, (src)
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lw t0, (src)
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LONG_SUBU t8, t8, 0x1
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LONG_SUBU t8, t8, 0x1
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ADDC(sum, T0)
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ADDC(sum, t0)
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bnez t8, end_words
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bnez t8, end_words
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PTR_ADDU src, src, 0x4
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PTR_ADDU src, src, 0x4
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maybe_end_cruft:
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maybe_end_cruft:
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andi T2, a1, 0x3
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andi t2, a1, 0x3
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small_memcpy:
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small_memcpy:
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j small_csumcpy; move a1, T2 /* XXX ??? */
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j small_csumcpy; move a1, t2 /* XXX ??? */
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beqz t2, out
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beqz t2, out
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move a1, T2
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move a1, t2
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end_bytes:
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end_bytes:
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lb T0, (src)
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lb t0, (src)
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LONG_SUBU a1, a1, 0x1
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LONG_SUBU a1, a1, 0x1
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bnez a2, end_bytes
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bnez a2, end_bytes
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PTR_ADDU src, src, 0x1
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PTR_ADDU src, src, 0x1
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