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oprofile, x86: Introduce struct ibs_state

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This patch introduces struct ibs_state that will extended by additinal
members in follow-on patches.

Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
Robert Richter
2010-09-21 17:58:15 +02:00
parent fc889aa23f
commit 53b39e9480
1 changed files with 18 additions and 11 deletions
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29
arch/x86/oprofile/op_model_amd.c
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@@ -48,7 +48,7 @@ static unsigned long reset_value[NUM_VIRT_COUNTERS];
static u32 ibs_caps; static u32 ibs_caps;
struct op_ibs_config { struct ibs_config {
unsigned long op_enabled; unsigned long op_enabled;
unsigned long fetch_enabled; unsigned long fetch_enabled;
unsigned long max_cnt_fetch; unsigned long max_cnt_fetch;
@@ -57,8 +57,12 @@ struct op_ibs_config {
unsigned long dispatched_ops; unsigned long dispatched_ops;
}; };
static struct op_ibs_config ibs_config; struct ibs_state {
static u64 ibs_op_ctl; u64 ibs_op_ctl;
};
static struct ibs_config ibs_config;
static struct ibs_state ibs_state;
/* /*
* IBS cpuid feature detection * IBS cpuid feature detection
@@ -219,7 +223,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
oprofile_write_commit(&entry); oprofile_write_commit(&entry);
/* reenable the IRQ */ /* reenable the IRQ */
ctl = op_amd_randomize_ibs_op(ibs_op_ctl); ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
wrmsrl(MSR_AMD64_IBSOPCTL, ctl); wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
} }
} }
@@ -232,6 +236,8 @@ static inline void op_amd_start_ibs(void)
if (!ibs_caps) if (!ibs_caps)
return; return;
memset(&ibs_state, 0, sizeof(ibs_state));
if (ibs_config.fetch_enabled) { if (ibs_config.fetch_enabled) {
val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT; val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
@@ -240,13 +246,13 @@ static inline void op_amd_start_ibs(void)
} }
if (ibs_config.op_enabled) { if (ibs_config.op_enabled) {
ibs_op_ctl = ibs_config.max_cnt_op >> 4; val = ibs_config.max_cnt_op >> 4;
if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) { if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
/* /*
* IbsOpCurCnt not supported. See * IbsOpCurCnt not supported. See
* op_amd_randomize_ibs_op() for details. * op_amd_randomize_ibs_op() for details.
*/ */
ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL); val = clamp(val, 0x0081ULL, 0xFF80ULL);
} else { } else {
/* /*
* The start value is randomized with a * The start value is randomized with a
@@ -254,12 +260,13 @@ static inline void op_amd_start_ibs(void)
* with the half of the randomized range. Also * with the half of the randomized range. Also
* avoid underflows. * avoid underflows.
*/ */
ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET, val = min(val + IBS_RANDOM_MAXCNT_OFFSET,
IBS_OP_MAX_CNT); IBS_OP_MAX_CNT);
} }
ibs_op_ctl |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
ibs_op_ctl |= IBS_OP_ENABLE; val |= IBS_OP_ENABLE;
val = op_amd_randomize_ibs_op(ibs_op_ctl); ibs_state.ibs_op_ctl = val;
val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
wrmsrl(MSR_AMD64_IBSOPCTL, val); wrmsrl(MSR_AMD64_IBSOPCTL, val);
} }
} }