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Blackfin arch: Fix Bug - System with EMAC driver enabled - Core not idling

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- Disable all bits in SIC_IWR unless we are going into a real (DPMC)
   power saving mode. Any Interrupt can wake the core form it's idle state.

 - Remove deep sleep mode as it is not going to be used anywhere:
   We support sleep, sleep deeper and hibernate.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich
2008-08-06 17:55:32 +08:00
committed by Bryan Wu
parent 15b0753689
commit 56f5f59052
8 changed files with 8 additions and 93 deletions
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56
arch/blackfin/mach-common/dpmc_modes.S
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@ -78,62 +78,6 @@ ENTRY(_hibernate_mode)
jump .Lforever;
ENDPROC(_hibernate_mode)
ENTRY(_deep_sleep)
[--SP] = ( R7:0, P5:0 );
[--SP] = RETS;
CLI R4;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
call _set_dram_srfs;
/* Clear all the interrupts,bits sticky */
R0 = 0xFFFF (Z);
call _set_rtc_istat
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
R0 = W[P0](z);
BITSET (R0, 5);
W[P0] = R0.L;
call _test_pll_locked;
SSYNC;
IDLE;
call _unset_dram_srfs;
call _test_pll_locked;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
R0 = w[p0](z);
BITCLR (R0, 3);
BITCLR (R0, 5);
BITCLR (R0, 8);
w[p0] = R0;
IDLE;
call _test_pll_locked;
STI R4;
RETS = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
ENDPROC(_deep_sleep)
ENTRY(_sleep_deeper)
[--SP] = ( R7:0, P5:0 );
[--SP] = RETS;