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ARM: Add Tauros2 L2 cache controller support

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Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Lennert Buytenhek
2009-11-24 19:33:52 +02:00
committed by Nicolas Pitre
parent edabd38e1a
commit 573a652fb0
6 changed files with 291 additions and 2 deletions
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11
arch/arm/include/asm/hardware/cache-tauros2.h Normal file
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/*
* arch/arm/include/asm/hardware/cache-tauros2.h
*
* Copyright (C) 2008 Marvell Semiconductor
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
extern void __init tauros2_init(void);