bnx2x: Re-factor the initialization code
Moving the code to a more logical place and beautifying it. No real change in behavior. Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein
committed by
David S. Miller
David S. Miller
parent
e4ed711337
commit
573f203574
@ -11,85 +11,68 @@
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Vladislav Zolotarov <vladz@broadcom.com>
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*/
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#ifndef BNX2X_INIT_OPS_H
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#define BNX2X_INIT_OPS_H
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static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
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static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
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static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
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u32 len)
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{
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int i;
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u32 i;
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for (i = 0; i < len; i++) {
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for (i = 0; i < len; i++)
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REG_WR(bp, addr + i*4, data[i]);
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if (!(i % 10000)) {
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touch_softlockup_watchdog();
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cpu_relax();
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}
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}
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}
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static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
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u16 len)
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u32 len)
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{
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int i;
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u32 i;
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for (i = 0; i < len; i++) {
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for (i = 0; i < len; i++)
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REG_WR_IND(bp, addr + i*4, data[i]);
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if (!(i % 10000)) {
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touch_softlockup_watchdog();
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cpu_relax();
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}
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}
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}
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static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
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{
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int offset = 0;
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if (bp->dmae_ready) {
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while (len > DMAE_LEN32_WR_MAX) {
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bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
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addr + offset, DMAE_LEN32_WR_MAX);
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offset += DMAE_LEN32_WR_MAX * 4;
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len -= DMAE_LEN32_WR_MAX;
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}
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bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
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addr + offset, len);
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} else
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bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
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if (bp->dmae_ready)
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bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
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else
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bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
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}
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static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
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{
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u32 buf_len = (((len * 4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len * 4));
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u32 buf_len32 = buf_len / 4;
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int i;
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u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
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u32 buf_len32 = buf_len/4;
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u32 i;
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memset(bp->gunzip_buf, fill, buf_len);
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memset(GUNZIP_BUF(bp), (u8)fill, buf_len);
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for (i = 0; i < len; i += buf_len32) {
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u32 cur_len = min(buf_len32, len - i);
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bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
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bnx2x_write_big_buf(bp, addr + i*4, cur_len);
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}
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}
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static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
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u32 len64)
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{
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u32 buf_len32 = FW_BUF_SIZE / 4;
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u32 len = len64 * 2;
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u32 buf_len32 = FW_BUF_SIZE/4;
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u32 len = len64*2;
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u64 data64 = 0;
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int i;
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u32 i;
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/* 64 bit value is in a blob: first low DWORD, then high DWORD */
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data64 = HILO_U64((*(data + 1)), (*data));
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len64 = min((u32)(FW_BUF_SIZE/8), len64);
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for (i = 0; i < len64; i++) {
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u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i;
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u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i;
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*pdata = data64;
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}
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@ -97,7 +80,7 @@ static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
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for (i = 0; i < len; i += buf_len32) {
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u32 cur_len = min(buf_len32, len - i);
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bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
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bnx2x_write_big_buf(bp, addr + i*4, cur_len);
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}
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}
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@ -118,97 +101,81 @@ static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
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static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, const u8 *data)
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{
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IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
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data = bp->tsem_int_table_data;
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else IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
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data = bp->csem_int_table_data;
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else IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
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data = bp->usem_int_table_data;
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else IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
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data = bp->xsem_int_table_data;
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else IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
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data = bp->tsem_pram_data;
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else IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
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data = bp->csem_pram_data;
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else IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
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data = bp->usem_pram_data;
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else IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
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data = bp->xsem_pram_data;
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data = INIT_TSEM_INT_TABLE_DATA(bp);
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else
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IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
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data = INIT_CSEM_INT_TABLE_DATA(bp);
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else
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IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
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data = INIT_USEM_INT_TABLE_DATA(bp);
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else
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IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
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data = INIT_XSEM_INT_TABLE_DATA(bp);
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else
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IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
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data = INIT_TSEM_PRAM_DATA(bp);
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else
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IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
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data = INIT_CSEM_PRAM_DATA(bp);
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else
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IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
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data = INIT_USEM_PRAM_DATA(bp);
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else
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IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
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data = INIT_XSEM_PRAM_DATA(bp);
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return data;
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}
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static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
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{
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int offset = 0;
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if (bp->dmae_ready) {
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while (len > DMAE_LEN32_WR_MAX) {
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bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
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addr + offset, DMAE_LEN32_WR_MAX);
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offset += DMAE_LEN32_WR_MAX * 4;
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len -= DMAE_LEN32_WR_MAX;
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}
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bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
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addr + offset, len);
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} else
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bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len);
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if (bp->dmae_ready)
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bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
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else
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bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
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}
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static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
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u32 len)
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{
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/* This is needed for NO_ZIP mode, currently supported
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in little endian mode only */
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data = (const u32*)bnx2x_sel_blob(bp, addr, (const u8*)data);
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data = (const u32 *)bnx2x_sel_blob(bp, addr, (const u8 *)data);
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if ((len * 4) > FW_BUF_SIZE) {
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BNX2X_ERR("LARGE DMAE OPERATION ! "
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"addr 0x%x len 0x%x\n", addr, len*4);
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return;
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}
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memcpy(bp->gunzip_buf, data, len * 4);
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bnx2x_write_big_buf_wb(bp, addr, len);
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if (bp->dmae_ready)
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VIRT_WR_DMAE_LEN(bp, data, addr, len);
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else
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bnx2x_init_ind_wr(bp, addr, data, len);
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}
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static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr,
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u32 len, u32 blob_off)
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static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, u32 blob_off)
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{
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int rc, i;
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const u8 *data = NULL;
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const u8 *data = NULL;
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int rc;
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u32 i;
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data = bnx2x_sel_blob(bp, addr, data) + 4*blob_off;
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if (data == NULL) {
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panic("Blob not found for addr 0x%x\n", addr);
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return;
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}
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data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
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rc = bnx2x_gunzip(bp, data, len);
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if (rc) {
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BNX2X_ERR("gunzip failed ! addr 0x%x rc %d\n", addr, rc);
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BNX2X_ERR("blob_offset=0x%x\n", blob_off);
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if (rc)
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return;
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}
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/* gunzip_outlen is in dwords */
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len = bp->gunzip_outlen;
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len = GUNZIP_OUTLEN(bp);
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for (i = 0; i < len; i++)
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((u32 *)bp->gunzip_buf)[i] =
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cpu_to_le32(((u32 *)bp->gunzip_buf)[i]);
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((u32 *)GUNZIP_BUF(bp))[i] =
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cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]);
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bnx2x_write_big_buf_wb(bp, addr, len);
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}
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static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
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{
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int hw_wr, i;
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u16 op_start =
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bp->init_ops_offsets[BLOCK_OPS_IDX(block,stage,STAGE_START)];
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INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, STAGE_START)];
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u16 op_end =
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bp->init_ops_offsets[BLOCK_OPS_IDX(block,stage,STAGE_END)];
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INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, STAGE_END)];
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union init_op *op;
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u32 op_type, addr, len;
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int hw_wr;
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u32 i, op_type, addr, len;
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const u32 *data, *data_base;
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/* If empty block */
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@ -222,11 +189,11 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
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else
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hw_wr = OP_WR_ASIC;
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data_base = bp->init_data;
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data_base = INIT_DATA(bp);
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for (i = op_start; i < op_end; i++) {
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op = (union init_op *)&(bp->init_ops[i]);
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op = (union init_op *)&(INIT_OPS(bp)[i]);
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op_type = op->str_wr.op;
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addr = op->str_wr.offset;
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@ -234,7 +201,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
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data = data_base + op->str_wr.data_off;
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/* HW/EMUL specific */
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if (unlikely((op_type > OP_WB) && (op_type == hw_wr)))
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if ((op_type > OP_WB) && (op_type == hw_wr))
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op_type = OP_WR;
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switch (op_type) {
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@ -265,34 +232,178 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
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break;
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default:
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/* happens whenever an op is of a diff HW */
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#if 0
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DP(NETIF_MSG_HW, "skipping init operation "
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"index %d[%d:%d]: type %d addr 0x%x "
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"len %d(0x%x)\n",
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i, op_start, op_end, op_type, addr, len, len);
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#endif
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break;
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}
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}
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}
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/* PXP */
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static void bnx2x_init_pxp(struct bnx2x *bp)
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{
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u16 devctl;
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int r_order, w_order;
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u32 val, i;
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pci_read_config_word(bp->pdev,
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bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
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DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
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w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
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if (bp->mrrs == -1)
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r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
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else {
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DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
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r_order = bp->mrrs;
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}
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/****************************************************************************
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* PXP Arbiter
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****************************************************************************/
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/*
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* This code configures the PCI read/write arbiter
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* which implements a weighted round robin
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* between the virtual queues in the chip.
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*
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* The values were derived for each PCI max payload and max request size.
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* since max payload and max request size are only known at run time,
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* this is done as a separate init stage.
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*/
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#define NUM_WR_Q 13
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#define NUM_RD_Q 29
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#define MAX_RD_ORD 3
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#define MAX_WR_ORD 2
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/* configuration for one arbiter queue */
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struct arb_line {
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int l;
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int add;
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int ubound;
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};
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/* derived configuration for each read queue for each max request size */
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static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
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/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
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{ {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
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{ {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
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{ {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
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{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
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/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
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};
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/* derived configuration for each write queue for each max request size */
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static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
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/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
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{ {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
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{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
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{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
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{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
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{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
|
||||
{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
|
||||
{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
|
||||
{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
|
||||
/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
|
||||
{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
|
||||
{ {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
|
||||
{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
|
||||
};
|
||||
|
||||
/* register addresses for read queues */
|
||||
static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
|
||||
/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND0},
|
||||
{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
|
||||
PXP2_REG_PSWRQ_BW_UB1},
|
||||
{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
|
||||
PXP2_REG_PSWRQ_BW_UB2},
|
||||
{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
|
||||
PXP2_REG_PSWRQ_BW_UB3},
|
||||
{PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND4},
|
||||
{PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND5},
|
||||
{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
|
||||
PXP2_REG_PSWRQ_BW_UB6},
|
||||
{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
|
||||
PXP2_REG_PSWRQ_BW_UB7},
|
||||
{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
|
||||
PXP2_REG_PSWRQ_BW_UB8},
|
||||
/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
|
||||
PXP2_REG_PSWRQ_BW_UB9},
|
||||
{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
|
||||
PXP2_REG_PSWRQ_BW_UB10},
|
||||
{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
|
||||
PXP2_REG_PSWRQ_BW_UB11},
|
||||
{PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND12},
|
||||
{PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND13},
|
||||
{PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND14},
|
||||
{PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND15},
|
||||
{PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND16},
|
||||
{PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND17},
|
||||
{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND18},
|
||||
/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND19},
|
||||
{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND20},
|
||||
{PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND22},
|
||||
{PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND23},
|
||||
{PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND24},
|
||||
{PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND25},
|
||||
{PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND26},
|
||||
{PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND27},
|
||||
{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
|
||||
PXP2_REG_PSWRQ_BW_UB28}
|
||||
};
|
||||
|
||||
/* register addresses for write queues */
|
||||
static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
|
||||
/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
|
||||
PXP2_REG_PSWRQ_BW_UB1},
|
||||
{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
|
||||
PXP2_REG_PSWRQ_BW_UB2},
|
||||
{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
|
||||
PXP2_REG_PSWRQ_BW_UB3},
|
||||
{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
|
||||
PXP2_REG_PSWRQ_BW_UB6},
|
||||
{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
|
||||
PXP2_REG_PSWRQ_BW_UB7},
|
||||
{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
|
||||
PXP2_REG_PSWRQ_BW_UB8},
|
||||
{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
|
||||
PXP2_REG_PSWRQ_BW_UB9},
|
||||
{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
|
||||
PXP2_REG_PSWRQ_BW_UB10},
|
||||
{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
|
||||
PXP2_REG_PSWRQ_BW_UB11},
|
||||
/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
|
||||
PXP2_REG_PSWRQ_BW_UB28},
|
||||
{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
|
||||
PXP2_REG_RQ_BW_WR_UBOUND29},
|
||||
{PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
|
||||
PXP2_REG_RQ_BW_WR_UBOUND30}
|
||||
};
|
||||
|
||||
static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, int w_order)
|
||||
{
|
||||
u32 val, i;
|
||||
|
||||
if (r_order > MAX_RD_ORD) {
|
||||
DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
|
||||
@ -367,6 +478,11 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
|
||||
REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
|
||||
|
||||
if (CHIP_IS_E1H(bp)) {
|
||||
/* MPS w_order optimal TH presently TH
|
||||
* 128 0 0 2
|
||||
* 256 1 1 3
|
||||
* >=512 2 2 3
|
||||
*/
|
||||
val = ((w_order == 0) ? 2 : 3);
|
||||
REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
|
||||
REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
|
||||
@ -382,61 +498,4 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Description:
|
||||
* Calculates crc 8 on a word value: polynomial 0-1-2-8
|
||||
* Code was translated from Verilog.
|
||||
****************************************************************************/
|
||||
static u8 calc_crc8(u32 data, u8 crc)
|
||||
{
|
||||
u8 D[32];
|
||||
u8 NewCRC[8];
|
||||
u8 C[8];
|
||||
u8 crc_res;
|
||||
u8 i;
|
||||
|
||||
/* split the data into 31 bits */
|
||||
for (i = 0; i < 32; i++) {
|
||||
D[i] = data & 1;
|
||||
data = data >> 1;
|
||||
}
|
||||
|
||||
/* split the crc into 8 bits */
|
||||
for (i = 0; i < 8; i++) {
|
||||
C[i] = crc & 1;
|
||||
crc = crc >> 1;
|
||||
}
|
||||
|
||||
NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
|
||||
D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
|
||||
C[6] ^ C[7];
|
||||
NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
|
||||
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
|
||||
D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
|
||||
NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
|
||||
D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
|
||||
C[0] ^ C[1] ^ C[4] ^ C[5];
|
||||
NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
|
||||
D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
|
||||
C[1] ^ C[2] ^ C[5] ^ C[6];
|
||||
NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
|
||||
D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
|
||||
C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
|
||||
NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
|
||||
D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
|
||||
C[3] ^ C[4] ^ C[7];
|
||||
NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
|
||||
D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
|
||||
C[5];
|
||||
NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
|
||||
D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
|
||||
C[6];
|
||||
|
||||
crc_res = 0;
|
||||
for (i = 0; i < 8; i++)
|
||||
crc_res |= (NewCRC[i] << i);
|
||||
|
||||
return crc_res;
|
||||
}
|
||||
|
||||
#endif /* BNX2X_INIT_OPS_H */
|
||||
|
||||
Reference in New Issue
Block a user