ARM: 6834/1: perf: reset counters on all CPUs during initialisation
ARMv7 dictates that the interrupt-enable and count-enable registers for each PMU counter are UNKNOWN following core reset. This patch adds a new (optional) function pointer to struct arm_pmu for resetting the PMU state during init. The reset function is called on each CPU via an arch_initcall in the generic ARM perf_event code and allows the PMU backend to write sane values to any UNKNOWN registers. Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King
parent
d25d3b4c4d
commit
574b69cbb6
@ -79,6 +79,7 @@ struct arm_pmu {
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void (*write_counter)(int idx, u32 val);
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void (*start)(void);
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void (*stop)(void);
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void (*reset)(void *);
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const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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@ -624,6 +625,19 @@ static struct pmu pmu = {
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#include "perf_event_v6.c"
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#include "perf_event_v7.c"
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/*
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* Ensure the PMU has sane values out of reset.
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* This requires SMP to be available, so exists as a separate initcall.
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*/
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static int __init
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armpmu_reset(void)
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{
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if (armpmu && armpmu->reset)
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return on_each_cpu(armpmu->reset, NULL, 1);
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return 0;
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}
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arch_initcall(armpmu_reset);
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static int __init
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init_hw_perf_events(void)
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{
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