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[BNX2]: Add write posting comment.

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Add comment to explain why we cannot read back after chip reset
before delaying.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
2007-08-28 15:39:42 -07:00
committed by David S. Miller
parent 8e54588161
commit 594a9dfae7
1 changed files with 4 additions and 0 deletions
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4
drivers/net/bnx2.c
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@@ -3934,6 +3934,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
/* Chip reset. */ /* Chip reset. */
REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
/* Reading back any register after chip reset will hang the
* bus on 5706 A0 and A1. The msleep below provides plenty
* of margin for write posting.
*/
if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
(CHIP_ID(bp) == CHIP_ID_5706_A1)) (CHIP_ID(bp) == CHIP_ID_5706_A1))
msleep(20); msleep(20);