Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (74 commits) PCI: make msi_free_irqs() to use msix_mask_irq() instead of open coded write PCI: Fix the NIU MSI-X problem in a better way PCI ASPM: remove get_root_port_link PCI ASPM: cleanup pcie_aspm_sanity_check PCI ASPM: remove has_switch field PCI ASPM: cleanup calc_Lx_latency PCI ASPM: cleanup pcie_aspm_get_cap_device PCI ASPM: cleanup clkpm checks PCI ASPM: cleanup __pcie_aspm_check_state_one PCI ASPM: cleanup initialization PCI ASPM: cleanup change input argument of aspm functions PCI ASPM: cleanup misc in struct pcie_link_state PCI ASPM: cleanup clkpm state in struct pcie_link_state PCI ASPM: cleanup latency field in struct pcie_link_state PCI ASPM: cleanup aspm state field in struct pcie_link_state PCI ASPM: fix typo in struct pcie_link_state PCI: drivers/pci/slot.c should depend on CONFIG_SYSFS PCI: remove redundant __msi_set_enable() PCI PM: consistently use type bool for wake enable variable x86/ACPI: Correct maximum allowed _CRS returned resources and warn if exceeded ...
This commit is contained in:
Linus Torvalds
@@ -485,6 +485,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
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pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
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pmcsr |= state;
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break;
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case PCI_D3hot:
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case PCI_D3cold:
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case PCI_UNKNOWN: /* Boot-up */
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if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
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&& !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
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@@ -1208,7 +1210,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable)
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* Error code depending on the platform is returned if both the platform and
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* the native mechanism fail to enable the generation of wake-up events
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*/
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int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
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int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
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{
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int error = 0;
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bool pme_done = false;
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@@ -1287,15 +1289,14 @@ pci_power_t pci_target_state(struct pci_dev *dev)
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default:
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target_state = state;
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}
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} else if (!dev->pm_cap) {
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target_state = PCI_D0;
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} else if (device_may_wakeup(&dev->dev)) {
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/*
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* Find the deepest state from which the device can generate
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* wake-up events, make it the target state and enable device
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* to generate PME#.
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*/
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if (!dev->pm_cap)
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return PCI_POWER_ERROR;
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if (dev->pme_support) {
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while (target_state
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&& !(dev->pme_support & (1 << target_state)))
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@@ -1532,7 +1533,7 @@ pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
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if (!pin)
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return -1;
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while (dev->bus->parent) {
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while (!pci_is_root_bus(dev->bus)) {
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pin = pci_swizzle_interrupt_pin(dev, pin);
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dev = dev->bus->self;
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}
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@@ -1552,7 +1553,7 @@ u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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u8 pin = *pinp;
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while (dev->bus->parent) {
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while (!pci_is_root_bus(dev->bus)) {
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pin = pci_swizzle_interrupt_pin(dev, pin);
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dev = dev->bus->self;
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}
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@@ -2058,111 +2059,177 @@ int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
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EXPORT_SYMBOL(pci_set_dma_seg_boundary);
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#endif
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static int __pcie_flr(struct pci_dev *dev, int probe)
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static int pcie_flr(struct pci_dev *dev, int probe)
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{
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u16 status;
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int i;
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int pos;
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u32 cap;
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int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP);
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u16 status;
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if (!exppos)
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pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (!pos)
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return -ENOTTY;
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pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap);
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pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
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if (!(cap & PCI_EXP_DEVCAP_FLR))
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return -ENOTTY;
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if (probe)
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return 0;
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pci_block_user_cfg_access(dev);
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/* Wait for Transaction Pending bit clean */
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pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
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if (!(status & PCI_EXP_DEVSTA_TRPND))
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goto transaction_done;
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for (i = 0; i < 4; i++) {
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if (i)
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msleep((1 << (i - 1)) * 100);
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msleep(100);
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pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
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if (!(status & PCI_EXP_DEVSTA_TRPND))
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goto transaction_done;
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pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
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if (!(status & PCI_EXP_DEVSTA_TRPND))
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goto clear;
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}
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dev_info(&dev->dev, "Busy after 100ms while trying to reset; "
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"sleeping for 1 second\n");
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ssleep(1);
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pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
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if (status & PCI_EXP_DEVSTA_TRPND)
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dev_info(&dev->dev, "Still busy after 1s; "
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"proceeding with reset anyway\n");
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dev_err(&dev->dev, "transaction is not cleared; "
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"proceeding with reset anyway\n");
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transaction_done:
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pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL,
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clear:
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pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
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PCI_EXP_DEVCTL_BCR_FLR);
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mdelay(100);
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msleep(100);
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pci_unblock_user_cfg_access(dev);
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return 0;
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}
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static int __pci_af_flr(struct pci_dev *dev, int probe)
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static int pci_af_flr(struct pci_dev *dev, int probe)
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{
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int cappos = pci_find_capability(dev, PCI_CAP_ID_AF);
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u8 status;
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int i;
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int pos;
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u8 cap;
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u8 status;
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if (!cappos)
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pos = pci_find_capability(dev, PCI_CAP_ID_AF);
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if (!pos)
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return -ENOTTY;
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pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap);
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pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
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if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
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return -ENOTTY;
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if (probe)
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return 0;
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pci_block_user_cfg_access(dev);
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/* Wait for Transaction Pending bit clean */
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pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
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if (!(status & PCI_AF_STATUS_TP))
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goto transaction_done;
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for (i = 0; i < 4; i++) {
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if (i)
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msleep((1 << (i - 1)) * 100);
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pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
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if (!(status & PCI_AF_STATUS_TP))
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goto clear;
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}
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dev_err(&dev->dev, "transaction is not cleared; "
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"proceeding with reset anyway\n");
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clear:
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pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
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msleep(100);
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pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
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if (!(status & PCI_AF_STATUS_TP))
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goto transaction_done;
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dev_info(&dev->dev, "Busy after 100ms while trying to"
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" reset; sleeping for 1 second\n");
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ssleep(1);
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pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
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if (status & PCI_AF_STATUS_TP)
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dev_info(&dev->dev, "Still busy after 1s; "
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"proceeding with reset anyway\n");
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transaction_done:
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pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
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mdelay(100);
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pci_unblock_user_cfg_access(dev);
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return 0;
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}
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static int __pci_reset_function(struct pci_dev *pdev, int probe)
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static int pci_pm_reset(struct pci_dev *dev, int probe)
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{
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int res;
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u16 csr;
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res = __pcie_flr(pdev, probe);
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if (res != -ENOTTY)
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return res;
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if (!dev->pm_cap)
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return -ENOTTY;
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res = __pci_af_flr(pdev, probe);
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if (res != -ENOTTY)
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return res;
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pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
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if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
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return -ENOTTY;
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return res;
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if (probe)
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return 0;
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if (dev->current_state != PCI_D0)
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return -EINVAL;
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csr &= ~PCI_PM_CTRL_STATE_MASK;
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csr |= PCI_D3hot;
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pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
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msleep(pci_pm_d3_delay);
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csr &= ~PCI_PM_CTRL_STATE_MASK;
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csr |= PCI_D0;
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pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
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msleep(pci_pm_d3_delay);
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return 0;
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}
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static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
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{
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u16 ctrl;
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struct pci_dev *pdev;
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if (dev->subordinate)
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return -ENOTTY;
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list_for_each_entry(pdev, &dev->bus->devices, bus_list)
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if (pdev != dev)
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return -ENOTTY;
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if (probe)
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return 0;
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pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
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ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
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msleep(100);
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ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
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msleep(100);
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return 0;
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}
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static int pci_dev_reset(struct pci_dev *dev, int probe)
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{
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int rc;
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might_sleep();
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if (!probe) {
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pci_block_user_cfg_access(dev);
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/* block PM suspend, driver probe, etc. */
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down(&dev->dev.sem);
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}
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rc = pcie_flr(dev, probe);
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if (rc != -ENOTTY)
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goto done;
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rc = pci_af_flr(dev, probe);
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if (rc != -ENOTTY)
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goto done;
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rc = pci_pm_reset(dev, probe);
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if (rc != -ENOTTY)
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goto done;
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rc = pci_parent_bus_reset(dev, probe);
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done:
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if (!probe) {
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up(&dev->dev.sem);
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pci_unblock_user_cfg_access(dev);
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}
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return rc;
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}
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/**
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* pci_execute_reset_function() - Reset a PCI device function
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* @dev: Device function to reset
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* __pci_reset_function - reset a PCI device function
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* @dev: PCI device to reset
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*
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* Some devices allow an individual function to be reset without affecting
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* other functions in the same device. The PCI device must be responsive
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@@ -2174,18 +2241,18 @@ static int __pci_reset_function(struct pci_dev *pdev, int probe)
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* device including MSI, bus mastering, BARs, decoding IO and memory spaces,
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* etc.
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*
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* Returns 0 if the device function was successfully reset or -ENOTTY if the
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* Returns 0 if the device function was successfully reset or negative if the
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* device doesn't support resetting a single function.
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*/
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int pci_execute_reset_function(struct pci_dev *dev)
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int __pci_reset_function(struct pci_dev *dev)
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{
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return __pci_reset_function(dev, 0);
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return pci_dev_reset(dev, 0);
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}
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EXPORT_SYMBOL_GPL(pci_execute_reset_function);
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EXPORT_SYMBOL_GPL(__pci_reset_function);
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/**
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* pci_reset_function() - quiesce and reset a PCI device function
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* @dev: Device function to reset
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* pci_reset_function - quiesce and reset a PCI device function
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* @dev: PCI device to reset
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*
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* Some devices allow an individual function to be reset without affecting
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* other functions in the same device. The PCI device must be responsive
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@@ -2193,32 +2260,33 @@ EXPORT_SYMBOL_GPL(pci_execute_reset_function);
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*
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* This function does not just reset the PCI portion of a device, but
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* clears all the state associated with the device. This function differs
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* from pci_execute_reset_function in that it saves and restores device state
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* from __pci_reset_function in that it saves and restores device state
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* over the reset.
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*
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* Returns 0 if the device function was successfully reset or -ENOTTY if the
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* Returns 0 if the device function was successfully reset or negative if the
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* device doesn't support resetting a single function.
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*/
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int pci_reset_function(struct pci_dev *dev)
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{
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int r = __pci_reset_function(dev, 1);
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int rc;
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if (r < 0)
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return r;
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rc = pci_dev_reset(dev, 1);
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if (rc)
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return rc;
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if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
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disable_irq(dev->irq);
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pci_save_state(dev);
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/*
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* both INTx and MSI are disabled after the Interrupt Disable bit
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* is set and the Bus Master bit is cleared.
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*/
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pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
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r = pci_execute_reset_function(dev);
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rc = pci_dev_reset(dev, 0);
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pci_restore_state(dev);
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if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
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enable_irq(dev->irq);
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return r;
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return rc;
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}
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EXPORT_SYMBOL_GPL(pci_reset_function);
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@@ -2591,6 +2659,8 @@ static int __init pci_setup(char *str)
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} else if (!strncmp(str, "resource_alignment=", 19)) {
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pci_set_resource_alignment_param(str + 19,
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strlen(str + 19));
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} else if (!strncmp(str, "ecrc=", 5)) {
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pcie_ecrc_get_policy(str + 5);
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} else {
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printk(KERN_ERR "PCI: Unknown option `%s'\n",
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str);
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Reference in New Issue
Block a user