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ARM: OMAP: Timer32K: Re-organize duplicated 32k-timer code

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On OMAP2/3, the gp-timer code can be used for a 32kHz timer simply by
setting the source to be the 32k clock instead of sys_clk.

This patch uses the mach-omap2/timer-gp.c code for 32kHz timer on
OMAP2, moving the logic into mach-omap2/timer-gp.c, and not using
plat-omap/timer32k.c which, for OMAP2, is redundant with the timer-gp
code.

Also, if CONFIG_OMAP_32K_TIMER is enabled, the gptimer-based
clocksource is not used.  Instead the default 32k sync counter is used
as the clocksource (see the clocksource in plat-omap/common.c.)  This
is important for sleep/suspend so there is a valid counter during
sleep.  Note that the suspend/sleep code needs fixing to check for
overflows of this counter.

In addition, the OMAP2/3 details are removed from timer32k.c leaving
that with only OMAP1 specifics.  A follow-up patch will move it from
plat-omap common code to mach-omap1.

Signed-off-by: Kevin Hilman <khilman@mvista.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Kevin Hilman
2007-11-12 23:24:02 -08:00
committed by Tony Lindgren
parent 225dfda1d6
commit 5a3a388fbe
4 changed files with 141 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/plat-omap/Makefile
View File

@@ -9,7 +9,9 @@ obj-m :=
obj-n :=
obj- :=
ifeq ($(CONFIG_ARCH_OMAP1),y)
obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
endif
# OCPI interconnect support for 1710, 1610 and 5912
obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o

44
arch/arm/plat-omap/timer32k.c
View File

@@ -40,6 +40,7 @@
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clocksource.h>
@@ -93,8 +94,6 @@ struct sys_timer omap_timer;
#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
(((nr_jiffies) * (clock_rate)) / HZ)
#if defined(CONFIG_ARCH_OMAP1)
static inline void omap_32k_timer_write(int val, int reg)
{
omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
@@ -120,30 +119,6 @@ static inline void omap_32k_timer_stop(void)
#define omap_32k_timer_ack_irq()
#elif defined(CONFIG_ARCH_OMAP2)
static struct omap_dm_timer *gptimer;
static inline void omap_32k_timer_start(unsigned long load_val)
{
omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
omap_dm_timer_start(gptimer);
}
static inline void omap_32k_timer_stop(void)
{
omap_dm_timer_stop(gptimer);
}
static inline void omap_32k_timer_ack_irq(void)
{
u32 status = omap_dm_timer_read_status(gptimer);
omap_dm_timer_write_status(gptimer, status);
}
#endif
static void omap_32k_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
@@ -222,23 +197,6 @@ static struct irqaction omap_32k_timer_irq = {
static __init void omap_init_32k_timer(void)
{
if (cpu_class_is_omap1())
setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
#ifdef CONFIG_ARCH_OMAP2
/* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
if (cpu_is_omap24xx()) {
gptimer = omap_dm_timer_request_specific(1);
BUG_ON(gptimer == NULL);
omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
omap_dm_timer_set_int_enable(gptimer,
OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
OMAP_TIMER_INT_MATCH);
}
#endif
clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
NSEC_PER_SEC,
clockevent_32k_timer.shift);