drm/radeon/kms/atom: rework crtc modeset
- clean up tv timing handling - unify SetCRTC_Timing and SetCRTC_UsingDTDTiming Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
committed by
Dave Airlie
Dave Airlie
parent
2606c88608
commit
5a9bcacc0a
@@ -270,59 +270,89 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
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static void
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atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
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SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param)
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struct drm_display_mode *mode)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
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SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
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int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
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u16 misc = 0;
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conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size);
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conv_param.usH_Blanking_Time =
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cpu_to_le16(crtc_param->usH_Blanking_Time);
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conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size);
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conv_param.usV_Blanking_Time =
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cpu_to_le16(crtc_param->usV_Blanking_Time);
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conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset);
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conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
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conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset);
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conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
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conv_param.susModeMiscInfo.usAccess =
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cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
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conv_param.ucCRTC = crtc_param->ucCRTC;
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memset(&args, 0, sizeof(args));
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args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
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args.usH_Blanking_Time =
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cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
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args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
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args.usV_Blanking_Time =
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cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
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args.usH_SyncOffset =
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cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
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args.usH_SyncWidth =
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cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
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args.usV_SyncOffset =
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cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
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args.usV_SyncWidth =
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cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
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/*args.ucH_Border = mode->hborder;*/
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/*args.ucV_Border = mode->vborder;*/
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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misc |= ATOM_VSYNC_POLARITY;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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misc |= ATOM_HSYNC_POLARITY;
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if (mode->flags & DRM_MODE_FLAG_CSYNC)
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misc |= ATOM_COMPOSITESYNC;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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misc |= ATOM_INTERLACE;
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if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
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misc |= ATOM_DOUBLE_CLOCK_MODE;
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args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
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args.ucCRTC = radeon_crtc->crtc_id;
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printk("executing set crtc dtd timing\n");
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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void atombios_crtc_set_timing(struct drm_crtc *crtc,
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SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *
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crtc_param)
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static void atombios_crtc_set_timing(struct drm_crtc *crtc,
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struct drm_display_mode *mode)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
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SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
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int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
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u16 misc = 0;
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conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
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conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
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conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
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conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
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conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
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conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
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conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
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conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
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conv_param.susModeMiscInfo.usAccess =
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cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
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conv_param.ucCRTC = crtc_param->ucCRTC;
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conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
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conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
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conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
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conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
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conv_param.ucReserved = crtc_param->ucReserved;
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memset(&args, 0, sizeof(args));
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args.usH_Total = cpu_to_le16(mode->crtc_htotal);
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args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
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args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
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args.usH_SyncWidth =
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cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
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args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
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args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
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args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
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args.usV_SyncWidth =
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cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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misc |= ATOM_VSYNC_POLARITY;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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misc |= ATOM_HSYNC_POLARITY;
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if (mode->flags & DRM_MODE_FLAG_CSYNC)
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misc |= ATOM_COMPOSITESYNC;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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misc |= ATOM_INTERLACE;
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if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
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misc |= ATOM_DOUBLE_CLOCK_MODE;
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args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
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args.ucCRTC = radeon_crtc->crtc_id;
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printk("executing set crtc timing\n");
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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@@ -602,128 +632,17 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct drm_encoder *encoder;
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SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
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int need_tv_timings = 0;
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bool ret;
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/* TODO color tiling */
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memset(&crtc_timing, 0, sizeof(crtc_timing));
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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/* find tv std */
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if (encoder->crtc == crtc) {
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
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struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
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if (tv_dac) {
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if (tv_dac->tv_std == TV_STD_NTSC ||
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tv_dac->tv_std == TV_STD_NTSC_J ||
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tv_dac->tv_std == TV_STD_PAL_M)
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need_tv_timings = 1;
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else
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need_tv_timings = 2;
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break;
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}
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}
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}
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}
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crtc_timing.ucCRTC = radeon_crtc->crtc_id;
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if (need_tv_timings) {
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ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1,
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&crtc_timing, &adjusted_mode->clock);
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if (ret == false)
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need_tv_timings = 0;
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}
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if (!need_tv_timings) {
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crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
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crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
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crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
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crtc_timing.usH_SyncWidth =
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adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
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crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
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crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
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crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
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crtc_timing.usV_SyncWidth =
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adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
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if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
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}
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atombios_crtc_set_pll(crtc, adjusted_mode);
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atombios_crtc_set_timing(crtc, &crtc_timing);
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atombios_crtc_set_timing(crtc, adjusted_mode);
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if (ASIC_IS_AVIVO(rdev))
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atombios_crtc_set_base(crtc, x, y, old_fb);
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else {
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if (radeon_crtc->crtc_id == 0) {
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SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
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memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
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/* setup FP shadow regs on R4xx */
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crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
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crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
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crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
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crtc_dtd_timing.usH_Blanking_Time =
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adjusted_mode->crtc_hblank_end -
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adjusted_mode->crtc_hdisplay;
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crtc_dtd_timing.usV_Blanking_Time =
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adjusted_mode->crtc_vblank_end -
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adjusted_mode->crtc_vdisplay;
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crtc_dtd_timing.usH_SyncOffset =
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adjusted_mode->crtc_hsync_start -
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adjusted_mode->crtc_hdisplay;
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crtc_dtd_timing.usV_SyncOffset =
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adjusted_mode->crtc_vsync_start -
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adjusted_mode->crtc_vdisplay;
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crtc_dtd_timing.usH_SyncWidth =
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adjusted_mode->crtc_hsync_end -
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adjusted_mode->crtc_hsync_start;
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crtc_dtd_timing.usV_SyncWidth =
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adjusted_mode->crtc_vsync_end -
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adjusted_mode->crtc_vsync_start;
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/* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
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/* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
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if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
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crtc_dtd_timing.susModeMiscInfo.usAccess |=
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ATOM_VSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
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crtc_dtd_timing.susModeMiscInfo.usAccess |=
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ATOM_HSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
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crtc_dtd_timing.susModeMiscInfo.usAccess |=
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ATOM_COMPOSITESYNC;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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crtc_dtd_timing.susModeMiscInfo.usAccess |=
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ATOM_INTERLACE;
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
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crtc_dtd_timing.susModeMiscInfo.usAccess |=
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ATOM_DOUBLE_CLOCK_MODE;
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atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
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}
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if (radeon_crtc->crtc_id == 0)
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atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
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radeon_crtc_set_base(crtc, x, y, old_fb);
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radeon_legacy_atom_set_surface(crtc);
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}
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