MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.
These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S
This commit is contained in:
David Daney
committed by
Ralf Baechle
Ralf Baechle
parent
58f07778ce
commit
5b3b16880f
307
arch/mips/mm/c-octeon.c
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307
arch/mips/mm/c-octeon.c
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2007 Cavium Networks
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/bitops.h>
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#include <linux/cpu.h>
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#include <linux/io.h>
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheops.h>
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#include <asm/cpu-features.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/r4kcache.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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#include <asm/war.h>
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#include <asm/octeon/octeon.h>
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unsigned long long cache_err_dcache[NR_CPUS];
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/**
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* Octeon automatically flushes the dcache on tlb changes, so
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* from Linux's viewpoint it acts much like a physically
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* tagged cache. No flushing is needed
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*
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*/
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static void octeon_flush_data_cache_page(unsigned long addr)
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{
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/* Nothing to do */
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}
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static inline void octeon_local_flush_icache(void)
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{
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asm volatile ("synci 0($0)");
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}
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/*
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* Flush local I-cache for the specified range.
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*/
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static void local_octeon_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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octeon_local_flush_icache();
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}
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/**
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* Flush caches as necessary for all cores affected by a
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* vma. If no vma is supplied, all cores are flushed.
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*
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* @vma: VMA to flush or NULL to flush all icaches.
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*/
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static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
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{
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extern void octeon_send_ipi_single(int cpu, unsigned int action);
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#ifdef CONFIG_SMP
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int cpu;
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cpumask_t mask;
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#endif
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mb();
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octeon_local_flush_icache();
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#ifdef CONFIG_SMP
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preempt_disable();
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cpu = smp_processor_id();
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/*
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* If we have a vma structure, we only need to worry about
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* cores it has been used on
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*/
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if (vma)
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mask = vma->vm_mm->cpu_vm_mask;
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else
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mask = cpu_online_map;
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cpu_clear(cpu, mask);
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for_each_cpu_mask(cpu, mask)
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octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
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preempt_enable();
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#endif
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}
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/**
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* Called to flush the icache on all cores
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*/
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static void octeon_flush_icache_all(void)
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{
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octeon_flush_icache_all_cores(NULL);
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}
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/**
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* Called to flush all memory associated with a memory
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* context.
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*
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* @mm: Memory context to flush
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*/
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static void octeon_flush_cache_mm(struct mm_struct *mm)
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{
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/*
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* According to the R4K version of this file, CPUs without
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* dcache aliases don't need to do anything here
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*/
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}
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/**
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* Flush a range of kernel addresses out of the icache
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*
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*/
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static void octeon_flush_icache_range(unsigned long start, unsigned long end)
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{
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octeon_flush_icache_all_cores(NULL);
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}
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/**
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* Flush the icache for a trampoline. These are used for interrupt
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* and exception hooking.
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*
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* @addr: Address to flush
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*/
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static void octeon_flush_cache_sigtramp(unsigned long addr)
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{
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struct vm_area_struct *vma;
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vma = find_vma(current->mm, addr);
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octeon_flush_icache_all_cores(vma);
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}
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/**
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* Flush a range out of a vma
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*
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* @vma: VMA to flush
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* @start:
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* @end:
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*/
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static void octeon_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (vma->vm_flags & VM_EXEC)
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octeon_flush_icache_all_cores(vma);
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}
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/**
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* Flush a specific page of a vma
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*
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* @vma: VMA to flush page for
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* @page: Page to flush
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* @pfn:
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*/
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static void octeon_flush_cache_page(struct vm_area_struct *vma,
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unsigned long page, unsigned long pfn)
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{
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if (vma->vm_flags & VM_EXEC)
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octeon_flush_icache_all_cores(vma);
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}
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/**
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* Probe Octeon's caches
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*
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*/
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static void __devinit probe_octeon(void)
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{
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unsigned long icache_size;
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unsigned long dcache_size;
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unsigned int config1;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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switch (c->cputype) {
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case CPU_CAVIUM_OCTEON:
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config1 = read_c0_config1();
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c->icache.linesz = 2 << ((config1 >> 19) & 7);
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c->icache.sets = 64 << ((config1 >> 22) & 7);
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c->icache.ways = 1 + ((config1 >> 16) & 7);
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c->icache.flags |= MIPS_CACHE_VTAG;
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icache_size =
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c->icache.sets * c->icache.ways * c->icache.linesz;
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c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
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c->dcache.linesz = 128;
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if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
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c->dcache.sets = 1; /* CN3XXX has one Dcache set */
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else
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c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
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c->dcache.ways = 64;
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dcache_size =
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c->dcache.sets * c->dcache.ways * c->dcache.linesz;
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c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
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c->options |= MIPS_CPU_PREFETCH;
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break;
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default:
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panic("Unsupported Cavium Networks CPU type\n");
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break;
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}
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/* compute a couple of other cache variables */
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c->icache.waysize = icache_size / c->icache.ways;
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c->dcache.waysize = dcache_size / c->dcache.ways;
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c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
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c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
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if (smp_processor_id() == 0) {
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pr_notice("Primary instruction cache %ldkB, %s, %d way, "
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"%d sets, linesize %d bytes.\n",
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icache_size >> 10,
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cpu_has_vtag_icache ?
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"virtually tagged" : "physically tagged",
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c->icache.ways, c->icache.sets, c->icache.linesz);
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pr_notice("Primary data cache %ldkB, %d-way, %d sets, "
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"linesize %d bytes.\n",
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dcache_size >> 10, c->dcache.ways,
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c->dcache.sets, c->dcache.linesz);
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}
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}
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/**
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* Setup the Octeon cache flush routines
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*
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*/
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void __devinit octeon_cache_init(void)
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{
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extern unsigned long ebase;
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extern char except_vec2_octeon;
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memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80);
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octeon_flush_cache_sigtramp(ebase + 0x100);
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probe_octeon();
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shm_align_mask = PAGE_SIZE - 1;
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flush_cache_all = octeon_flush_icache_all;
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__flush_cache_all = octeon_flush_icache_all;
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flush_cache_mm = octeon_flush_cache_mm;
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flush_cache_page = octeon_flush_cache_page;
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flush_cache_range = octeon_flush_cache_range;
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flush_cache_sigtramp = octeon_flush_cache_sigtramp;
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flush_icache_all = octeon_flush_icache_all;
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flush_data_cache_page = octeon_flush_data_cache_page;
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flush_icache_range = octeon_flush_icache_range;
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local_flush_icache_range = local_octeon_flush_icache_range;
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build_clear_page();
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build_copy_page();
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}
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/**
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* Handle a cache error exception
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*/
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static void cache_parity_error_octeon(int non_recoverable)
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{
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unsigned long coreid = cvmx_get_core_num();
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uint64_t icache_err = read_octeon_c0_icacheerr();
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pr_err("Cache error exception:\n");
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pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
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if (icache_err & 1) {
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pr_err("CacheErr (Icache) == %llx\n",
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(unsigned long long)icache_err);
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write_octeon_c0_icacheerr(0);
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}
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if (cache_err_dcache[coreid] & 1) {
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pr_err("CacheErr (Dcache) == %llx\n",
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(unsigned long long)cache_err_dcache[coreid]);
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cache_err_dcache[coreid] = 0;
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}
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if (non_recoverable)
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panic("Can't handle cache error: nested exception");
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}
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/**
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* Called when the the exception is not recoverable
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*/
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asmlinkage void cache_parity_error_octeon_recoverable(void)
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{
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cache_parity_error_octeon(0);
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}
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/**
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* Called when the the exception is recoverable
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*/
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asmlinkage void cache_parity_error_octeon_non_recoverable(void)
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{
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cache_parity_error_octeon(1);
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}
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