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dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors

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Whenever a single or cyclic transaction is prepared, the driver
could eventually split it over several SG descriptors in order
to deal with the HW maximum transfer length.

This could end up in DMA operations starting from a misaligned
address. This seems fatal for the HW if DRE (Data Realignment Engine)
is not enabled.

This patch eventually adjusts the transfer size in order to make sure
all operations start from an aligned address.

Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Andrea Merello 2018-11-20 16:31:46 +01:00 committed by Vinod Koul
parent 616f0f81d8
commit 5c094d4cac
1 changed files with 9 additions and 0 deletions
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9
drivers/dma/xilinx/xilinx_dma.c
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@ -977,6 +977,15 @@ static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
copy = min_t(size_t, size - done,
chan->xdev->max_buffer_len);
if ((copy + done < size) &&
chan->xdev->common.copy_align) {
/*
* If this is not the last descriptor, make sure
* the next one will be properly aligned
*/
copy = rounddown(copy,
(1 << chan->xdev->common.copy_align));
}
return copy;
}