sh: Definitions for 3-level page table layout
If using 64-bit PTEs and 4K pages then each page table has 512 entries (as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows the convention that all structures in the page table (pgd_t, pmd_t, pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require 64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs it is only possible to map 1GB of virtual address space. In order to map all 4GB of virtual address space we need to adopt a 3-level page table layout. This actually works out better for CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2 areas (which are untranslated) instead of 256. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@@ -120,7 +120,13 @@ void __init page_table_range_init(unsigned long start, unsigned long end,
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for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
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pud = (pud_t *)pgd;
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for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) {
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#ifdef __PAGETABLE_PMD_FOLDED
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pmd = (pmd_t *)pud;
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#else
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pmd = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE);
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pud_populate(&init_mm, pud, pmd);
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pmd += k;
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#endif
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for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
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if (pmd_none(*pmd)) {
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pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
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