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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

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* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (158 commits)
  powerpc: Fix CHRP PCI config access for indirect_pci
  powerpc/chrp: Fix detection of Python PCI host bridge on IBM CHRPs
  powerpc: Fix 32-bit SMP boot on CHRP
  powerpc: Fix link errors on 32-bit machines using legacy DMA
  powerpc/pci: Improve detection of unassigned bridge resources
  hvc_console: Fix free_irq in spinlocked section
  powerpc: Get USE_STRICT_MM_TYPECHECKS working again
  powerpc: Reflect the used arguments in machine_init() prototype
  powerpc: Fix DMA offset for non-coherent DMA
  powerpc: fix fsl_upm nand driver modular build
  powerpc/83xx: add NAND support for the MPC8360E-RDK boards
  powerpc: FPGA support for GE Fanuc SBC610
  i2c: MPC8349E-mITX Power Management and GPIO expander driver
  powerpc: reserve two DMA channels for audio in MPC8610 HPCD device tree
  powerpc: document the "fsl,ssi-dma-channel" compatible property
  powerpc: disable CHRP and PMAC support in various defconfigs
  OF: add fsl,mcu-mpc8349emitx to the exception list
  powerpc/83xx: add DS1374 RTC support for the MPC837xE-MDS boards
  powerpc: remove support for bootmem-allocated memory for the DIU driver
  powerpc: remove non-dependent load fsl_booke PTE_64BIT
  ...
This commit is contained in:
Linus Torvalds
2008-10-15 08:07:35 -07:00
parent 278429cff8 6dc6472581
commit 5f2434a66d
325 changed files with 13690 additions and 6717 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/powerpc/00-INDEX
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@@ -18,10 +18,6 @@ mpc52xx.txt
- Linux 2.6.x on MPC52xx family
mpc52xx-device-tree-bindings.txt
- MPC5200 Device Tree Bindings
ppc_htab.txt
- info about the Linux/PPC /proc/ppc_htab entry
smp.txt
- use and state info about Linux/PPC on MP machines
sound.txt
- info on sound support under Linux/PPC
zImage_layout.txt

40
Documentation/powerpc/dts-bindings/fsl/83xx-512x-pci.txt Normal file
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@@ -0,0 +1,40 @@
* Freescale 83xx and 512x PCI bridges
Freescale 83xx and 512x SOCs include the same pci bridge core.
83xx/512x specific notes:
- reg: should contain two address length tuples
The first is for the internal pci bridge registers
The second is for the pci config space access registers
Example (MPC8313ERDB)
pci0: pci@e0008500 {
cell-index = <1>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0E -mini PCI */
0x7000 0x0 0x0 0x1 &ipic 18 0x8
0x7000 0x0 0x0 0x2 &ipic 18 0x8
0x7000 0x0 0x0 0x3 &ipic 18 0x8
0x7000 0x0 0x0 0x4 &ipic 18 0x8
/* IDSEL 0x0F - PCI slot */
0x7800 0x0 0x0 0x1 &ipic 17 0x8
0x7800 0x0 0x0 0x2 &ipic 18 0x8
0x7800 0x0 0x0 0x3 &ipic 17 0x8
0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};

40
Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt Normal file
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@@ -0,0 +1,40 @@
GPIO controllers on MPC8xxx SoCs
This is for the non-QE/CPM/GUTs GPIO controllers as found on
8349, 8572, 8610 and compatible.
Every GPIO controller node must have #gpio-cells property defined,
this information will be used to translate gpio-specifiers.
Required properties:
- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters (currently unused).
- interrupts : Interrupt mapping for GPIO IRQ (currently unused).
- interrupt-parent : Phandle for the interrupt controller that
services interrupts for this device.
- gpio-controller : Marks the port as GPIO controller.
Example of gpio-controller nodes for a MPC8347 SoC:
gpio1: gpio-controller@c00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
reg = <0xc00 0x100>;
interrupts = <74 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
};
gpio2: gpio-controller@d00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
reg = <0xd00 0x100>;
interrupts = <75 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
};
See booting-without-of.txt for details of how to specify GPIO
information for devices.

13
Documentation/powerpc/dts-bindings/fsl/dma.txt
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@@ -20,7 +20,7 @@ Required properties:
- compatible : compatible list, contains 2 entries, first is
"fsl,CHIP-dma-channel", where CHIP is the processor
(mpc8349, mpc8350, etc.) and the second is
"fsl,elo-dma-channel"
"fsl,elo-dma-channel". However, see note below.
- reg : <registers mapping for channel>
- cell-index : dma channel index starts at 0.
@@ -82,7 +82,7 @@ Required properties:
- compatible : compatible list, contains 2 entries, first is
"fsl,CHIP-dma-channel", where CHIP is the processor
(mpc8540, mpc8560, etc.) and the second is
"fsl,eloplus-dma-channel"
"fsl,eloplus-dma-channel". However, see note below.
- cell-index : dma channel index starts at 0.
- reg : <registers mapping for channel>
- interrupts : <interrupt mapping for DMA channel IRQ>
@@ -125,3 +125,12 @@ Example:
interrupts = <17 2>;
};
};
Note on DMA channel compatible properties: The compatible property must say
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
driver (fsldma). Any DMA channel used by fsldma cannot be used by another
DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
channel that should be used for another driver should not use
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
for more information.

23
Documentation/powerpc/dts-bindings/fsl/ssi.txt
View File

@@ -24,6 +24,12 @@ Required properties:
"rj-master" - r.j., SSI is clock master
"ac97-slave" - AC97 mode, SSI is clock slave
"ac97-master" - AC97 mode, SSI is clock master
- fsl,playback-dma: phandle to a node for the DMA channel to use for
playback of audio. This is typically dictated by SOC
design. See the notes below.
- fsl,capture-dma: phandle to a node for the DMA channel to use for
capture (recording) of audio. This is typically dictated
by SOC design. See the notes below.
Optional properties:
- codec-handle : phandle to a 'codec' node that defines an audio
@@ -36,3 +42,20 @@ Child 'codec' node required properties:
Child 'codec' node optional properties:
- clock-frequency : The frequency of the input clock, which typically
comes from an on-board dedicated oscillator.
Notes on fsl,playback-dma and fsl,capture-dma:
On SOCs that have an SSI, specific DMA channels are hard-wired for playback
and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
playback and DMA channel 3 for capture. The developer can choose which
DMA controller to use, but the channels themselves are hard-wired. The
purpose of these two properties is to represent this hardware design.
The device tree nodes for the DMA channels that are referenced by
"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
"fsl,mpc8610-dma-channel") can remain. If these nodes are left as
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
drivers (fsldma) will attempt to use them, and it will conflict with the
sound drivers.

118
Documentation/powerpc/ppc_htab.txt
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@@ -1,118 +0,0 @@
Information about /proc/ppc_htab
=====================================================================
This document and the related code was written by me (Cort Dougan), please
email me (cort@fsmlabs.com) if you have questions, comments or corrections.
Last Change: 2.16.98
This entry in the proc directory is readable by all users but only
writable by root.
The ppc_htab interface is a user level way of accessing the
performance monitoring registers as well as providing information
about the PTE hash table.
1. Reading
Reading this file will give you information about the memory management
hash table that serves as an extended tlb for page translation on the
powerpc. It will also give you information about performance measurement
specific to the cpu that you are using.
Explanation of the 604 Performance Monitoring Fields:
MMCR0 - the current value of the MMCR0 register
PMC1
PMC2 - the value of the performance counters and a
description of what events they are counting
which are based on MMCR0 bit settings.
Explanation of the PTE Hash Table fields:
Size - hash table size in Kb.
Buckets - number of buckets in the table.
Address - the virtual kernel address of the hash table base.
Entries - the number of ptes that can be stored in the hash table.
User/Kernel - how many pte's are in use by the kernel or user at that time.
Overflows - How many of the entries are in their secondary hash location.
Percent full - ratio of free pte entries to in use entries.
Reloads - Count of how many hash table misses have occurred
that were fixed with a reload from the linux tables.
Should always be 0 on 603 based machines.
Non-error Misses - Count of how many hash table misses have occurred
that were completed with the creation of a pte in the linux
tables with a call to do_page_fault().
Error Misses - Number of misses due to errors such as bad address
and permission violations. This includes kernel access of
bad user addresses that are fixed up by the trap handler.
Note that calculation of the data displayed from /proc/ppc_htab takes
a long time and spends a great deal of time in the kernel. It would
be quite hard on performance to read this file constantly. In time
there may be a counter in the kernel that allows successive reads from
this file only after a given amount of time has passed to reduce the
possibility of a user slowing the system by reading this file.
2. Writing
Writing to the ppc_htab allows you to change the characteristics of
the powerpc PTE hash table and setup performance monitoring.
Resizing the PTE hash table is not enabled right now due to many
complications with moving the hash table, rehashing the entries
and many many SMP issues that would have to be dealt with.
Write options to ppc_htab:
- To set the size of the hash table to 64Kb:
echo 'size 64' > /proc/ppc_htab
The size must be a multiple of 64 and must be greater than or equal to
64.
- To turn off performance monitoring:
echo 'off' > /proc/ppc_htab
- To reset the counters without changing what they're counting:
echo 'reset' > /proc/ppc_htab
Note that counting will continue after the reset if it is enabled.
- To count only events in user mode or only in kernel mode:
echo 'user' > /proc/ppc_htab
...or...
echo 'kernel' > /proc/ppc_htab
Note that these two options are exclusive of one another and the
lack of either of these options counts user and kernel.
Using 'reset' and 'off' reset these flags.
- The 604 has 2 performance counters which can each count events from
a specific set of events. These sets are disjoint so it is not
possible to count _any_ combination of 2 events. One event can
be counted by PMC1 and one by PMC2.
To start counting a particular event use:
echo 'event' > /proc/ppc_htab
and choose from these events:
PMC1
----
'ic miss' - instruction cache misses
'dtlb' - data tlb misses (not hash table misses)
PMC2
----
'dc miss' - data cache misses
'itlb' - instruction tlb misses (not hash table misses)
'load miss time' - cycles to complete a load miss
3. Bugs
The PMC1 and PMC2 counters can overflow and give no indication of that
in /proc/ppc_htab.

34
Documentation/powerpc/smp.txt
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@@ -1,34 +0,0 @@
Information about Linux/PPC SMP mode
=====================================================================
This document and the related code was written by me
(Cort Dougan, cort@fsmlabs.com) please email me if you have questions,
comments or corrections.
Last Change: 3.31.99
If you want to help by writing code or testing different hardware please
email me!
1. State of Supported Hardware
PowerSurge Architecture - tested on UMAX s900, Apple 9600
The second processor on this machine boots up just fine and
enters its idle loop. Hopefully a completely working SMP kernel
on this machine will be done shortly.
The code makes the assumption of only two processors. The changes
necessary to work with any number would not be overly difficult but
I don't have any machines with >2 processors so it's not high on my
list of priorities. If anyone else would like do to the work email
me and I can point out the places that need changed. If you have >2
processors and don't want to add support yourself let me know and I
can take a look into it.
BeBox
BeBox support hasn't been added to the 2.1.X kernels from 2.0.X
but work is being done and SMP support for BeBox is in the works.
CHRP
CHRP SMP works and is fairly solid. It's been tested on the IBM F50
with 4 processors for quite some time now.