[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Haavard Skinnemoen
committed by
Linus Torvalds
Linus Torvalds
parent
53e62d3aaa
commit
5f97f7f940
378
arch/avr32/mm/tlb.c
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378
arch/avr32/mm/tlb.c
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/*
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* AVR32 TLB operations
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*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#define _TLBEHI_I 0x100
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void show_dtlb_entry(unsigned int index)
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{
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unsigned int tlbehi, tlbehi_save, tlbelo, mmucr, mmucr_save, flags;
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local_irq_save(flags);
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mmucr_save = sysreg_read(MMUCR);
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tlbehi_save = sysreg_read(TLBEHI);
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mmucr = mmucr_save & 0x13;
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mmucr |= index << 14;
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sysreg_write(MMUCR, mmucr);
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asm volatile("tlbr" : : : "memory");
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cpu_sync_pipeline();
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tlbehi = sysreg_read(TLBEHI);
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tlbelo = sysreg_read(TLBELO);
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printk("%2u: %c %c %02x %05x %05x %o %o %c %c %c %c\n",
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index,
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(tlbehi & 0x200)?'1':'0',
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(tlbelo & 0x100)?'1':'0',
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(tlbehi & 0xff),
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(tlbehi >> 12), (tlbelo >> 12),
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(tlbelo >> 4) & 7, (tlbelo >> 2) & 3,
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(tlbelo & 0x200)?'1':'0',
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(tlbelo & 0x080)?'1':'0',
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(tlbelo & 0x001)?'1':'0',
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(tlbelo & 0x002)?'1':'0');
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sysreg_write(MMUCR, mmucr_save);
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sysreg_write(TLBEHI, tlbehi_save);
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cpu_sync_pipeline();
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local_irq_restore(flags);
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}
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void dump_dtlb(void)
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{
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unsigned int i;
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printk("ID V G ASID VPN PFN AP SZ C B W D\n");
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for (i = 0; i < 32; i++)
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show_dtlb_entry(i);
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}
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static unsigned long last_mmucr;
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static inline void set_replacement_pointer(unsigned shift)
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{
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unsigned long mmucr, mmucr_save;
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mmucr = mmucr_save = sysreg_read(MMUCR);
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/* Does this mapping already exist? */
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__asm__ __volatile__(
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" tlbs\n"
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" mfsr %0, %1"
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: "=r"(mmucr)
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: "i"(SYSREG_MMUCR));
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if (mmucr & SYSREG_BIT(MMUCR_N)) {
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/* Not found -- pick a not-recently-accessed entry */
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unsigned long rp;
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unsigned long tlbar = sysreg_read(TLBARLO);
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rp = 32 - fls(tlbar);
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if (rp == 32) {
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rp = 0;
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sysreg_write(TLBARLO, -1L);
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}
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mmucr &= 0x13;
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mmucr |= (rp << shift);
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sysreg_write(MMUCR, mmucr);
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}
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last_mmucr = mmucr;
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}
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static void update_dtlb(unsigned long address, pte_t pte, unsigned long asid)
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{
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unsigned long vpn;
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vpn = (address & MMU_VPN_MASK) | _TLBEHI_VALID | asid;
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sysreg_write(TLBEHI, vpn);
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cpu_sync_pipeline();
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set_replacement_pointer(14);
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sysreg_write(TLBELO, pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK);
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/* Let's go */
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asm volatile("nop\n\ttlbw" : : : "memory");
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cpu_sync_pipeline();
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}
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void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t pte)
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{
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unsigned long flags;
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/* ptrace may call this routine */
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if (vma && current->active_mm != vma->vm_mm)
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return;
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local_irq_save(flags);
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update_dtlb(address, pte, get_asid());
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local_irq_restore(flags);
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}
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void __flush_tlb_page(unsigned long asid, unsigned long page)
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{
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unsigned long mmucr, tlbehi;
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page |= asid;
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sysreg_write(TLBEHI, page);
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cpu_sync_pipeline();
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asm volatile("tlbs");
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mmucr = sysreg_read(MMUCR);
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if (!(mmucr & SYSREG_BIT(MMUCR_N))) {
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unsigned long tlbarlo;
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unsigned long entry;
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/* Clear the "valid" bit */
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tlbehi = sysreg_read(TLBEHI);
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tlbehi &= ~_TLBEHI_VALID;
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sysreg_write(TLBEHI, tlbehi);
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cpu_sync_pipeline();
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/* mark the entry as "not accessed" */
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entry = (mmucr >> 14) & 0x3f;
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tlbarlo = sysreg_read(TLBARLO);
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tlbarlo |= (0x80000000 >> entry);
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sysreg_write(TLBARLO, tlbarlo);
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/* update the entry with valid bit clear */
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asm volatile("tlbw");
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cpu_sync_pipeline();
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}
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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if (vma->vm_mm && vma->vm_mm->context != NO_CONTEXT) {
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unsigned long flags, asid;
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unsigned long saved_asid = MMU_NO_ASID;
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asid = vma->vm_mm->context & MMU_CONTEXT_ASID_MASK;
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page &= PAGE_MASK;
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local_irq_save(flags);
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if (vma->vm_mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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__flush_tlb_page(asid, page);
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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local_irq_restore(flags);
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}
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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if (mm->context != NO_CONTEXT) {
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
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mm->context = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm);
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} else {
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unsigned long asid = mm->context & MMU_CONTEXT_ASID_MASK;
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unsigned long saved_asid = MMU_NO_ASID;
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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if (mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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while (start < end) {
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__flush_tlb_page(asid, start);
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start += PAGE_SIZE;
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}
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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}
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/*
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* TODO: If this is only called for addresses > TASK_SIZE, we can probably
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* skip the ASID stuff and just use the Global bit...
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*/
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
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flush_tlb_all();
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} else {
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unsigned long asid = init_mm.context & MMU_CONTEXT_ASID_MASK;
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unsigned long saved_asid = get_asid();
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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set_asid(asid);
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while (start < end) {
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__flush_tlb_page(asid, start);
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start += PAGE_SIZE;
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}
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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/* Invalidate all TLB entries of this process by getting a new ASID */
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if (mm->context != NO_CONTEXT) {
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unsigned long flags;
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local_irq_save(flags);
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mm->context = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm);
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local_irq_restore(flags);
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}
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}
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void flush_tlb_all(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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sysreg_write(MMUCR, sysreg_read(MMUCR) | SYSREG_BIT(MMUCR_I));
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local_irq_restore(flags);
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}
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#ifdef CONFIG_PROC_FS
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#include <linux/seq_file.h>
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#include <linux/proc_fs.h>
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#include <linux/init.h>
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static void *tlb_start(struct seq_file *tlb, loff_t *pos)
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{
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static unsigned long tlb_index;
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if (*pos >= 32)
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return NULL;
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tlb_index = 0;
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return &tlb_index;
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}
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static void *tlb_next(struct seq_file *tlb, void *v, loff_t *pos)
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{
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unsigned long *index = v;
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if (*index >= 31)
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return NULL;
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++*pos;
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++*index;
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return index;
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}
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static void tlb_stop(struct seq_file *tlb, void *v)
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{
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}
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static int tlb_show(struct seq_file *tlb, void *v)
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{
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unsigned int tlbehi, tlbehi_save, tlbelo, mmucr, mmucr_save, flags;
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unsigned long *index = v;
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if (*index == 0)
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seq_puts(tlb, "ID V G ASID VPN PFN AP SZ C B W D\n");
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BUG_ON(*index >= 32);
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local_irq_save(flags);
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mmucr_save = sysreg_read(MMUCR);
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tlbehi_save = sysreg_read(TLBEHI);
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mmucr = mmucr_save & 0x13;
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mmucr |= *index << 14;
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sysreg_write(MMUCR, mmucr);
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asm volatile("tlbr" : : : "memory");
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cpu_sync_pipeline();
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tlbehi = sysreg_read(TLBEHI);
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tlbelo = sysreg_read(TLBELO);
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sysreg_write(MMUCR, mmucr_save);
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sysreg_write(TLBEHI, tlbehi_save);
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cpu_sync_pipeline();
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local_irq_restore(flags);
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seq_printf(tlb, "%2lu: %c %c %02x %05x %05x %o %o %c %c %c %c\n",
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*index,
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(tlbehi & 0x200)?'1':'0',
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(tlbelo & 0x100)?'1':'0',
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(tlbehi & 0xff),
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(tlbehi >> 12), (tlbelo >> 12),
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(tlbelo >> 4) & 7, (tlbelo >> 2) & 3,
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(tlbelo & 0x200)?'1':'0',
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(tlbelo & 0x080)?'1':'0',
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(tlbelo & 0x001)?'1':'0',
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(tlbelo & 0x002)?'1':'0');
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return 0;
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}
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static struct seq_operations tlb_ops = {
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.start = tlb_start,
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.next = tlb_next,
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.stop = tlb_stop,
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.show = tlb_show,
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};
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static int tlb_open(struct inode *inode, struct file *file)
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{
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return seq_open(file, &tlb_ops);
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}
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static struct file_operations proc_tlb_operations = {
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.open = tlb_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = seq_release,
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};
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static int __init proctlb_init(void)
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{
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struct proc_dir_entry *entry;
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entry = create_proc_entry("tlb", 0, NULL);
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if (entry)
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entry->proc_fops = &proc_tlb_operations;
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return 0;
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}
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late_initcall(proctlb_init);
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#endif /* CONFIG_PROC_FS */
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