e1000e: comment corrections
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
committed by
David S. Miller
parent
9e135a2e62
commit
5ff5b66435
@@ -1551,7 +1551,7 @@ bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
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* @hw: pointer to the HW structure
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* @hw: pointer to the HW structure
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* @state: enable/disable locally administered address
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* @state: enable/disable locally administered address
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*
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*
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* Enable/Disable the current locally administers address state.
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* Enable/Disable the current locally administered address state.
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**/
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**/
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void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
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void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
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{
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{
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@@ -1747,7 +1747,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
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if (hsfsts.hsf_status.flcinprog == 0) {
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if (hsfsts.hsf_status.flcinprog == 0) {
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/*
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/*
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* There is no cycle running at present,
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* There is no cycle running at present,
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* so we can start a cycle
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* so we can start a cycle.
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* Begin by setting Flash Cycle Done.
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* Begin by setting Flash Cycle Done.
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*/
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*/
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hsfsts.hsf_status.flcdone = 1;
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hsfsts.hsf_status.flcdone = 1;
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@@ -1755,7 +1755,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
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ret_val = 0;
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ret_val = 0;
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} else {
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} else {
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/*
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/*
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* otherwise poll for sometime so the current
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* Otherwise poll for sometime so the current
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* cycle has a chance to end before giving up.
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* cycle has a chance to end before giving up.
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*/
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*/
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for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
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for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
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@@ -2645,7 +2645,6 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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ctrl |= E1000_CTRL_PHY_RST;
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ctrl |= E1000_CTRL_PHY_RST;
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}
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}
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ret_val = e1000_acquire_swflag_ich8lan(hw);
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ret_val = e1000_acquire_swflag_ich8lan(hw);
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/* Whether or not the swflag was acquired, we need to reset the part */
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e_dbg("Issuing a global reset to ich8lan\n");
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e_dbg("Issuing a global reset to ich8lan\n");
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ew32(CTRL, (ctrl | E1000_CTRL_RST));
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ew32(CTRL, (ctrl | E1000_CTRL_RST));
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msleep(20);
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msleep(20);
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@@ -1086,7 +1086,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
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* 1 | 1 | 0 | 0 | e1000_fc_none
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* 1 | 1 | 0 | 0 | e1000_fc_none
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* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
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* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
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*
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*
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*
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* Are both PAUSE bits set to 1? If so, this implies
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* Are both PAUSE bits set to 1? If so, this implies
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* Symmetric Flow Control is enabled at both ends. The
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* Symmetric Flow Control is enabled at both ends. The
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* ASM_DIR bits are irrelevant per the spec.
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* ASM_DIR bits are irrelevant per the spec.
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@@ -1124,7 +1123,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
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*-------|---------|-------|---------|--------------------
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*-------|---------|-------|---------|--------------------
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* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
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* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
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*
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*/
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*/
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else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
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else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
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(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
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(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
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@@ -1140,7 +1138,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
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*-------|---------|-------|---------|--------------------
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*-------|---------|-------|---------|--------------------
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* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
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* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
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*
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*/
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*/
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else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
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else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
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(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
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(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
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@@ -2363,7 +2360,7 @@ static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
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}
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}
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/**
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/**
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* e1000_mng_host_if_write - Writes to the manageability host interface
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* e1000_mng_host_if_write - Write to the manageability host interface
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* @hw: pointer to the HW structure
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* @hw: pointer to the HW structure
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* @buffer: pointer to the host interface buffer
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* @buffer: pointer to the host interface buffer
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* @length: size of the buffer
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* @length: size of the buffer
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@@ -153,10 +153,10 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
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goto out;
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goto out;
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/*
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/*
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* If the PHY ID is still unknown, we may have an 82577i
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* If the PHY ID is still unknown, we may have an 82577
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* without link. We will try again after setting Slow
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* without link. We will try again after setting Slow MDIC
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* MDIC mode. No harm in trying again in this case since
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* mode. No harm in trying again in this case since the PHY
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* the PHY ID is unknown at this point anyway
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* ID is unknown at this point anyway.
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*/
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*/
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ret_val = phy->ops.acquire(hw);
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ret_val = phy->ops.acquire(hw);
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if (ret_val)
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if (ret_val)
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@@ -1744,7 +1744,7 @@ out:
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* The automatic gain control (agc) normalizes the amplitude of the
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* The automatic gain control (agc) normalizes the amplitude of the
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* received signal, adjusting for the attenuation produced by the
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* received signal, adjusting for the attenuation produced by the
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* cable. By reading the AGC registers, which represent the
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* cable. By reading the AGC registers, which represent the
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* combination of course and fine gain value, the value can be put
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* combination of coarse and fine gain value, the value can be put
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* into a lookup table to obtain the approximate cable length
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* into a lookup table to obtain the approximate cable length
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* for each channel.
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* for each channel.
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**/
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**/
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@@ -1769,7 +1769,7 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
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/*
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/*
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* Getting bits 15:9, which represent the combination of
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* Getting bits 15:9, which represent the combination of
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* course and fine gain values. The result is a number
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* coarse and fine gain values. The result is a number
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* that can be put into the lookup table to obtain the
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* that can be put into the lookup table to obtain the
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* approximate cable length.
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* approximate cable length.
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*/
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*/
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@@ -2511,7 +2511,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
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ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
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ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
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data);
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data);
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} else {
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} else {
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/* Read the page 800 value using opcode 0x12 */
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/* Write the page 800 value using opcode 0x12 */
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ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
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ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
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*data);
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*data);
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}
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}
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