arch/mips/: Spelling fixes
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
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@@ -98,7 +98,7 @@ static __inline__ void
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jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
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{
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/*
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* Convert jiffies to nanoseconds and seperate with
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* Convert jiffies to nanoseconds and separate with
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* one divide.
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*/
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u64 nsec = (u64)jiffies * TICK_NSEC;
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@@ -100,7 +100,7 @@ static inline void
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jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
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{
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/*
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* Convert jiffies to nanoseconds and seperate with
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* Convert jiffies to nanoseconds and separate with
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* one divide.
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*/
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u64 nsec = (u64)jiffies * TICK_NSEC;
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@@ -221,7 +221,7 @@ void sp_work_handle_request(void)
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}
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}
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/* Run the syscall at the priviledge of the user who loaded the
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/* Run the syscall at the privilege of the user who loaded the
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SP program */
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if (vpe_getuid(tclimit))
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@@ -424,13 +424,13 @@ static void __init bootmem_init(void)
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#endif /* CONFIG_SGI_IP27 */
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/*
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* arch_mem_init - initialize memory managment subsystem
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* arch_mem_init - initialize memory management subsystem
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*
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* o plat_mem_setup() detects the memory configuration and will record detected
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* memory areas using add_memory_region.
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*
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* At this stage the memory configuration of the system is known to the
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* kernel but generic memory managment system is still entirely uninitialized.
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* kernel but generic memory management system is still entirely uninitialized.
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*
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* o bootmem_init()
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* o sparse_init()
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@@ -65,7 +65,7 @@ asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
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static atomic_t ipi_timer_latch[NR_CPUS];
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/*
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* Number of InterProcessor Interupt (IPI) message buffers to allocate
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* Number of InterProcessor Interrupt (IPI) message buffers to allocate
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*/
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#define IPIBUF_PER_CPU 4
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@@ -780,7 +780,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
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if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
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if (type == SMTC_CLOCK_TICK)
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atomic_inc(&ipi_timer_latch[cpu]);
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/* If not on same VPE, enqueue and send cross-VPE interupt */
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/* If not on same VPE, enqueue and send cross-VPE interrupt */
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smtc_ipi_nq(&IPIQ[cpu], pipi);
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LOCK_CORE_PRA();
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settc(cpu_data[cpu].tc_id);
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@@ -1063,7 +1063,7 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe)
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return;
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if (!cpu_has_vint)
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panic("SMTC Kernel requires Vectored Interupt support");
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panic("SMTC Kernel requires Vectored Interrupt support");
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set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
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