rt2x00: Implement HW encryption (rt61pci)
rt61pci supports hardware encryption. rt61pci supports up to 4 shared keys and up to 64 pairwise keys. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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John W. Linville
parent
2bb057d07a
commit
61e754f44b
@ -134,6 +134,16 @@
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#define PAIRWISE_KEY_TABLE_BASE 0x1200
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#define PAIRWISE_TA_TABLE_BASE 0x1a00
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#define SHARED_KEY_ENTRY(__idx) \
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( SHARED_KEY_TABLE_BASE + \
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((__idx) * sizeof(struct hw_key_entry)) )
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#define PAIRWISE_KEY_ENTRY(__idx) \
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( PAIRWISE_KEY_TABLE_BASE + \
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((__idx) * sizeof(struct hw_key_entry)) )
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#define PAIRWISE_TA_ENTRY(__idx) \
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( PAIRWISE_TA_TABLE_BASE + \
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((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
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struct hw_key_entry {
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u8 key[16];
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u8 tx_mic[8];
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@ -142,7 +152,8 @@ struct hw_key_entry {
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struct hw_pairwise_ta_entry {
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u8 address[6];
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u8 reserved[2];
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u8 cipher;
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u8 reserved;
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} __attribute__ ((packed));
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/*
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@ -662,6 +673,10 @@ struct hw_pairwise_ta_entry {
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* SEC_CSR4: Pairwise key table lookup control.
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*/
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#define SEC_CSR4 0x30b0
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#define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
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#define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
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#define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
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#define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
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/*
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* SEC_CSR5: shared key table security mode register.
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@ -1428,8 +1443,10 @@ struct hw_pairwise_ta_entry {
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/*
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* Word4
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* ICV: Received ICV of originally encrypted.
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* NOTE: This is a guess, the official definition is "reserved"
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*/
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#define RXD_W4_RESERVED FIELD32(0xffffffff)
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#define RXD_W4_ICV FIELD32(0xffffffff)
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/*
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* the above 20-byte is called RXINFO and will be DMAed to MAC RX block
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