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ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310

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The L310 cache controller's interface is almost identical
to the L210. One major difference is that the PL310 can
have up to 16 ways.

This change uses the cache's part ID and the Associativity
bits in the AUX_CTRL register to determine the number of ways.

Also, this version prints out the CACHE_ID and AUX_CTRL registers.

Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Jason McMullan
2010-05-05 18:59:37 +01:00
committed by Russell King
parent a2227120ee
commit 64039be822
2 changed files with 37 additions and 5 deletions
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3
arch/arm/include/asm/hardware/cache-l2x0.h
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@@ -21,6 +21,9 @@
#define __ASM_ARM_HARDWARE_L2X0_H
#define L2X0_CACHE_ID 0x000
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
#define L2X0_CACHE_ID_PART_L210 (1 << 6)
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104