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[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

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It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2007-10-11 23:46:05 +01:00
parent 424b28ba4d
commit 641e97f318
11 changed files with 54 additions and 577 deletions
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8
arch/mips/kernel/cpu-probe.c
View File

@@ -746,14 +746,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
{
decode_configs(c);
/*
* For historical reasons the SB1 comes with it's own variant of
* cache code which eventually will be folded into c-r4k.c. Until
* then we pretend it's got it's own cache architecture.
*/
c->options &= ~MIPS_CPU_4K_CACHE;
c->options |= MIPS_CPU_SB1_CACHE;
switch (c->processor_id & 0xff00) {
case PRID_IMP_SB1:
c->cputype = CPU_SB1;

6
arch/mips/kernel/traps.c
View File

@@ -1435,6 +1435,9 @@ void __init set_handler (unsigned long offset, void *addr, unsigned long size)
flush_icache_range(ebase + offset, ebase + offset + size);
}
static char panic_null_cerr[] __initdata =
"Trying to set NULL cache error exception handler";
/* Install uncached CPU exception handler */
void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
{
@@ -1445,6 +1448,9 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon
unsigned long uncached_ebase = TO_UNCAC(ebase);
#endif
if (!addr)
panic(panic_null_cerr);
memcpy((void *)(uncached_ebase + offset), addr, size);
}