MIPS: Netlogic: Add XLP platform files for XLP SoC
- Update common files to support XLP. - Add arch/mips/include/asm/netlogic/xlp-hal for register definitions and access macros - Add arch/mips/netlogic/xlp/ for XLP specific files. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jayachandran C
committed by
Ralf Baechle
Ralf Baechle
parent
a3d4fb2d2a
commit
65040e224e
@@ -38,13 +38,22 @@
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#include <asm/mipsregs.h>
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#include <asm/netlogic/haldefs.h>
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#if defined(CONFIG_CPU_XLP)
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/uart.h>
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#elif defined(CONFIG_CPU_XLR)
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#include <asm/netlogic/xlr/iomap.h>
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#endif
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void prom_putchar(char c)
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{
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uint64_t uartbase;
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#if defined(CONFIG_CPU_XLP)
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uartbase = nlm_get_uart_regbase(0, 0);
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#elif defined(CONFIG_CPU_XLR)
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uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
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#endif
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while (nlm_read_reg(uartbase, UART_LSR) == 0)
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;
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nlm_write_reg(uartbase, UART_TX, c);
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@@ -53,8 +53,16 @@
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#if defined(CONFIG_CPU_XLP)
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#elif defined(CONFIG_CPU_XLR)
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#include <asm/netlogic/xlr/iomap.h>
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#include <asm/netlogic/xlr/pic.h>
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#else
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#error "Unknown CPU"
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#endif
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/*
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* These are the routines that handle all the low level interrupt stuff.
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* Actions handled here are: initialization of the interrupt map, requesting of
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@@ -45,8 +45,15 @@
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#if defined(CONFIG_CPU_XLP)
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#elif defined(CONFIG_CPU_XLR)
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#include <asm/netlogic/xlr/iomap.h>
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#include <asm/netlogic/xlr/pic.h>
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#else
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#error "Unknown CPU"
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#endif
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void nlm_send_ipi_single(int logical_cpu, unsigned int action)
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{
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@@ -70,15 +77,15 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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/* IRQ_IPI_SMP_FUNCTION Handler */
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void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
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{
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smp_call_function_interrupt();
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write_c0_eirr(1ull << irq);
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smp_call_function_interrupt();
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}
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/* IRQ_IPI_SMP_RESCHEDULE handler */
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void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
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{
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scheduler_ipi();
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write_c0_eirr(1ull << irq);
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scheduler_ipi();
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}
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/*
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@@ -86,9 +93,10 @@ void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
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*/
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void nlm_early_init_secondary(int cpu)
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{
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change_c0_config(CONF_CM_CMASK, 0x3);
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write_c0_ebase((uint32_t)nlm_common_ebase);
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#ifdef NLM_XLP
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if (cpu % 4 == 0)
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#ifdef CONFIG_CPU_XLP
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if (hard_smp_processor_id() % 4 == 0)
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xlp_mmu_init();
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#endif
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}
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105
arch/mips/netlogic/xlp/nlm_hal.c
Normal file
105
arch/mips/netlogic/xlp/nlm_hal.c
Normal file
@@ -0,0 +1,105 @@
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <asm/mipsregs.h>
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#include <asm/time.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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/* These addresses are computed by the nlm_hal_init() */
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uint64_t nlm_io_base;
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uint64_t nlm_sys_base;
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uint64_t nlm_pic_base;
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/* Main initialization */
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void nlm_hal_init(void)
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{
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nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
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nlm_sys_base = nlm_get_sys_regbase(0); /* node 0 */
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nlm_pic_base = nlm_get_pic_regbase(0); /* node 0 */
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}
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int nlm_irq_to_irt(int irq)
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{
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if (!PIC_IRQ_IS_IRT(irq))
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return -1;
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switch (irq) {
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case PIC_UART_0_IRQ:
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return PIC_IRT_UART_0_INDEX;
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case PIC_UART_1_IRQ:
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return PIC_IRT_UART_1_INDEX;
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default:
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return -1;
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}
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}
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int nlm_irt_to_irq(int irt)
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{
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switch (irt) {
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case PIC_IRT_UART_0_INDEX:
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return PIC_UART_0_IRQ;
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case PIC_IRT_UART_1_INDEX:
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return PIC_UART_1_IRQ;
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default:
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return -1;
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}
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}
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unsigned int nlm_get_cpu_frequency(void)
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{
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unsigned int pll_divf, pll_divr, dfs_div, denom;
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unsigned int val;
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uint64_t num;
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val = nlm_read_sys_reg(nlm_sys_base, SYS_POWER_ON_RESET_CFG);
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pll_divf = (val >> 10) & 0x7f;
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pll_divr = (val >> 8) & 0x3;
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dfs_div = (val >> 17) & 0x3;
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num = pll_divf + 1;
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denom = 3 * (pll_divr + 1) * (1 << (dfs_div + 1));
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num = num * 800000000ULL;
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do_div(num, denom);
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return (unsigned int)num;
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}
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108
arch/mips/netlogic/xlp/platform.c
Normal file
108
arch/mips/netlogic/xlp/platform.c
Normal file
@@ -0,0 +1,108 @@
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#include <linux/pci.h>
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#include <linux/serial_reg.h>
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#include <linux/spinlock.h>
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#include <asm/time.h>
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#include <asm/addrspace.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/uart.h>
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static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
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{
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return nlm_read_reg(p->iobase, offset);
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}
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static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
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{
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nlm_write_reg(p->iobase, offset, value);
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}
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#define PORT(_irq) \
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{ \
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.irq = _irq, \
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.regshift = 2, \
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.iotype = UPIO_MEM32, \
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.flags = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\
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UPF_BOOT_AUTOCONF), \
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.uartclk = XLP_IO_CLK, \
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.type = PORT_16550A, \
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.serial_in = nlm_xlp_uart_in, \
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.serial_out = nlm_xlp_uart_out, \
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}
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static struct plat_serial8250_port xlp_uart_data[] = {
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PORT(PIC_UART_0_IRQ),
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PORT(PIC_UART_1_IRQ),
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{},
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};
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static struct platform_device uart_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = xlp_uart_data,
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},
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};
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static int __init nlm_platform_uart_init(void)
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{
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unsigned long mmio;
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mmio = (unsigned long)nlm_get_uart_regbase(0, 0);
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xlp_uart_data[0].iobase = mmio;
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xlp_uart_data[0].membase = (void __iomem *)mmio;
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xlp_uart_data[0].mapbase = mmio;
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mmio = (unsigned long)nlm_get_uart_regbase(0, 1);
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xlp_uart_data[1].iobase = mmio;
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xlp_uart_data[1].membase = (void __iomem *)mmio;
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xlp_uart_data[1].mapbase = mmio;
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return platform_device_register(&uart_device);
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}
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arch_initcall(nlm_platform_uart_init);
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101
arch/mips/netlogic/xlp/setup.c
Normal file
101
arch/mips/netlogic/xlp/setup.c
Normal file
@@ -0,0 +1,101 @@
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
|
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* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
|
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*
|
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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*/
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#include <linux/kernel.h>
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#include <linux/serial_8250.h>
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#include <linux/pm.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/bootinfo.h>
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#include <linux/of_fdt.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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unsigned long nlm_common_ebase = 0x0;
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static void nlm_linux_exit(void)
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{
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nlm_write_sys_reg(nlm_sys_base, SYS_CHIP_RESET, 1);
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for ( ; ; )
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cpu_wait();
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}
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void __init plat_mem_setup(void)
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{
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panic_timeout = 5;
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_machine_restart = (void (*)(char *))nlm_linux_exit;
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_machine_halt = nlm_linux_exit;
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pm_power_off = nlm_linux_exit;
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}
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const char *get_system_type(void)
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{
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return "Netlogic XLP Series";
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}
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void __init prom_free_prom_memory(void)
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{
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/* Nothing yet */
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}
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void xlp_mmu_init(void)
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{
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write_c0_config6(read_c0_config6() | 0x24);
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current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
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write_c0_config7(PM_DEFAULT_MASK >>
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(13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
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}
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void __init prom_init(void)
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{
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void *fdtp;
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fdtp = (void *)(long)fw_arg0;
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xlp_mmu_init();
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nlm_hal_init();
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early_init_devtree(fdtp);
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nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
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#ifdef CONFIG_SMP
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nlm_wakeup_secondary_cpus(0xffffffff);
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register_smp_ops(&nlm_smp_ops);
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#endif
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}
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217
arch/mips/netlogic/xlp/smpboot.S
Normal file
217
arch/mips/netlogic/xlp/smpboot.S
Normal file
@@ -0,0 +1,217 @@
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/stackframe.h>
|
||||
#include <asm/asmmacro.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#include <asm/netlogic/xlp-hal/iomap.h>
|
||||
#include <asm/netlogic/xlp-hal/xlp.h>
|
||||
#include <asm/netlogic/xlp-hal/sys.h>
|
||||
#include <asm/netlogic/xlp-hal/cpucontrol.h>
|
||||
|
||||
#define CP0_EBASE $15
|
||||
#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
|
||||
XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
|
||||
SYS_CPU_NONCOHERENT_MODE * 4
|
||||
|
||||
.macro __config_lsu
|
||||
li t0, LSU_DEFEATURE
|
||||
mfcr t1, t0
|
||||
|
||||
lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
|
||||
or t1, t1, t2
|
||||
li t2, ~0xe /* S1RCM */
|
||||
and t1, t1, t2
|
||||
mtcr t1, t0
|
||||
|
||||
li t0, SCHED_DEFEATURE
|
||||
lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */
|
||||
mtcr t1, t0
|
||||
.endm
|
||||
|
||||
.set noreorder
|
||||
.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
|
||||
|
||||
__CPUINIT
|
||||
EXPORT(nlm_reset_entry)
|
||||
mfc0 t0, CP0_EBASE, 1
|
||||
mfc0 t1, CP0_EBASE, 1
|
||||
srl t1, 5
|
||||
andi t1, 0x3 /* t1 <- node */
|
||||
li t2, 0x40000
|
||||
mul t3, t2, t1 /* t3 = node * 0x40000 */
|
||||
srl t0, t0, 2
|
||||
and t0, t0, 0x7 /* t0 <- core */
|
||||
li t1, 0x1
|
||||
sll t0, t1, t0
|
||||
nor t0, t0, zero /* t0 <- ~(1 << core) */
|
||||
li t2, SYS_CPU_COHERENT_BASE(0)
|
||||
add t2, t2, t3 /* t2 <- SYS offset for node */
|
||||
lw t1, 0(t2)
|
||||
and t1, t1, t0
|
||||
sw t1, 0(t2)
|
||||
|
||||
/* read back to ensure complete */
|
||||
lw t1, 0(t2)
|
||||
sync
|
||||
|
||||
/* Configure LSU on Non-0 Cores. */
|
||||
__config_lsu
|
||||
|
||||
/*
|
||||
* Wake up sibling threads from the initial thread in
|
||||
* a core.
|
||||
*/
|
||||
EXPORT(nlm_boot_siblings)
|
||||
li t0, CKSEG1ADDR(RESET_DATA_PHYS)
|
||||
lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
|
||||
li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
|
||||
mfcr t2, t0
|
||||
or t2, t2, t1
|
||||
mtcr t2, t0
|
||||
|
||||
/*
|
||||
* The new hardware thread starts at the next instruction
|
||||
* For all the cases other than core 0 thread 0, we will
|
||||
* jump to the secondary wait function.
|
||||
*/
|
||||
mfc0 v0, CP0_EBASE, 1
|
||||
andi v0, 0x7f /* v0 <- node/core */
|
||||
|
||||
#if 1
|
||||
/* A0 errata - Write MMU_SETUP after changing thread mode register. */
|
||||
andi v1, v0, 0x3 /* v1 <- thread id */
|
||||
bnez v1, 2f
|
||||
nop
|
||||
|
||||
li t0, MMU_SETUP
|
||||
li t1, 0
|
||||
mtcr t1, t0
|
||||
ehb
|
||||
#endif
|
||||
|
||||
2: beqz v0, 3f
|
||||
nop
|
||||
|
||||
/* setup status reg */
|
||||
mfc0 t1, CP0_STATUS
|
||||
li t0, ST0_BEV
|
||||
or t1, t0
|
||||
xor t1, t0
|
||||
#ifdef CONFIG_64BIT
|
||||
ori t1, ST0_KX
|
||||
#endif
|
||||
mtc0 t1, CP0_STATUS
|
||||
|
||||
/* SETUP TLBs for a mapped kernel here */
|
||||
PTR_LA t0, prom_pre_boot_secondary_cpus
|
||||
jalr t0
|
||||
nop
|
||||
|
||||
/*
|
||||
* For the boot CPU, we have to restore registers and
|
||||
* return
|
||||
*/
|
||||
3: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
|
||||
li t1, 0xfadebeef
|
||||
dmtc0 t1, $4, 2 /* restore SP from UserLocal */
|
||||
PTR_SUBU sp, t0, PT_SIZE
|
||||
RESTORE_ALL
|
||||
jr ra
|
||||
nop
|
||||
EXPORT(nlm_reset_entry_end)
|
||||
|
||||
EXPORT(nlm_boot_core0_siblings) /* "Master" (n0c0t0) cpu starts from here */
|
||||
__config_lsu
|
||||
dmtc0 sp, $4, 2 /* SP saved in UserLocal */
|
||||
SAVE_ALL
|
||||
sync
|
||||
/* find the location to which nlm_boot_siblings was relocated */
|
||||
li t0, CKSEG1ADDR(RESET_VEC_PHYS)
|
||||
dla t1, nlm_reset_entry
|
||||
dla t2, nlm_boot_siblings
|
||||
dsubu t2, t1
|
||||
daddu t2, t0
|
||||
/* call it */
|
||||
jr t2
|
||||
nop
|
||||
__FINIT
|
||||
|
||||
__CPUINIT
|
||||
NESTED(prom_pre_boot_secondary_cpus, 16, sp)
|
||||
.set mips64
|
||||
mfc0 a0, CP0_EBASE, 1 /* read ebase */
|
||||
andi a0, 0x3ff /* a0 has the processor_id() */
|
||||
sll t0, a0, 2 /* offset in cpu array */
|
||||
|
||||
PTR_LA t1, nlm_cpu_ready /* mark CPU ready */
|
||||
PTR_ADDU t1, t0
|
||||
li t2, 1
|
||||
sw t2, 0(t1)
|
||||
|
||||
PTR_LA t1, nlm_cpu_unblock
|
||||
PTR_ADDU t1, t0
|
||||
1: lw t2, 0(t1) /* wait till unblocked */
|
||||
bnez t2, 2f
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
j 1b
|
||||
nop
|
||||
|
||||
2: PTR_LA t1, nlm_next_sp
|
||||
PTR_L sp, 0(t1)
|
||||
PTR_LA t1, nlm_next_gp
|
||||
PTR_L gp, 0(t1)
|
||||
|
||||
/* a0 has the processor id */
|
||||
PTR_LA t0, nlm_early_init_secondary
|
||||
jalr t0
|
||||
nop
|
||||
|
||||
PTR_LA t0, smp_bootstrap
|
||||
jr t0
|
||||
nop
|
||||
END(prom_pre_boot_secondary_cpus)
|
||||
__FINIT
|
||||
149
arch/mips/netlogic/xlp/wakeup.c
Normal file
149
arch/mips/netlogic/xlp/wakeup.c
Normal file
@@ -0,0 +1,149 @@
|
||||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/threads.h>
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/string.h>
|
||||
|
||||
#include <asm/netlogic/haldefs.h>
|
||||
#include <asm/netlogic/common.h>
|
||||
#include <asm/netlogic/mips-extns.h>
|
||||
|
||||
#include <asm/netlogic/xlp-hal/iomap.h>
|
||||
#include <asm/netlogic/xlp-hal/pic.h>
|
||||
#include <asm/netlogic/xlp-hal/xlp.h>
|
||||
#include <asm/netlogic/xlp-hal/sys.h>
|
||||
|
||||
unsigned long secondary_entry;
|
||||
uint32_t nlm_coremask;
|
||||
unsigned int nlm_threads_per_core;
|
||||
unsigned int nlm_threadmode;
|
||||
|
||||
static void nlm_enable_secondary_cores(unsigned int cores_bitmap)
|
||||
{
|
||||
uint32_t core, value, coremask;
|
||||
|
||||
for (core = 1; core < 8; core++) {
|
||||
coremask = 1 << core;
|
||||
if ((cores_bitmap & coremask) == 0)
|
||||
continue;
|
||||
|
||||
/* Enable CPU clock */
|
||||
value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
|
||||
value &= ~coremask;
|
||||
nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
|
||||
|
||||
/* Remove CPU Reset */
|
||||
value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
|
||||
value &= ~coremask;
|
||||
nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
|
||||
|
||||
/* Poll for CPU to mark itself coherent */
|
||||
do {
|
||||
value = nlm_read_sys_reg(nlm_sys_base,
|
||||
SYS_CPU_NONCOHERENT_MODE);
|
||||
} while ((value & coremask) != 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void nlm_parse_cpumask(u32 cpu_mask)
|
||||
{
|
||||
uint32_t core0_thr_mask, core_thr_mask;
|
||||
int i;
|
||||
|
||||
core0_thr_mask = cpu_mask & 0xf;
|
||||
switch (core0_thr_mask) {
|
||||
case 1:
|
||||
nlm_threads_per_core = 1;
|
||||
nlm_threadmode = 0;
|
||||
break;
|
||||
case 3:
|
||||
nlm_threads_per_core = 2;
|
||||
nlm_threadmode = 2;
|
||||
break;
|
||||
case 0xf:
|
||||
nlm_threads_per_core = 4;
|
||||
nlm_threadmode = 3;
|
||||
break;
|
||||
default:
|
||||
goto unsupp;
|
||||
}
|
||||
|
||||
/* Verify other cores CPU masks */
|
||||
nlm_coremask = 1;
|
||||
for (i = 1; i < 8; i++) {
|
||||
core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
|
||||
if (core_thr_mask) {
|
||||
if (core_thr_mask != core0_thr_mask)
|
||||
goto unsupp;
|
||||
nlm_coremask |= 1 << i;
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
unsupp:
|
||||
panic("Unsupported CPU mask %x\n", cpu_mask);
|
||||
}
|
||||
|
||||
int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
|
||||
{
|
||||
unsigned long reset_vec;
|
||||
unsigned int *reset_data;
|
||||
|
||||
/* Update reset entry point with CPU init code */
|
||||
reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
|
||||
memcpy((void *)reset_vec, (void *)nlm_reset_entry,
|
||||
(nlm_reset_entry_end - nlm_reset_entry));
|
||||
|
||||
/* verify the mask and setup core config variables */
|
||||
nlm_parse_cpumask(wakeup_mask);
|
||||
|
||||
/* Setup CPU init parameters */
|
||||
reset_data = (unsigned int *)CKSEG1ADDR(RESET_DATA_PHYS);
|
||||
reset_data[BOOT_THREAD_MODE] = nlm_threadmode;
|
||||
|
||||
/* first wakeup core 0 siblings */
|
||||
nlm_boot_core0_siblings();
|
||||
|
||||
/* enable the reset of the cores */
|
||||
nlm_enable_secondary_cores(nlm_coremask);
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user