[XTENSA] Add support for cache-aliasing
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
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@@ -24,6 +24,8 @@
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unsigned long asid_cache = ASID_USER_FIRST;
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void bad_page_fault(struct pt_regs*, unsigned long, int);
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#undef DEBUG_PAGE_FAULT
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/*
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* This routine handles page faults. It determines the address,
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* and the problem, and then passes it off to one of the appropriate
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@@ -64,7 +66,7 @@ void do_page_fault(struct pt_regs *regs)
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exccause == EXCCAUSE_ITLB_MISS ||
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exccause == EXCCAUSE_FETCH_CACHE_ATTRIBUTE) ? 1 : 0;
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#if 0
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#ifdef DEBUG_PAGE_FAULT
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printk("[%s:%d:%08x:%d:%08x:%s%s]\n", current->comm, current->pid,
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address, exccause, regs->pc, is_write? "w":"", is_exec? "x":"");
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#endif
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@@ -219,7 +221,7 @@ bad_page_fault(struct pt_regs *regs, unsigned long address, int sig)
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/* Are we prepared to handle this kernel fault? */
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if ((entry = search_exception_tables(regs->pc)) != NULL) {
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#if 1
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#ifdef DEBUG_PAGE_FAULT
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printk(KERN_DEBUG "%s: Exception at pc=%#010lx (%lx)\n",
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current->comm, regs->pc, entry->fixup);
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#endif
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