[POWERPC] Merge 32 and 64 bits asm-powerpc/io.h
powerpc: Merge 32 and 64 bits asm-powerpc/io.h The rework on io.h done for the new hookable accessors made it easier, so I just finished the work and merged 32 and 64 bits io.h for arch/powerpc. arch/ppc still uses the old version in asm-ppc, there is just too much gunk in there that I really can't be bothered trying to cleanup. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
committed by
Paul Mackerras
Paul Mackerras
parent
3d1ea8e8cb
commit
68a64357d1
@@ -13,24 +13,51 @@
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extern int check_legacy_ioport(unsigned long base_port);
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#define PNPBIOS_BASE 0xf000 /* only relevant for PReP */
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#ifndef CONFIG_PPC64
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#include <asm-ppc/io.h>
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#else
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#include <linux/compiler.h>
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#include <asm/page.h>
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#include <asm/byteorder.h>
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#include <asm/paca.h>
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#include <asm/synch.h>
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#include <asm/delay.h>
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#include <asm/mmu.h>
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#include <asm-generic/iomap.h>
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#ifdef CONFIG_PPC64
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#include <asm/paca.h>
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#endif
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#define SIO_CONFIG_RA 0x398
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#define SIO_CONFIG_RD 0x399
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#define SLOW_DOWN_IO
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/* 32 bits uses slightly different variables for the various IO
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* bases. Most of this file only uses _IO_BASE though which we
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* define properly based on the platform
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*/
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#ifndef CONFIG_PCI
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#define _IO_BASE 0
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#define _ISA_MEM_BASE 0
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#define PCI_DRAM_OFFSET 0
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#elif defined(CONFIG_PPC32)
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#define PCI_DRAM_OFFSET pci_dram_offset
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#else
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#define _IO_BASE pci_io_base
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#define _ISA_MEM_BASE 0
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#define PCI_DRAM_OFFSET 0
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#endif
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extern unsigned long isa_io_base;
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extern unsigned long isa_mem_base;
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extern unsigned long pci_io_base;
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extern unsigned long pci_dram_offset;
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#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
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#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
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#endif
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/*
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*
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* Low level MMIO accessors
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@@ -53,7 +80,11 @@ extern int check_legacy_ioport(unsigned long base_port);
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*
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*/
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#ifdef CONFIG_PPC64
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#define IO_SET_SYNC_FLAG() do { get_paca()->io_sync = 1; } while(0)
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#else
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#define IO_SET_SYNC_FLAG()
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#endif
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#define DEF_MMIO_IN(name, type, insn) \
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static inline type name(const volatile type __iomem *addr) \
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@@ -86,17 +117,19 @@ static inline void name(volatile type __iomem *addr, type val) \
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DEF_MMIO_IN_BE(in_8, 8, lbz);
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DEF_MMIO_IN_BE(in_be16, 16, lhz);
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DEF_MMIO_IN_BE(in_be32, 32, lwz);
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DEF_MMIO_IN_BE(in_be64, 64, ld);
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DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
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DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
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DEF_MMIO_OUT_BE(out_8, 8, stb);
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DEF_MMIO_OUT_BE(out_be16, 16, sth);
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DEF_MMIO_OUT_BE(out_be32, 32, stw);
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DEF_MMIO_OUT_BE(out_be64, 64, std);
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DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
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DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
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#ifdef __powerpc64__
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DEF_MMIO_OUT_BE(out_be64, 64, std);
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DEF_MMIO_IN_BE(in_be64, 64, ld);
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/* There is no asm instructions for 64 bits reverse loads and stores */
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static inline u64 in_le64(const volatile u64 __iomem *addr)
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{
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@@ -107,6 +140,7 @@ static inline void out_le64(volatile u64 __iomem *addr, u64 val)
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{
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out_be64(addr, cpu_to_le64(val));
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}
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#endif /* __powerpc64__ */
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/*
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* Low level IO stream instructions are defined out of line for now
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@@ -126,6 +160,17 @@ extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
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#define _outsw _outsw_ns
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#define _outsl _outsl_ns
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/*
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* memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
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*/
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extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
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extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
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unsigned long n);
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extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
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unsigned long n);
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/*
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*
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* PCI and standard ISA accessors
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@@ -140,9 +185,6 @@ extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
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* of the accessors.
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*/
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extern unsigned long isa_io_base;
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extern unsigned long pci_io_base;
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/*
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* Non ordered and non-swapping "raw" accessors
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@@ -160,10 +202,6 @@ static inline unsigned int __raw_readl(const volatile void __iomem *addr)
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{
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return *(volatile unsigned int __force *)addr;
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}
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static inline unsigned long __raw_readq(const volatile void __iomem *addr)
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{
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return *(volatile unsigned long __force *)addr;
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}
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static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
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{
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*(volatile unsigned char __force *)addr = v;
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@@ -176,11 +214,17 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
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{
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*(volatile unsigned int __force *)addr = v;
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}
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#ifdef __powerpc64__
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static inline unsigned long __raw_readq(const volatile void __iomem *addr)
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{
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return *(volatile unsigned long __force *)addr;
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}
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static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
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{
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*(volatile unsigned long __force *)addr = v;
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}
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#endif /* __powerpc64__ */
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/*
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*
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@@ -188,7 +232,13 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
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*
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*/
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/*
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* Include the EEH definitions when EEH is enabled only so they don't get
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* in the way when building for 32 bits
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*/
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#ifdef CONFIG_EEH
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#include <asm/eeh.h>
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#endif
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/* Shortcut to the MMIO argument pointer */
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#define PCI_IO_ADDR volatile void __iomem *
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@@ -196,7 +246,7 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
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/* Indirect IO address tokens:
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*
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* When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
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* on all IOs.
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* on all IOs. (Note that this is all 64 bits only for now)
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*
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* To help platforms who may need to differenciate MMIO addresses in
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* their hooks, a bitfield is reserved for use by the platform near the
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@@ -241,6 +291,70 @@ do { \
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#define PCI_FIX_ADDR(addr) (addr)
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#endif
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/*
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* On 32 bits, PIO operations have a recovery mechanism in case they trigger
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* machine checks (which they occasionally do when probing non existing
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* IO ports on some platforms, like PowerMac and 8xx).
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* I always found it to be of dubious reliability and I am tempted to get
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* rid of it one of these days. So if you think it's important to keep it,
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* please voice up asap. We never had it for 64 bits and I do not intend
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* to port it over
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*/
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#ifdef CONFIG_PPC32
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#define __do_in_asm(name, op) \
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extern __inline__ unsigned int name(unsigned int port) \
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{ \
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unsigned int x; \
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__asm__ __volatile__( \
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"sync\n" \
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"0:" op " %0,0,%1\n" \
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"1: twi 0,%0,0\n" \
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"2: isync\n" \
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"3: nop\n" \
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"4:\n" \
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".section .fixup,\"ax\"\n" \
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"5: li %0,-1\n" \
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" b 4b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 0b,5b\n" \
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" .long 1b,5b\n" \
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" .long 2b,5b\n" \
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" .long 3b,5b\n" \
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".previous" \
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: "=&r" (x) \
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: "r" (port + _IO_BASE)); \
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return x; \
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}
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#define __do_out_asm(name, op) \
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extern __inline__ void name(unsigned int val, unsigned int port) \
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{ \
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__asm__ __volatile__( \
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"sync\n" \
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"0:" op " %0,0,%1\n" \
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"1: sync\n" \
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"2:\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 0b,2b\n" \
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" .long 1b,2b\n" \
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".previous" \
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: : "r" (val), "r" (port + _IO_BASE)); \
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}
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__do_in_asm(_rec_inb, "lbzx")
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__do_in_asm(_rec_inw, "lhbrx")
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__do_in_asm(_rec_inl, "lwbrx")
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__do_out_asm(_rec_outb, "stbx")
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__do_out_asm(_rec_outw, "sthbrx")
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__do_out_asm(_rec_outl, "stwbrx")
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#endif /* CONFIG_PPC32 */
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/* The "__do_*" operations below provide the actual "base" implementation
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* for each of the defined acccessor. Some of them use the out_* functions
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* directly, some of them still use EEH, though we might change that in the
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@@ -263,6 +377,8 @@ do { \
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#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
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#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
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#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
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#ifdef CONFIG_EEH
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#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
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#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
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#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
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@@ -270,33 +386,64 @@ do { \
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#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
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#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
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#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
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#else /* CONFIG_EEH */
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#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
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#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
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#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
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#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
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#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
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#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
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#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
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#endif /* !defined(CONFIG_EEH) */
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#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)pci_io_base+port);
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#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)pci_io_base+port);
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#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)pci_io_base+port);
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#define __do_inb(port) readb((PCI_IO_ADDR)pci_io_base + port);
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#define __do_inw(port) readw((PCI_IO_ADDR)pci_io_base + port);
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#define __do_inl(port) readl((PCI_IO_ADDR)pci_io_base + port);
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#ifdef CONFIG_PPC32
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#define __do_outb(val, port) _rec_outb(val, port)
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#define __do_outw(val, port) _rec_outw(val, port)
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#define __do_outl(val, port) _rec_outl(val, port)
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#define __do_inb(port) _rec_inb(port)
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#define __do_inw(port) _rec_inw(port)
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#define __do_inl(port) _rec_inl(port)
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#else /* CONFIG_PPC32 */
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#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
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#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
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#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
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#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
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#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
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#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
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#endif /* !CONFIG_PPC32 */
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#ifdef CONFIG_EEH
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#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
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#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
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#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
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#else /* CONFIG_EEH */
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#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
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#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
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#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
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#endif /* !CONFIG_EEH */
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#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
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#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
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#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
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#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)pci_io_base+(p), (b), (n))
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#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)pci_io_base+(p), (b), (n))
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#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)pci_io_base+(p), (b), (n))
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#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)pci_io_base+(p),(b),(n))
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#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)pci_io_base+(p),(b),(n))
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#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)pci_io_base+(p),(b),(n))
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#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
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#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
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#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
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#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
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#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
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#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
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#define __do_memset_io(addr, c, n) eeh_memset_io(PCI_FIX_ADDR(addr), c, n)
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#define __do_memcpy_fromio(dst, src, n) eeh_memcpy_fromio(dst, \
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PCI_FIX_ADDR(src), n)
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#define __do_memcpy_toio(dst, src, n) eeh_memcpy_toio(PCI_FIX_ADDR(dst), \
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src, n)
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#define __do_memset_io(addr, c, n) \
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_memset_io(PCI_FIX_ADDR(addr), c, n)
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#define __do_memcpy_toio(dst, src, n) \
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_memcpy_toio(PCI_FIX_ADDR(dst), src, n)
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#ifdef CONFIG_EEH
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#define __do_memcpy_fromio(dst, src, n) \
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eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
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#else /* CONFIG_EEH */
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#define __do_memcpy_fromio(dst, src, n) \
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_memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
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#endif /* !CONFIG_EEH */
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#ifdef CONFIG_PPC_INDIRECT_IO
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#define DEF_PCI_HOOK(x) x
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@@ -343,15 +490,27 @@ static inline void name at \
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/* Some drivers check for the presence of readq & writeq with
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* a #ifdef, so we make them happy here.
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*/
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#ifdef __powerpc64__
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#define readq readq
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#define writeq writeq
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#endif
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/* Nothing to do for cache stuff x*/
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#ifdef CONFIG_NOT_COHERENT_CACHE
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#define dma_cache_inv(_start,_size) \
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invalidate_dcache_range(_start, (_start + _size))
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#define dma_cache_wback(_start,_size) \
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clean_dcache_range(_start, (_start + _size))
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#define dma_cache_wback_inv(_start,_size) \
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flush_dcache_range(_start, (_start + _size))
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#else /* CONFIG_NOT_COHERENT_CACHE */
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#define dma_cache_inv(_start,_size) do { } while (0)
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#define dma_cache_wback(_start,_size) do { } while (0)
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#define dma_cache_wback_inv(_start,_size) do { } while (0)
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#endif /* !CONFIG_NOT_COHERENT_CACHE */
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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@@ -372,6 +531,9 @@ static inline void name at \
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#define readl_relaxed(addr) readl(addr)
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#define readq_relaxed(addr) readq(addr)
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#ifdef CONFIG_PPC32
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#define mmiowb()
|
||||
#else
|
||||
/*
|
||||
* Enforce synchronisation of stores vs. spin_unlock
|
||||
* (this does it explicitely, though our implementation of spin_unlock
|
||||
@@ -385,6 +547,7 @@ static inline void mmiowb(void)
|
||||
: "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
|
||||
: "memory");
|
||||
}
|
||||
#endif /* !CONFIG_PPC32 */
|
||||
|
||||
static inline void iosync(void)
|
||||
{
|
||||
@@ -453,22 +616,29 @@ static inline void iosync(void)
|
||||
* be hooked (but can be used by a hook on iounmap)
|
||||
*
|
||||
*/
|
||||
extern void __iomem *ioremap(unsigned long address, unsigned long size);
|
||||
extern void __iomem *ioremap_flags(unsigned long address, unsigned long size,
|
||||
extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
|
||||
extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
|
||||
unsigned long flags);
|
||||
#define ioremap_nocache(addr, size) ioremap((addr), (size))
|
||||
extern void iounmap(void __iomem *addr);
|
||||
extern void iounmap(volatile void __iomem *addr);
|
||||
|
||||
extern void __iomem *__ioremap(unsigned long address, unsigned long size,
|
||||
extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
|
||||
unsigned long flags);
|
||||
extern void __iounmap(void __iomem *addr);
|
||||
extern void __iounmap(volatile void __iomem *addr);
|
||||
|
||||
extern int __ioremap_explicit(unsigned long p_addr, unsigned long v_addr,
|
||||
extern int __ioremap_explicit(phys_addr_t p_addr, unsigned long v_addr,
|
||||
unsigned long size, unsigned long flags);
|
||||
extern int __iounmap_explicit(void __iomem *start, unsigned long size);
|
||||
extern int __iounmap_explicit(volatile void __iomem *start,
|
||||
unsigned long size);
|
||||
|
||||
extern void __iomem * reserve_phb_iospace(unsigned long size);
|
||||
|
||||
/* Those are more 32 bits only functions */
|
||||
extern unsigned long iopa(unsigned long addr);
|
||||
extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
|
||||
extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
|
||||
unsigned int size, int flags);
|
||||
|
||||
|
||||
/*
|
||||
* When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
|
||||
@@ -538,7 +708,33 @@ static inline void * phys_to_virt(unsigned long address)
|
||||
*/
|
||||
#define BIO_VMERGE_BOUNDARY 0
|
||||
|
||||
/*
|
||||
* 32 bits still uses virt_to_bus() for it's implementation of DMA
|
||||
* mappings se we have to keep it defined here. We also have some old
|
||||
* drivers (shame shame shame) that use bus_to_virt() and haven't been
|
||||
* fixed yet so I need to define it here.
|
||||
*/
|
||||
#ifdef CONFIG_PPC32
|
||||
|
||||
static inline unsigned long virt_to_bus(volatile void * address)
|
||||
{
|
||||
if (address == NULL)
|
||||
return 0;
|
||||
return __pa(address) + PCI_DRAM_OFFSET;
|
||||
}
|
||||
|
||||
static inline void * bus_to_virt(unsigned long address)
|
||||
{
|
||||
if (address == 0)
|
||||
return NULL;
|
||||
return __va(address - PCI_DRAM_OFFSET);
|
||||
}
|
||||
|
||||
#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
|
||||
|
||||
#endif /* CONFIG_PPC32 */
|
||||
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* CONFIG_PPC64 */
|
||||
#endif /* _ASM_POWERPC_IO_H */
|
||||
|
||||
Reference in New Issue
Block a user